DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-10 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim of U.S. Patent No. 12,417,743. Although the claims at issue are not identical, they are not patentably distinct from each other because the only difference between the Co-pending 12,417,743 claim 1 is the removal of the original third transistor, however the dependent claim 6 provides the identical structure with the same third transistor as an addition emission transistor which is an obvious variation of the co-pending claim 1. Claims 12-10 are rejected as being dependent on claim 1 and is rejected for the same reasons.
Co-pending 12,417,743: claim 1
Instant Application claim 1
Claim 1, a display comprising a plurality of pixels, wherein a pixel in the plurality of pixels comprises:
a first transistor;
a second transistor;
a third transistor;
a light-emitting diode, wherein the first transistor, the second transistor, the third transistor, and the light-emitting diode are connected in series between a first power supply terminal and a second power supply terminal;
a fourth transistor that is coupled to a source of the second transistor; and
a fifth transistor that is coupled to an anode of the light-emitting diode, wherein a gate of the fifth transistor and a gate of the fourth transistor receive a common control signal.
Claim 1, a display comprising a plurality of pixels, wherein a pixel in the plurality of pixels comprises:
a first transistor;
a second transistor;
a light-emitting diode, wherein the first transistor, the second transistor, and the light-emitting diode are connected in series between a first power supply terminal and a second power supply terminal;
a third transistor that is coupled to a source of the second transistor; and
a fourth transistor that is coupled to an anode of the light-emitting diode, wherein a gate of the fourth transistor and a gate of the third transistor receive a common control signal.
Claim 6, the display defined in claim 5, wherein the pixel further comprises: an additional emission transistor, wherein a gate of the first transistor and a gate of the additional emission transistor receive a common emission control signal.
Claims 11-15 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 12 of U.S. Patent No. 12,417,743. Although the claims at issue are not identical, they are not patentably distinct from each other because the instant claim 11 is almost identical to claim 12 of the co-pending ‘743 except for the additional limitation of a fourth, fifth, sixth switching transistor versus fourth, fifth, sixth transistor, since a transistor is a switch by direct functional design it is inherent that the fourth, fifth and sixth transistor are indeed switching an electrical signal. Claim 12-15 are rejected as being dependent on claim 11 and is rejected for the same reasons.
Co-pending 12,417,743: claim 12
Instant claim 11
11. A display pixel comprising:
a first power supply terminal;
a second power supply terminal;
a first transistor, a second transistor, a third transistor, and a light-emitting diode that are connected in series between the first power supply terminal and the second power supply terminal;
a fourth transistor that is coupled between a gate of the second transistor and a signal line;
a fifth transistor that is coupled between a source of the second transistor and a data line; and
a sixth transistor that is coupled between an anode of the light-emitting diode and the signal line.
12. The display pixel defined in claim 11, wherein the first and third transistors are emission transistors and wherein the second transistor is a drive transistor connected between the first and third transistors.
11. A display pixel comprising:
a first power supply terminal;
a second power supply terminal;
a drive transistor, a first emission transistor, a second emission transistor, and a light-emitting diode that are connected in series between the first power supply terminal and the second power supply terminal;
a first switching transistor that is coupled between a gate of the drive transistor and a signal line;
a second switching transistor that is coupled between a source of the drive transistor and a data line; and
a third switching transistor that is coupled between an anode of the light-emitting diode and the signal line.
Claims 16-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 18 of the co-pending U.S. Patent No. 12,417,743. Although the claims at issue are not identical, they are not patentably distinct from each other because the scope of the instant claim 16 is basically the same as the claim 18 only differs in the addition recitation of a different signal line which is apparent the data line being cited in the co-pending claim 16 which is recited to be couple to the fifth transistor which is different. Claim 17-20 are rejected as being dependent on claim 16 and is rejected for the same reasons.
Co-pending 12,417,743: claim 18
Instant application claim 16
16. A display pixel comprising:
a first power supply terminal;
a second power supply terminal;
a first transistor, a second transistor, a third transistor, and a light-emitting diode that are connected in series between the first power supply terminal and the second power supply terminal;
a fourth transistor that is coupled to a gate of the second transistor;
a fifth transistor that is coupled between a source of the second transistor and a data line; and
a sixth transistor that is coupled to an anode of the light-emitting diode, wherein the first, second, third, fifth, and sixth transistors comprise p-channel silicon transistors.
Claim 18, the display pixel defined in claim 16, wherein the fourth transistor is coupled between th gate of the second transistor and a signal line.
16. A display pixel comprising:
a first power supply terminal;
a second power supply terminal;
a first transistor, a second transistor, a third transistor, and a light- emitting diode that are connected in series between the first power supply terminal and the second power supply terminal;
a fourth transistor that is coupled to a gate of the second transistor, wherein a gate of the fourth transistor receives a first control signal;
a fifth transistor that is coupled between a source of the second transistor and a data line, wherein a gate of the fifth transistor receives a second control signal different than the first control signal; and
a sixth transistor that is coupled to an anode of the light-emitting diode, wherein the first, second, third, fifth, and sixth transistors comprise p-channel silicon transistors.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The prior art Chiou (US Pub: 2009/0091264 A1) is cited to teach another design for a emission display pixel circuitry design as seen in figures 1-4 embodiment. The prior art Gupta et al. (US Pub: 2015/0109279 A1) is cited to teach another type of display device with similar driving pixel circuitry in figures 1-5 embodiments.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CALVIN C. MA whose telephone number is (571)270-1713. The examiner can normally be reached on 8:00AM-5:00PM.
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/CALVIN C MA/Primary Examiner, Art Unit 2693 June 27, 2026
20140331791
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