DETAILED ACTION
Claims 1-20 are present for examination.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-13 and 19 of U.S. Patent No. 12,386,745 contains every element of claims 1-20 of the instant application and as such anticipates claims 1-20 of the instant application.
Claim 1 of the present application corresponds to claim 1 of the ‘745 patent, where “A method…” corresponds to claim 1, line 1 of the ‘745 patent; where “identifying a plurality of X-level cell (XLC)…” corresponds to claim 1, lines 3-6 of the ‘745 patent; “allocating a y-level cell (YLC) cache…” corresponds to claim 1, lines 12-13 of the ‘745 patent; and “in response to one or more memory access requests…” corresponds to claim 1, lines 15-16 of the ‘745 patent.
Claim 2 of the present application corresponds to claim 1 of the ‘745 patent, where “wherein y is less than x…” corresponds to claim 1, line 14 of the ‘745 patent.
Claim 3 of the present application corresponds to claim 1 of the ‘745 patent, where “wherein the one or more memory access requests include one or more write requests…” corresponds to claim 1, lines 15-17 of the ‘745 patent.
Claim 4 of the present application corresponds to claim 1 of the ‘745 patent, where “identifying a write shaping status…” corresponds to claim 1, line 3 of the ‘745 patent; and “based on the write shaping status, determining that the electronic device…” corresponds to claim 1, lines 7-9 of the ‘745 patent; and “wherein the YLC cache is allocated in accordance with a determination…” corresponds to claim 1, lines 7-13 of the ‘745 patent.
Claim 5 of the present application corresponds to claims 1 and 2 of the ‘745 patent, where “wherein the electronic device includes a host…” corresponds to claim 1, lines 1-2 of the ‘745 patent; “receiving a notification by the memory device…” corresponds to claim 2, lines 3-4 of the ‘745 patent; and “determining, based on the notification, whether the host device…” corresponds to claim 2, lines 5-11 of the ‘745 patent.
Claim 6 of the present application corresponds to claim 3 of the ‘745 patent, where “wherein the notification comprises at least one of: an identifying controller (IDC) command received during device discovery…” corresponds to claim 3, lines 1-8 of the ‘745 patent.
Claim 7 of the present application corresponds to claim 4 of the ‘745 patent, where “detecting an input/output (I/O) pattern…” corresponds to claim 4, lines 5-6 of the ‘745 patent; and “determining whether the I/O pattern indicates the sequential data regions…” corresponds to claim 4, lines 7-13 of the ‘745 patent.
Claim 8 of the present application corresponds to claim 1 of the ‘745 patent, where “wherein accessing the plurality of XLC memory blocks…” corresponds to claim 1, lines 15-17 of the ‘745 patent.
Claim 9 of the present application corresponds to claim 5 of the ‘745 patent, where “obtaining the data to be stored…” corresponds to claim 5, lines 3-4 of the ‘745 patent; “writing the data in a plurality of memory blocks in the YLC cache…” corresponds to claim 5, lines 6-9 of the ‘745 patent; and “moving the data from the YLC cache to a target memory…” corresponds to claim 5, lines 10-13 of the ‘745 patent.
Claim 10 of the present application corresponds to claim 5 of the ‘745 patent, where “wherein the data is moved from the YLC cache to the target memory block…” corresponds to claim 1, lines 15-17 of the ‘745 patent.
Claim 11 of the present application corresponds to claims 1 and 19 of the ‘745 patent, where “An electronic system…” corresponds to claim 1, line 1-2 and claim 19, line 1 of the ‘745 patent; “a host device…” corresponds to claim 1, lines 1-2 and claim 19, line 2 of the ‘745 patent; “a memory device coupled to the host device…” corresponds to claim 1, lines 2 and claim 19, lines 3-4 of the ‘745 patent; “identifying a plurality of X-level cell (XLC)…” corresponds to claim 1, lines 3-6 and claim 19, lines 5-8 of the ‘745 patent; “allocating a y-level cell (YLC) cache…” corresponds to claim 1, lines 12-13 and claim 19, lines 14-15 of the ‘745 patent; and “in response to one or more memory access requests…” corresponds to claim 1, lines 15-16 and claim 19, line 17-19 of the ‘745 patent.
Claim 12 of the present application corresponds to claim 6 of the ‘745 patent, where “monitor memory access environment…” corresponds to claim 6, lines 2-3 of the ‘745 patent; and “dynamically adjust a size of the YLC cache…” corresponds to claim 6, lines 4-5 of the ‘745 patent.
Claim 13 of the present application corresponds to claim 7 of the ‘745 patent, where “wherein the memory access environment information comprises at least one of: information related to an identity controller (IDC) command…” corresponds to claim 7, lines 1-7 of the ‘745 patent.
Claim 14 of the present application corresponds to claim 11 of the ‘745 patent, where “wherein the memory access environment information is monitored…” corresponds to claim 11, lines 1-3 of the ‘745 patent.
Claim 15 of the present application corresponds to claim 8 of the ‘745 patent, where “monitor a write workload…” corresponds to claim 8, line 2 of the ‘745 patent; and “dynamically adjust a size of the YLC cache…” corresponds to claim 8, lines 5-8 of the ‘745 patent.
Claim 16 of the present application corresponds to claims 1 and 13 of the ‘745 patent, where “An electronic system…” corresponds to claim 1, line 1-2 and claim 13, line 1 of the ‘745 patent; “a plurality of x-level cell (XLC) memory blocks…” corresponds to claim 1, line 2 and claim 13, lines 2-3 of the ‘745 patent; a y-level cell (YLC) cache…” corresponds to claim 1, line 12 and claim 13, line 4 of the ‘745 patent; “a memory controller operable to execute instructions…” corresponds to claim 13, lines 5-7 of the ‘745 patent; “allocating the YLC cache…” corresponds to claim 1, lines 12-13 and claim 13, lines 13-18 of the ‘745 patent; and “in response to one or more memory access requests…” corresponds to claim 1, lines 15-16 and claim 13, line 15-18 of the ‘745 patent.
Claim 17 of the present application corresponds to claim 9 of the ‘745 patent, where “monitor a degree of data burstiness…” corresponds to claim 9, lines 2-3 of the ‘745 patent; and “dynamically adjust a size of the YLC cache…” corresponds to claim 9, lines 4-5 of the ‘745 patent.
Claim 18 of the present application corresponds to claim 10 of the ‘745 patent, where “monitor a degree of write pressure…” corresponds to claim 10, lines 2-3 of the ‘745 patent; and “dynamically adjust a size of the YLC cache…” corresponds to claim 10, lines 4-5 of the ‘745 patent.
Claim 19 of the present application corresponds to claims 1, 6 and 10 of the ‘745 patent, where “wherein the electronic device includes a host…” corresponds to claim 10, lines 6-8 of the ‘745 patent; “receiving a notification by the memory device…” corresponds to claim 10, lines 9-11 of the ‘745 patent; and “determining, based on the notification, whether the host device…” corresponds to claim 1, lines 10-17 of the ‘745 patent.
Claim 20 of the present application corresponds to claim 12 of the ‘745 patent, where “initiate the YLC cache with a default…” corresponds to claim 12, lines 2-3 of the ‘745 patent; and “write data into the plurality of XLC memory…” corresponds to claim 12, lines 4-5 of the ‘745 patent.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 8-13, 15-17 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Li et al. (US2021/0191858).
With respect claim 1, Li et al. teaches identifying a plurality of X-level cell (XLC) memory blocks (se paragraph 67; memory system 100 can track an amount of data (i.e., the session data measure 372) stored into a first subset of the memory cells 122 (i.e., XLC units) operating as cache memory cells… memory system 100 can also designate the second subset of the cache memory cells to operate in the XLC mode), where X is greater than one (see paragraph 11; memory device can include extra-level cell (XLCs) for holding or representing multiple bits per cell (i.e., XLC memory cells storing data are identified));
allocating a y-level cell (YLC) cache to act as a memory-based cache, wherein y is an integer (see paragraph 53; memory system 100 can designate or group a portion or a subset of the memory cells 122 within the entirety of the memory cells 122 allotted for the SLC caching operation 130. The memory system 100 can initially designate or group a number of the memory cells 122, the memory pages 124, the memory blocks 126, or a combination thereof corresponding to an initial or predetermined value of the SLC increment size); and
in response to one or more memory access requests, accessing the plurality of XLC memory blocks via the YLC cache (see paragraph 55; memory system 100 can use the SLC segment 140 for caching data, where the data 110 is initially written to the SLC segment 140 and subsequently moved to a another location, such as other XLC locations outside of cache locations (XLC is written/accessed through YLC/SLC)).
With respect claim 2, Li et al. teaches wherein y is less than x (see paragraph 11; memory device can include single-level cells (SLCs) for holding or representing one bit per cell and/or extra-level cell (XLCs) for holding or representing multiple bits per cell ).
With respect claim 3, Li et al. teaches wherein the one or more memory access requests include one or more write requests, and accessing the plurality of XLC memory blocks includes storing data into the plurality of XLC memory blocks via the YLC cache (see paragraph 55; memory system 100 can use the SLC segment 140 for caching data, where the data 110 is initially written to the SLC segment 140 and subsequently moved to a another location, such as other XLC locations outside of cache locations (XLC is written/accessed through YLC/SLC)).
With respect claim 8, Li et al. teaches wherein accessing the plurality of XLC memory blocks via the YLC cache further comprises storing data into the plurality of XLC memory blocks (see paragraph 55; memory system 100 can use the SLC segment 140 for caching data, where the data 110 is initially written to the SLC segment 140 and subsequently moved to a another location, such as other XLC locations outside of cache locations (XLC is written/accessed through YLC/SLC)).
With respect claim 9, Li et al. teaches obtaining the data to be stored (see paragraph 55; memory system 100 can perform operations on the data 110. The memory system 100 can write or access the data 110 to or from the memory cells 122. The memory system 100 can use the SLC segment 140 for caching data, where the data 110 is initially written to the SLC segment 140 (i.e., data to be written is obtained));
writing the data in a plurality of memory blocks in the YLC cache (see paragraph 55 memory system 100 can use the SLC segment 140 for caching data, where the data 110 is initially written to the SLC segment 140), wherein each of the plurality of memory blocks is located in a respective distinct die (see paragraph 19; memory array 104 includes a plurality of memory regions, or memory units 120. The memory units 120 can be individual memory dies), and
moving the data from the YLC cache to a target memory block in the plurality of XLC memory blocks (see paragraph 55; data 110 is initially written to the SLC segment 140 and subsequently moved to a another location, such as other XLC locations).
With respect claim 10, Li et al. teaches wherein the data is moved from the YLC cache to the target memory block in the plurality of XLC memory blocks, when the YLC cache is full or has enough data to complete a XLC program cycle (see paragraph 55; memory system 100 can use the SLC segment 140 for caching data, where the data 110 is initially written to the SLC segment 140 and subsequently moved to a another location, such as other XLC locations outside of cache locations (XLC is written/accessed through YLC/SLC)).
With respect claim 11, Li et al. teaches a host device (see Fig. 1 and paragraph 18; host device 108); and
a memory device coupled to the host device (see Fig. 1 and paragraph 18; memory device 102, coupled to host device 108) and configured to perform operations comprising:
identifying a plurality of X-level cell (XLC) memory blocks (see paragraph 67; memory system 100 can track an amount of data (i.e., the session data measure 372) stored into a first subset of the memory cells 122 (i.e., XLC units) operating as cache memory cells… memory system 100 can also designate the second subset of the cache memory cells to operate in the XLC mode (i.e., XLC memory cells storing data are identified)), where X is greater than one (see paragraph 11; memory device can include extra-level cell (XLCs) for holding or representing multiple bits per cell);
allocating a y-level cell (YLC) cache to act as a memory-based cache, wherein y is an integer (see paragraph 53; memory system 100 can designate or group a portion or a subset of the memory cells 122 within the entirety of the memory cells 122 allotted for the SLC caching operation 130. The memory system 100 can initially designate or group a number of the memory cells 122, the memory pages 124, the memory blocks 126, or a combination thereof corresponding to an initial or predetermined value of the SLC increment size); and
in response to one or more memory access requests, accessing the plurality of XLC memory blocks via the YLC cache (see paragraph 55; memory system 100 can use the SLC segment 140 for caching data, where the data 110 is initially written to the SLC segment 140 and subsequently moved to a another location, such as other XLC locations outside of cache locations (XLC is written/accessed through YLC/SLC)).
With respect claim 12, Li et al. teaches wherein the electronic system is further configured to: monitor memory access environment information for access data in the electronic system (see paragraph 38; workload type 146 characterizes a sequence of operations that the memory device 102 has been tasked to perform at a given time. The memory system 100 can determine the workload type 146 based on the operations being executed with regards to the data 110 (i.e., memory access is monitored)); and
dynamically adjust a size of the YLC cache based on the memory access environment information (see paragraph 43; memory system 100 can also calculate a burst size 154 which can be used to dynamically calculate the SLC increment size 142. The burst size 154 is a representation of an amount of data processed for each grouping or segment of operations or instructions between the idle time events (i.e., YLC/SLC size calculated based on monitored workload)).
With respect claim 13, Li et al. teaches wherein the memory access environment information comprises at least one of: information related to an identify controller (IDC) command received during device discovery ; a write workload detected from the host device; a write pressure bandwidth requirement; or a shaping size notification (see paragraphs 38 and 43; workload type 146 characterizes a sequence of operations that the memory device 102 has been tasked to perform at a given time. The memory system 100 can determine the workload type 146 based on the operations being executed with regards to the data (i.e., workload detected)).
With respect claim 15, Li et al. teaches wherein the electronic system is further configured to: monitor a write workload (see paragraphs 38 and 43; workload type 146 characterizes a sequence of operations that the memory device 102 has been tasked to perform at a given time. The memory system 100 can determine the workload type 146 based on the operations being executed with regards to the data (i.e., workload detected)); and
dynamically adjust a size of the YLC cache based on the write workload (see paragraph 43; memory system 100 can also calculate a burst size 154 which can be used to dynamically calculate the SLC increment size 142. The burst size 154 is a representation of an amount of data processed for each grouping or segment of operations or instructions between the idle time events (i.e., YLC/SLC size calculated based on monitored workload)).
With respect claim 16, Li et al. teaches a plurality of x-level cell (XLC) memory blocks (see paragraph 67; memory system 100 can track an amount of data (i.e., the session data measure 372) stored into a first subset of the memory cells 122 (i.e., XLC units) operating as cache memory cells… memory system 100 can also designate the second subset of the cache memory cells to operate in the XLC mode), where X is greater than one (see paragraph 11; memory device can include extra-level cell (XLCs) for holding or representing multiple bits per cell);
a y-level cell (YLC) cache (see paragraph 53; (see paragraph 53; memory system 100 can designate or group a portion or a subset of the memory cells 122 within the entirety of the memory cells 122 allotted for the SLC caching operation 130); and
a memory controller operable to execute instructions which when executed cause the memory controller (see Fig. 1 and paragraph 28; controller 106 can include a processor 131 configured to execute instructions stored in memory) to perform operations comprising:
allocating a y-level cell (YLC) cache to act as a memory-based cache, wherein y is an integer (see paragraph 53; memory system 100 can designate or group a portion or a subset of the memory cells 122 within the entirety of the memory cells 122 allotted for the SLC caching operation 130. The memory system 100 can initially designate or group a number of the memory cells 122, the memory pages 124, the memory blocks 126, or a combination thereof corresponding to an initial or predetermined value of the SLC increment size); and
in response to one or more memory access requests, accessing the plurality of XLC memory blocks via the YLC cache (see paragraph 55; memory system 100 can use the SLC segment 140 for caching data, where the data 110 is initially written to the SLC segment 140 and subsequently moved to a another location, such as other XLC locations outside of cache locations (XLC is written/accessed through YLC/SLC)).
With respect claim 17, Li et al. teaches wherein the electronic system is further configured to: monitor a degree of data burstiness (see paragraphs 38-39 and 41-42; memory system 100 can determine the workload type 146 based on the operations being executed with regards to the data 110. For example, the memory system 100 can determine the workload type 146 as a burst workload); and
dynamically adjust a size of the YLC cache based on the degree of data burstiness (see paragraph 43; memory system 100 can also calculate a burst size 154 which can be used to dynamically calculate the SLC increment size 142 (i.e., YLC/SLC size determined based on vurst workload determined)).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (US2021/0191858) as applied to claim 11-12 above, and further in view of Bielby et al. (US11,409,654).
With respect claim 14, Li et al. does not teach wherein the memory access environment information is monitored based on a machine learning model or an artificial intelligence (AI) model.
However, Bielby et al. teaches artificial neural network (ANN) can used to predict the optimized caching algorithm among a plurality of candidate caching algorithms and the optimized parameters for caching operations performed suing the optimized caching algorithm. Examples of the parameters used in caching operations performed using a caching strategy/scheme include cache size (see column 25, lines 40-47 and column 26, lines 6-11).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the system taught by Li et al. to include the above mentioned to optimize the caching performance level (see Bielby, column 26, lines 14-19).
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (US2021/0191858) as applied to claim 16 above, and further in view of Duan et al. (US2022/0283939).
With respect claim 18, Li et al. does not teach wherein the electronic system is further configured to: monitor a degree of write pressure; and dynamically adjust a size of the YLC cache based on the degree of write pressure,
However, Duan et al. teaches wherein size of the SLC cache can be adjusted during usage of the memory device based upon a write amplification (WA) metric of the memory device (see Abstract)… a write amplification metric can be tracked by the memory device (e.g., a memory controller). In some examples, the memory device can track one or more write amplification metric components—such as a total size of all data requested to be written by the host and a total size of all data written to flash. In some examples, the write amplification can then be calculated using these components. For example, a write amplification can be the total size of all data that already has been written to flash divided by the total size of all data requested to be written by the host (see paragraph 83).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the system taught by Li et al. to include the above mentioned to balance performance and device lifetime (see Duan, paragraph 67).
Allowable Subject Matter
Claims 4-7 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: No prior art or combination of prior art teaches or suggest identifying a write shaping status of the electronic device; and based on the write shaping status, determining that the electronic device performs write operations without the memory-based cache, wherein the YLC cache is allocated in accordance with a determination that the write operations are performed without the memory- based cache as recited in claim 4; determining, based on the notification, whether the host device supports write operations via the memory-based cache, wherein the YLC cache is allocated when the host device does not support write operations via the memory-based cache as recited in claim 5; detecting an input/output (I/O) pattern; and determining whether the I/O pattern indicates sequential data regions or random data regions with respect to logical block addressing (LBA), wherein the YLC cache is allocated when the I/O pattern indicates random data regions with respect to LBA as recited in claim 7; and wherein the YLC cache is applied and data is written to the plurality of XLC memory blocks via the YLC cache, when the degree of write pressure is lower than the predetermined threshold as recited in claim 19.
Li et al. (US2021/0191858) teaches memory system 100 can designate or group a portion or a subset of the memory cells 122 within the entirety of the memory cells 122 allotted for the SLC caching operation 130. The memory system 100 can initially designate or group a number of the memory cells 122, the memory pages 124, the memory blocks 126, or a combination thereof corresponding to an initial or predetermined value of the SLC increment size (see paragraph 53); and memory system 100 can use the SLC segment 140 for caching data, where the data 110 is initially written to the SLC segment 140 and subsequently moved to a another location, such as other XLC locations outside of cache locations (XLC is written/accessed through YLC/SLC) (see paragraph 55).
However, Li et al. does not teach identifying a write shaping status of the electronic device; and based on the write shaping status, determining that the electronic device performs write operations without the memory-based cache, wherein the YLC cache is allocated in accordance with a determination that the write operations are performed without the memory- based cache as recited in claim 4; determining, based on the notification, whether the host device supports write operations via the memory-based cache, wherein the YLC cache is allocated when the host device does not support write operations via the memory-based cache as recited in claim 5.
Raju et al. (US11,733,914) teaches wherein when the processor 124 determines that the write request received at block 210 is not a sequential write (“No” at decision block 220), the method 200 includes the processor 124 controlling the data to be written to an SLC random block of the non-volatile memory 104 (at block 240) (see column 5, lines 55-60)… and controlling the data to be written in a SLC sequential block of the non-volatile memory 104 (at block 260) (see column 6, lines 10-13).
However, Raju et al. does not teach detecting an input/output (I/O) pattern; and determining whether the I/O pattern indicates sequential data regions or random data regions with respect to logical block addressing (LBA), wherein the YLC cache is allocated when the I/O pattern indicates random data regions with respect to LBA as recited in claim 7.
Duan et al. (US2022/0283939) teaches wherein size of the SLC cache can be adjusted during usage of the memory device based upon a write amplification (WA) metric of the memory device (see Abstract)… a write amplification metric can be tracked by the memory device (e.g., a memory controller). In some examples, the memory device can track one or more write amplification metric components—such as a total size of all data requested to be written by the host and a total size of all data written to flash. In some examples, the write amplification can then be calculated using these components. For example, a write amplification can be the total size of all data that already has been written to flash divided by the total size of all data requested to be written by the host (see paragraph 83).
However, Duan et al. does not teach wherein the YLC cache is applied and data is written to the plurality of XLC memory blocks via the YLC cache, when the degree of write pressure is lower than the predetermined threshold as recited in claim 19.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Bi et al. (US2022/0404976) teaches enable a NAND memory system to write data using the MLC, TLC, or QLC mode directly when the queue depth (QD) is below the threshold and to write data using the SLC mode (e.g., and later rewriting using the MLC, TLC, or QLC mode) when the QD is above the threshold (see paragraph 13).
Chang et al (US2008/0244164) teaches storing information thereof particularly to device to store electronic information through a single-level-cell (SLC) processing structure and a multi-level cell (MLC) processing structure (see paragraph 1).
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/ARACELIS RUIZ/ Primary Examiner, Art Unit 2139
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