DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kanai et al. (US 2013/0268781) and Toru (EP331407 A2).
Regarding claim 1, Kanai et al. discloses a control device [¶0068: control device] comprising: a central processing unit [FIG. 12: processor], a nonvolatile memory [FIG. 12: secondary storage], and a volatile memory [FIG. 12: main memory], wherein the control device is configured to: first enter a first state after activation [¶0035: control a state transition of the information processing device between an activated state (first state)], and enter a second state after the first state [¶0035: control a state transition of the information processing device between an activated state (first state) and a suspended state (second state)].
Kanai et al. discloses the claimed invention as discussed above but does not explicitly disclose set an address range in the volatile memory that the central processing unit is inhibited from accessing in each state, and, when first entering the first state after activation, execute a program stored in the nonvolatile memory while the central processing unit is inhibited from accessing all areas in the volatile memory.
Toru set an address range in the volatile memory that the central processing unit is inhibited from accessing in each state [Title, Abstract, Claims, FIG 1: an inhibition address checker determines whether an accessing address supplied by the processor is for an address range of values which should be inhibited from being accessed], and, when first entering the first state after activation, execute a program stored in the nonvolatile memory while the central processing unit is inhibited from accessing all areas in the volatile memory [Title, Abstract, Claims, FIG 1: an inhibition address checker determines whether an accessing address supplied by the processor is for an address range of values which should be inhibited from being accessed, the access inhibition controller is arranged to respond to an access-inhibiting signal].
It would have been obvious to one of ordinary skill in at the time of invention to have an address range in the volatile memory that the central processing unit is inhibited from accessing in each state in order to provide a highly reliable memory which can prevent danger of a failure to operate the memory due to destruction of system control information and avoid the possibility that security information stored in the memory may be read out (Page 2).
Regarding claim 2, Toru discloses the control device according to claim 1, wherein the control device is configured to change setting to a state in which access to the volatile memory is permitted after the program confirms that there is no possibility that unauthorized software will run in the control device [Col. 2: 34-55].
Regarding claim 3, Kanai discloses the control device according to claim 1, wherein the volatile memory includes a storage area including a first area and a second area [FIG. 14: main memory, secondary storage], the control device further comprises: a bus coupled to the central processing unit [FIG. 14: bus coupled to processor], and a monitoring circuit that monitors communication between the central processing unit and the bus [FIG. 18: processor], is configured to permit the central processing unit to access the first area of the volatile memory and not to permit the central processing unit to access the second area of the volatile memory while the control device is in the first state [FIG. 18, ¶0057, 0063: first semiconductor device, second semiconductor device].
Toru further discloses the processing unit is configured not to permit the central processing unit to access the first area of the volatile memory but to permit the central processing unit to access the second area of the volatile memory while the control device is in the second state [Abstract; FIG. 1, Claim 1], and is configured to be able to change address ranges of the first area and the second area according to the program [Abstract; FIG. 1, Claim 1], and the control device is configured to execute the program stored in the nonvolatile memory in a state in which an entire area of the volatile memory is the second area when the control device first enters the first state after activation [Abstract; FIG. 1, Claim 1; 6], and is configured to be able to change setting of the volatile memory to the first area after the program confirms that there is no possibility that unauthorized software will run [Claims 11, 12].
Regarding claim 4, the rationale in the rejection of claim 1 is herein incorporated.
Regarding claim 5, Kanai discloses the control device according to claim 4, wherein the first mode is a test mode [FIG. 7, 8, 10].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Turean et al. (US 2013/0290637) discloses separate two zones in which CPU2 would be prevented from accessing the specified address range.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARDOCHEE CHERY whose telephone number is (571)272-4246. The examiner can normally be reached 900-500.
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/MARDOCHEE CHERY/Primary Examiner, Art Unit 2133
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