DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 13, 17 and 19 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 9, 13, 16 and 20 of U.S. Patent No. 12,431,884. Although the claims at issue are not identical, they are not patentably distinct from each other because
With respect to claim 1, claim 1 essentially recites the limitations of claim 9 of U.S. Patent No. 12,431,884, expect claim 1 of the instant invention is broader than claim 9. For instance, claim 1 of the instant applications does not require “a pair of capacitors”, “a second output drive circuit including at least a second P channel output transistor having a gate terminal and a drain terminal, the drain terminal of the second P channel output transistor being coupled to the serial data link output driver output terminal, the gate terminal of the second P channel output transistor being coupled to a second terminal of a corresponding capacitor of the at least one pair of capacitors of the capacitor pump circuit” and the “two oppositely phased clocks” as recited in claim 9 (see also claim 2 from which claim 9 depends upon) of U.S. Patent No. 12,431,884. It would have been obvious to remove the extra circuit elements from claim 9 of U.S. Patent No. 12,431,884, since it has been held that omission of an element and its function in a combination where the remaining elements perform the same functions as before involves only routine skill in the art. In re Karlson, 136 USPQ 184. One would have been motivated to do so for the purpose of simplifying circuit construction.
With respect to claim 13, claim 13 essentially recites the limitations of claim 13 of U.S. Patent No. 12,431,884, expect claim 13 of the instant invention is broader than claim 9. For instance, claim 1 of the instant applications does not require “a second P channel output transistor”, “a pair of capacitors”, “driving, by the input logic circuit, the pair of first P and N channel output transistors alternatingly with the second P channel output transistor in correspondence with two oppositely phased clock signals having overlapping high logic levels for a predetermined time period” recited in claim 13 (see also claim 12 from which claim 13 depends upon) of U.S. Patent No. 12,431,884. It would have been obvious to remove the extra circuit elements from claim 13 of U.S. Patent No. 12,431,884, since it has been held that omission of an element and its function in a combination where the remaining elements perform the same functions as before involves only routine skill in the art. In re Karlson, 136 USPQ 184. One would have been motivated to do so for the purpose of simplifying circuit construction.
With respect to claim 17, claim 17 essentially recites the limitations of claim 16 of U.S. Patent No. 12,431,884, expect claim 17 of the instant invention is broader than claim 16. For instance, claim 17 of the instant applications does not require “each of the P and N channel output transistors of the second output drive circuit having drain terminals commonly coupled to the output terminal of the serial data link output driver”, “a pair of capacitors”, and the “two oppositely phased clocks” as recited in claim 16 (see also claim 15 from which claim 17 depends upon) of U.S. Patent No. 12,431,884. It would have been obvious to remove the extra circuit elements from claim 16 of U.S. Patent No. 12,431,884, since it has been held that omission of an element and its function in a combination where the remaining elements perform the same functions as before involves only routine skill in the art. In re Karlson, 136 USPQ 184. One would have been motivated to do so for the purpose of simplifying circuit construction.
With respect to claim 19, claim 19 essentially recites the limitations of claim 17 of U.S. Patent No. 12,431,884, expect claim 19 of the instant invention is broader than claim 17. For instance, claim 19 of the instant applications does not require “each of the P and N channel output transistors of the second output drive circuit having drain terminals commonly coupled to the output terminal of the serial data link output driver”, “a pair of capacitors”, and the “two oppositely phased clocks” as recited in claim 17 (see also claim 15 from which claim 17 depends upon) of U.S. Patent No. 12,431,884. It would have been obvious to remove the extra circuit elements from claim 17 of U.S. Patent No. 12,431,884, since it has been held that omission of an element and its function in a combination where the remaining elements perform the same functions as before involves only routine skill in the art. In re Karlson, 136 USPQ 184. One would have been motivated to do so for the purpose of simplifying circuit construction.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 3-5, 7-8, 12-13, 15 and 17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tachibana et al (USPN 6,072,354).
With respect to claim 1, Tachibana et al. discloses, in Figs. 3-5, 7 and 9, a serial data link output driver (Fig. 3 details disclosed in Figs. 4-5, 7 and 9. Note the circuit of Fig. 3 is constructed within the integrated circuit of Fig. 9), having serial data input (one of DOT, DOB and DOE) and serial data output terminals (IO) the serial data link output driver comprising:
an input logic circuit (at least one of NAND1 and NAND2) having at least one input terminal coupled to the serial data link output driver input terminal for receiving serial data signal therefrom (DOT/DOB input, “serial data link output driver” and “serial data” are merely intended use of the operations of the circuit of the output driver of Fig. 3. The circuit of Fig. 3 is capable of receiving and driving serial data);
a capacitor pump circuit (one of C1, PMOSB2 and PMOSB3 of Fig. 4 within BST3 of Fig. 3 and C1, NMOSB 2 and NMOSB3 of Fig. 7 within BST2 of Fig. 3) including at least one capacitor (one of each C1 of BST3 and BST2) and having at least one input coupled to an output of the input logic circuit (C1 connected to IN which is connected to the output of NAND1/), the output of the at least one input circuit being coupled to a first terminal of the at least one capacitor for establishing a reference voltage for the at least one capacitor (when the output of NAND1/NAND2 is high the output establishes an upper reference voltage for the capacitor C1);
at least one output drive circuit (PMOS1 with NMOS2) including at least one P channel output transistor (PMOS1) having a gate terminal (at N3), a drain terminal coupled to the serial data link output driver output terminal (drain to IO), and a source terminal coupled to a first voltage source having a output voltage corresponding to at least a voltage of a logic one output of the serial data link output driver (source to VCCO which is the logical one value of IO), the at least one output drive circuit further including at least one N channel output transistor (NMOS2) having a gate terminal (at N4), a drain terminal coupled to the serial data link output driver output terminal in common with the drain terminal of the at least one P channel transistor (drain at IO), and a source terminal coupled to a second voltage source (source connected to VSSO), the gate terminal of at least one of the at least one P channel output transistor or the at least one N channel output transistor being coupled to a second terminal of the at least one capacitor (at out of BST3/B2 via NMOSB1 of Fig. 4 and PMOSB1 of Fig. 7, respectively);
at least one reset circuit (at least one of INVB1, PMOSB1 with NMOSB1 of Fig. 4 and PMOSB1 and NMOSB3 with NMOSB1 of Fig. 7) having an input coupled to the input logic circuit (input of INVBB1 of Fig. 4; IN terminal of Fig. 7) and having an output coupled to the second terminal of the at least one capacitor (output terminals of one of PMOSB1 and NMOSB1 Of Fig. 4 and 7 connected to the second terminal via the source to drain conduction paths), the reset circuit being configured to charge the capacitor to a voltage and polarity sufficient to hold a corresponding one of the at least one P channel output transistor (PMOSB1 operates as claimed) or the at least one N channel output transistor in an off state in correspondence with a logic level of the serial data input (NMOSB1 of Fig. 7 operates as claimed); and
at least one reset voltage source circuit (circuit that generates VCC), the at least one reset circuit being coupled to the at least one reset voltage source circuit (VCC coupled to PMOSB1 and NMOSB1), wherein:
a change in the logic level of the serial data input switches the at least one reset circuit to an off state and changes the reference voltage of the first terminal of the at least one capacitor from one logic level to another and thereby changes a magnitude of a voltage applied to the gate terminal to exceed a gate threshold turn on voltage of the at least one P channel output transistor or the at least one N channel output transistor coupled thereto to turn on the at least one P channel output transistor or the at least one N channel output transistor and output a logic signal to the serial data link output driver output terminal (the circuit operates as claimed see N3 being boosted to negative VSS of the dashed line of Fig. 5 for the PMOS capacitor and the solid line of Fig. 5 showing N4 boosted to plus VCC. The above values exceed the respective thresholds of PMOS1 and NMOS2); and
the at least one reset voltage source circuit outputs a voltage selected to compensate for one of circuit tolerance variations, ambient conditions, and output impedance of the at least one output drive circuit while the at least one P channel output transistor or the at least one N channel output transistor is in an on state (the reset voltage compensates for the output impedance of the line driver. For instance, when the boosting circuits generate the boosted signals on N3 and N4 such that one of PMOS1 and NMOS2 are on the signals are boosted high enough such that PMOS1 and NMOS2 operate with a low impedance state, i.e., are fully turned on/conductive).
With respect to claim 3, the serial data link output driver of claim 1, wherein the at least one output drive circuit includes one P channel output transistor (PMOS1), and the capacitor pump circuit includes a single capacitor (C1 of BST3/Fig. 4 when C1 of BST3 is interpreted as the capacitor pump circuit).
With respect to claim 4, the serial data link output driver of claim 1, wherein the capacitor pump circuit includes at least one pair of capacitors (when the pump capacitors of interpreted as C1 of BST3/Fig. 4 and C1 of BST2/Fig. 7), each having a first terminal coupled to an output of the input logic circuit (output of NAND1 and NAND2) and each having a second terminal (other terminal of each C1); and
the gate terminal of the at least one P channel output transistor is coupled to a second terminal of a first of the at least one pair of capacitors and the at least one N channel output transistor is coupled to a second terminal of a second of the at least one pair of capacitors (at N3 and N1 via NMOSB1 of Fig. 4 and PMOSB1 of Fig. 7, respectively).
With respect to claim 5, the serial data link output driver of claim 4, wherein the at least one reset circuit comprises:
at least one P channel transistor switch having a gate terminal coupled to the input logic circuit (PMOSB1 of Fig. 4 gate connected to IN/NAND1 via INVB1),
a source terminal coupled to a first of the at least one reset voltage source circuits (source connected to VCC), and
a drain terminal coupled to the second terminal of the first capacitor of the capacitor pump circuit (when NMOSB1 is active); and
at least one N channel transistor switch (NMOSB3 of Fig. 7) having a gate terminal coupled to the input logic circuit (to IN/NAND2 via INVB1 and C1),
a source terminal coupled to a second of the at least one reset voltage source circuits (source connected to VCC), and
a drain terminal coupled to the second terminal of the second capacitor of the capacitor pump circuit (drain connected to second terminal of C1 of Fig. 7).
With respect to claim 7, the serial data link output driver of claim 1, where the at least one reset circuit includes at least one P channel transistor switch having a gate terminal coupled to the input logic circuit (PMOSB1 of Fig. 4 gate connected to IN/NAND1 via INVB1), a source terminal coupled to a first of the at least one reset voltage source circuits (source connected to VCC), and a drain terminal coupled to the second terminal of the first capacitor of the capacitor pump circuit (when NMOSB1 is active).
With respect to claim 8, the serial data link output driver of claim 1, wherein the serial data link output driver is formed on an integrated circuit chip (the circuit is on a chip, e.g., see Fig. 9), and the at least one reset voltage source circuit being configured to output a voltage equal to a chip supply voltage (VCC and VCCO may be output as equal voltages levels of 3.3V, see Col. 1 lines 20-26).
With respect to claim 12, the serial data link output driver of claim 1, wherein the voltage selected to compensate for one of circuit tolerance variations, ambient conditions, and output impedance of the at least one output drive circuit while the at least one P channel output transistor or the at least one N channel output transistor is in an on state can be set to underdrive or overdrive the gate terminal of the at least one P channel output transistor or the at least one N channel output transistor (the transistors of PMOS1 and NMOS2 are overdriven due to the boosting operations of the gate voltages provided by BST3 and BST2. The output voltages at N3 and N4 are overdriven to voltages below VSS, i.e., VSS-, and voltages above VCC, i.e., VCC+, see Fig. 5).
Claims 13 and 15 essentially recite the methods of constructing and/or operating the circuits as recited in claims 1 and 5 and are rejected for the same reasons as claims 1 and 5.
With respect to claim 17, a serial data link output driver (Fig. 3 as used in Fig. 9 details disclosed in Figs. 4-5 and 7) having serial data input (one of DOT, DOB and DOE) and serial data output terminals (IO), further having an output drive circuit having at least one pair of P and N channel output transistors (PMOS1 and NMOS2), each of the P and N channel output transistors having drain terminals commonly coupled to an output terminal of the serial data link (drains at IO), the serial data link output driver comprising:
an input logic circuit having at least one input terminal coupled to the input terminal of the serial data link output driver for receiving serial data signal therefrom (at least one of NAND1 and NAND2, serial data is merely an intended use/function limitation which the circuit of Fig. 3 is a capable of providing);
at least one reset circuit (at least one of INVB1, PMOSB1 with NMOSB1 of Fig. 4 and PMOSB1 and NMOSB3 with NMOSB1 of Fig. 7) having an input terminal coupled to an output terminal of the input logic circuit (each reset circuitry are coupled to each IN of Fig. 4 and Fig. 7) and an output terminal coupled to a gate terminal of at least one transistor of the pair of P and N channel output transistors (each reset circuitry is coupled to each OUT of BST3 and BTS2 coupled to N3 and N4), the at least one reset circuit being configured to output a voltage and polarity thereof sufficient to hold the at least one of the P and N channel output transistors of the one pair of P and N channel output transistors in an off state (VCC of BST3 holds off PMOS1 and VSS of BST2 holds off NMOS2) in correspondence with a logic level of the serial data input (logic level of IN/N1/N2 at high), the at least one reset circuit being inhibited from output of a voltage in correspondence with an opposing logic level of the serial data input (at low); and
a capacitor pump circuit (one of C1, PMOSB2 and PMOSB3 of Fig. 4 within BST3 of Fig. 3 and C1, NMOSB 2 and NMOSB3 of Fig. 7 within BST2 of Fig. 3) having an input terminal thereof coupled to another output terminal of the input logic circuit (termina connected to IN) and an output terminal thereof coupled to the gate terminal of the at least one transistor of the at least one pair of P and N channel output transistors (terminal connected to OUT via the transistors of BST3 and BST2), the capacitor pump circuit being configured to capacitively store the voltage outputted by the at least one reset circuit relative to a logic level voltage of the other output terminal of the input logic circuit; wherein:
in correspondence with the inhibited output of the at least one reset circuit, the logic level voltage of the other output terminal of the input logic circuit changes to an opposing logic level to thereby change the reference of the stored voltage and thereby establish a gate voltage of the at least one of the P and N channel output transistors of the one pair of P and N channel output transistors that exceeds a gate threshold turn on voltage thereof (the circuit operates as claimed see N3 being boosted to negative VSS of the dashed line of Fig. 5 for the PMOS capacitor and the solid line of Fig. 5 showing N4 boosted to plus VCC. The above values exceed the respective thresholds of PMOS1 and NMOS2); and
the at least one reset circuit is coupled to a reset voltage source (VCC), which is configured to output a voltage selected to hold the at least one transistor of the at least one pair of P and N channel output transistors in an off state (VCC holds PMOS1 in an off state when applied to the gate of PMOS1) and compensate for at least one of circuit tolerance variations, ambient conditions, and output impedance of the output drive circuit of the serial data link output driver while the at least one P channel output transistor or the at least one N channel output transistor is in an on state (the reset voltage compensates for the output impedance of the line driver. For instance, when the boosting circuits generate the boosted signals on N3 and N4 such that one of PMOS1 and NMOS2 are on the signals are boosted high enough such that PMOS1 and NMOS2 operate with a low impedance state, i.e., are fully turned on/conductive).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tachibana et al. (USPN 6,072,354).
With respect to claim 6, Tachibana et al. discloses that BST3 and BST2 receive the same reset voltage source of VCC. Thus, Tachibana et al. fails to explicitly disclose “wherein the voltage levels of the first and second of the at least one reset voltage source circuits can be controlled independently.” However, it is old and well-known to have adjustable power supply voltages, such as VCC of Tachibana et al., for the purpose of being able to fine tune the voltage level of a power supply voltage to a desired value. Examiner takes official notice of the use of adjustable power supply voltages.
It would have been obvious to supply a distinct adjustable VCC voltage power supply source to each of BST3 and BST2 such that at least one reset voltage source circuits can be controlled independently, since it has been held the provision of adjustability, where needed, involves only routine skill in the art. In re Stevens, 101 USPQ 284 (CCPA 1954). Furthermore, it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980). One would have been motivated to do so for the purpose of being able to fine tune the voltage level supplied to each BST3 and BST2, the voltage level supplied to BST3 and BST2 controls, in part, the turning off and on as well as the on/off resistance of PMOS1 and NMOS2 via the control of the gate voltages of PMOS1 and NMOS2. Thus, one would have been motivated to control the supply voltages of VCC according to the requirements of the transistors receiving the outputs of BST3 and BST2. It is further noted that the claims merely state “can” and only require a possibility of independent control/different values.
Claim 16 is rejected for similar reasons as claim 6.
Claim(s) 9 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tachibana et al. (USPN 6,072,354) in view of Lou et al. (USPN 5,729,165).
With respect to claim 9, Tachibana et al. discloses the serial data link output driver of claim 1, wherein the serial data link output driver is formed on an integrated circuit chip (integrated circuit of Fig. 9).
However, Tachibana et al. fails to explicitly disclose the sizing of the transistors of the output driving transistors (PMOS1 and NMOS2) and the sizing of the gate boosting circuits of (BST3 and BST2). Thus, Tachibana et al. fails to disclose “the area of the reset circuit transistors is substantially smaller than the area of the output circuit transistors on the integrated circuit chip.”
However, it is old and well-known to construct an output driver with transistors that have a larger area (i.e., are wider) than the transistors of the gate voltage boosting circuit connected to the output driver. This is further evidenced in Figs. 1-3(b) of Lou et al. which discloses an output driving transistors (MP1/P1 and MN1) that are substantially wider than the transistors of the gate voltage boosting circuit (Fig. 1 lest MP1/P1 and MN1), see Col. 4 lines 4-17 (the PMOS and NMOS output driving transistors are substantially larger/wider than any respective PMOS and NMOS transistor of the gate boosting circuitry). Wider transistors allow for the supplying of higher current levels by the output driver.
It would have been obvious to one of ordinary skill in the art to construct the output driving transistors of PMOS1 and NMOS2 of Tachibana et al. to have a substantially larger circuit area than the reset transistors of Tachibana et al., similar to the sizing a as evidenced by Lou et al., for the purpose of having large output driving transistors capable of providing high output current levels.
Claim 18 is rejected for similar reasons as claim 9.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tachibana et al. (USPN 6,072,354) in view of Nishio (USPN 8,581,649).
Tachibana et al. fails to disclose the specific impedance of the transistors PMOS1 and NMOS2 and fails to disclose a resistor coupled in series to the drain terminals of at least one of PMOS1 and NMOS2.
Thus, Tachibana et al. fails to disclose “a resistor coupled in series to the drain terminals of the at least one P channel output transistor and the at least one N channel output transistor, wherein controlling the output impedance of the at least one output drive circuit while the at least one P channel output transistor or the at least one N channel output transistor is in an on state allows the output driver impedance to be maintained at substantially the same level over time.”
However, Nishio discloses in Fig. 10 that it is old and well known to connect a resistor (R) to in series to the drains of a PMOS transistor (PU) and an NMOS transistor (PD) output driver (100). Furthermore, Nishio disclose that the impedance of the driver may be set according to the impedance of the output driver transistors and resistors at the drains (see Col. 10 lines 4-18).
It would have been obvious to place resistors, such as R of Nishio, at the drains of PMOS1 and NMOS2 of Tachibana and size the transistor to provide a desired output impedance of the driver as evidenced by Nishio. Furthermore, it would be obvious to set the impedances and resistors to any desired value such that the output impedance is substantially the same over time, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980). One would have been motivated to do so to maintain the output impedance at a desired value at all times such as an output impedance of the driver that is matched to the impedance of the load being driven by the driver. It is old and well-known that matching the impedance of a driver/generator to the impedance of the load being driven by the driver/generator maximizes energy transfer. Examiner takes official notice that the matching of the output impedance of a source/driver/generator to the load of the source/driver/generator provides for a maximum energy transfer. Thus, it would have been obvious to provide for a match between the output impedance of the driver and the load of Tachibana et al. at all times for the purpose of maximizing energy transfer.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tachibana et al. (USPN 6,072,354) in view of Lou et al. (USPN 5,729,165) and in further view of Nishio (USPN 8,581,649).
With respect to claim 11, Tachibana et al., as modified above, fails to disclose the impedance of PMOS1 and NMOS2 the resistance of a resistor associated with the output driver. Thus, Tachibana et al. fails to disclose “wherein the output driver impedance is substantially 50 ohms, and the resistance of an associated resistor of the output driver is less than 20 ohms.”
However, Nishio discloses in Fig. 10 that it is old and well known to connect a resistor (R) to in series to the drains of a PMOS transistor (PU) and an NMOS transistor (PD) output driver (100). Furthermore, Nishio disclose that the impedance of the driver may be set according to the impedance of the output driver transistors and resistors at the drains (see Col. 10 lines 4-18).
It would have been obvious to place resistors, such as R of Nishio, at the drains of PMOS1 and NMOS2 of Tachibana and size the transistor to provide a desired output impedance of the driver as evidenced by Nishio. Furthermore, it would be obvious to set the impedances and resistors to any desired value such as 50 ohms for the output driver and 20 ohms or less for the resistor. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980). One would have been motivated to do so provide a desired total output impedance of the driver circuit and/or match the output impedance to the value of the load. It is old and well-known that matching the impedance of a driver/generator to the impedance of the load being driven by the driver/generator maximizes energy transfer. Examiner takes official notice that the matching of the output impedance of a source/driver/generator to the load of the source/driver/generator provides for a maximum energy transfer. Thus, it would have been obvious to provide any desired resistance and impedance values for the output driver transistors and resistors for a match between the output impedance of the driver and the load of Tachibana et al. at all times for the purpose of maximizing energy transfer.
Allowable Subject Matter
Claims 2 and 13 would be allowable if rewritten to overcome the rejection(s) under Double Patenting set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Claims 19 would be allowable if rewritten or amended to overcome the rejection(s) under Double Patenting set forth in this Office action.
Claim 20 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thomas J. Hiltunen whose telephone number is (571)272-5525. The examiner can normally be reached 9:00AM-5:30PM EST M-F.
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/THOMAS J. HILTUNEN/Primary Examiner, Art Unit 2836
Prosecution Insights