DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Specifically, the current title mentions “erase policy” which is not claimed.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1, 3 – 6, 8, 10 – 13, 15, and 17 – 19 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 – 5, 8 – 12, and 15 – 19 of U.S. Patent No. 12417028. Although the claims at issue are not identical, they are not patentably distinct from each other because each limitation of the instant application is obviously anticipated by a corresponding limitation present in US Patent ‘028.
Instant Application 19/305185
US Patent 12417028
1. A method comprising: determining a workload for a memory device, wherein the memory device includes a plurality of portions of memory;
1. A method comprising: determining an erase policy of a plurality of erase policies for a memory device, wherein the memory device includes a plurality of portions of memory; determining a workload for the memory device;
selecting an erase operation from a plurality of erase operations using the determined workload, wherein the plurality of erase operations comprises an alternating erase operation and a uniform erase operation; and
selecting an erase operation from a plurality of erase operations using the determined erase policy and the determined workload, wherein the plurality of erase operations comprises an alternating erase operation and a uniform erase operation;
executing the selected erase operation on a portion of memory of the plurality of portions of memory.
executing the erase operation on a portion of memory of the plurality of portions of memory.
As can be seen above, each limitation of the instant claim has a corresponding limitation in US Patent ‘028. Furthermore, claim 15 of the instant claim more specifically describes determining the queue depth. Claim 16 (which depends from claim 15) of US Patent ‘028 similarly determines the queue depth.
Claims 3 – 6, 8, 10 – 13, 15, and 17 – 19 of the instant application are similarly obvious in view of claims 2 – 5, 8 – 12, and 15 – 19 of US Patent ‘028.
Claim Objections
Claims 7, 14, and 20 are objected to because of the following informalities: Each of these claims starts by determining a power mode for the memory device. However, the next limitation describes selecting the erase operation further uses a bit density of the portion of memory. It is unclear if this was supposed to depend from a claim previously determining the bit density or if the power mode was supposed to be used to select the erase operation. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 3 – 6, 8, 10 – 13, 15, and 17 – 19 are rejected under 35 U.S.C. 103 as being unpatentable over Moon et al. US Patent Application Publication No. 2015/0205539 (herein after referred to as Moon) in view of Oowada et al. US Patent Application Publication No. 2022/0101926 (herein after referred to as Oowada).
Regarding claims 1 and 8, Moon describes a method comprising: determining a workload for a memory device (…it is possible to indicate a state of the write buffer 115 using an empty ratio (ER). That is, the empty ratio ER means a ratio of an empty memory size to the whole memory size (E+D). Thus, the empty ratio ER is expressed by E/(E+D) (page 5, paragraph [0079])), wherein the memory device includes a plurality of portions of memory (The nonvolatile memory device 120 has a plurality of memory blocks BLK1 to BLKi, each of which includes a plurality of memory cells arranged in rows and columns (page 3, paragraph [0044])); selecting an erase operation from a plurality of erase operations using the determined workload (An erase mode about a selected memory block may be decided using a set feature function or other control signals (page 3, paragraph [0041]). …erase method according to at least one example embodiment of the inventive concepts. A method of determining an erase mode according to an empty ratio ER will be more fully described with reference to Fig. 8 (page 6, paragraph [0082])); and executing the selected erase operation on a portion of memory of the plurality of portions of memory (If the empty ratio ER is less than or equal to the first threshold value TH1, the method proceeds to operation S135… In operation S135, the memory controller 110 selects a fast erase mode F_EM as an erase mode about a selected memory block (page 6, paragraphs [0085] - [0086]). If the empty ratio ER is smaller than the second threshold value TH2, the method proceeds to operations S145… In operation S145, the memory controller 110 selects a first slow erase mode S_EM1 as an erase mode about the selected memory block (page 6, paragraph [0087])). While Moon describes fast erase and slow erase (see above), it does not specifically disclose a non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to, nor wherein the plurality of erase operations comprises an alternating erase operation and a uniform erase operation.
Oowada discloses a non-volatile memory with switchable erase methods. Specifically, FIG. 11 is a block diagram that describes the physics of the erase process for NAND string 900 using the All Erase method. In response to applying WLer_en on all of the word lines, holes are injected into charge trapping layer 893. Some holes are further injected into the word lines and into the dielectric/oxide between word lines. A possible result of having holes injected into the dielectric/oxide between word lines is that the memory cells may experience data retention issues over a long period of time. That is, lateral hole movement may cause changes in threshold voltages of the memory cells, which can potentially lead to errors. It has been found that holes are injected into the dielectric/oxide between word lines because of the difference in voltage between the channel and the neighboring word line. FIG. 12 is a block diagram that describes the physics of the erase process for NAND string 900 using the Separate Erase Groups method. On the left side of FIG. 12, only memory cells connected to even word numbered lines are receiving WLer_en (e.g., n is an even number). On the right side of FIG. 12, only memory cells connected to odd numbered word lines are receiving WLer_en. Note that for purposes of this document, an even word line is an even numbered word line (e.g., WL0, WL2, WL4, etc.) and an odd word line is an odd numbered word line (e.g., (WL1, WL3, etc.) Because neighboring word lines are not receiving an erase enable voltage, hole injection into the space between word lines is suppressed. As a result using the Separate Erase Groups method reduces the above-described data retention issue. It has also been found that using the Separate Erase Groups method results in a tighter and more accurate erase threshold voltage distribution (e.g., see S0 of FIG. 5), which can improve programming accuracy. However, because odd word lines are erased separate from even word lines, more time is needed to erase using the Separate Erase Groups method than erasing using the All Erase method (page 11, paragraphs [0120] – [0121]). Therefore the All Erase method is a faster erase than the Separate Erase Groups method, while the Separate Erase Groups method provides an erase that reduces data retention issues caused by the All Erase method. Additionally, Oowada describes control circuitry that includes a state machine that is programmable by software (page 2, paragraph [0040]).
Therefore, it would have been obvious to a person of ordinary skill in the computer art before the effective filing date of the claimed invention to incorporate the Oowada teachings in the Moon system. Skilled artisan would have been motivated to incorporate the All Erase method and Separate Erase Group method as taught by Oowada in the Moon system for effectively reducing data retention issues while also having a faster erase method as necessary. In addition, both of the references teach features that are directed to analogous art and they are directed to the same field of endeavor, such as non-volatile memory erase management. This close relation between both of the references highly suggests an expectation of success.
It also would have been obvious to a person of ordinary skill in the computer art before the effective filing date of the claimed invention to incorporate the Oowada teachings in the Moon system. Skilled artisan would have been motivated to incorporate the control circuitry comprising a state machine programmable by software as taught by Oowada in the Moon system because hardware programmed with software is one of a limited number of methods for implementing computer system operations. In addition, both of the references teach features that are directed to analogous art and they are directed to the same field of endeavor, such as non-volatile memory erase management. This close relation between both of the references highly suggests an expectation of success.
Regarding claims 3 and 10, Moon in view of Oowada describe the method of claim 1 [the non-transitory computer-readable storage medium of claim 8] (see above), wherein determining the workload comprises determining a current command queue depth (That the empty ratio ER is great means that the amount of data to be written at a nonvolatile memory device 120 is small. This also means that a little of memory blocks are erased to write data. Thus, probability that a decrease in performance does not occur although a memory block is erased using a slow erase mode may be high… (Moon, page 5, paragraph [0080])).
Regarding claims 4 and 11, Moon in view of Oowada describe the method of claim 1 [the non-transitory computer-readable storage medium of claim 8] (see above), the method further comprising: selecting the uniform erase operation in response to determining that the workload satisfies a workload threshold (If the empty ratio ER is less than or equal to the first threshold value TH1, the method proceeds to operation S135… In operation S135, the memory controller 110 selects a fast erase mode F_EM as an erase mode about a selected memory block (Moon, page 6, paragraphs [0085] – [0086]). All Erase method (Oowada, page 11, paragraph [0120])).
Regarding claims 5 and 12, Moon in view of Oowada describe the method of claim 1 [the non-transitory computer-readable storage medium of claim 8] (see above), the method further comprising: selecting the alternating erase operation in response to determining that the workload does not satisfy a workload threshold (If the empty ratio is smaller than the second threshold value TH2, the method proceeds to operation S145… In operation S145, the memory controller 110 selects a first slow erase mode S_EM1 as an erase mode about the selected memory block (Moon, page 6, paragraph [0087]). Separate Erase Groups method (Oowada, page 11, paragraph [0121])).
Regarding claims 6 and 13, Moon in view of Oowada describe the method of claim 5 [the non-transitory computer-readable storage medium of claim 12] (see above), wherein the portion of memory comprises even numbered subportions and odd numbered subportions (…the memory cells are divided into two groups: (1) memory cells connected to even word lines and memory cells connected to odd word lines (Oowada, page 11, paragraph [0119])), wherein the alternating erase operation comprises at least two erase pulses comprising a first erase pulse and a second erase pulse (VERA pulses are applied for Separate Erase Groups… (Oowada, page 12, paragraph [0124])), and wherein executing the erase operation comprises: executing the first erase pulse with a first erase voltage on the even numbered subportions and a second erase voltage on the odd numbered subportions (…odd word lines receive erase enable voltage WLer_en while even word lines receive erase inhibit voltage WLer_inh… (Oowada, page 11, paragraph [0119])); and executing the second erase pulse with the second erase voltage on the even numbered subportions and the first erase voltage on the odd numbered subportions (…first memory cells connected to even word lines are erased, while memory cells connected to odd word lines are inhibited from erase… even word lines receive erase enable voltage WLer_en while odd word lines receive erase inhibit voltage WLer_inh (Oowada, page 11, paragraph [0119])), wherein the first erase voltage is a higher voltage than the second erase voltage (WLer_en<<WLer_inh (Oowada, page 11, paragraph [0119])).
Regarding claim 15, Moon describes a system comprising: a plurality of memory devices (NVMs 1230 of Fig. 17); and a processing device, operatively coupled with the plurality of memory devices (SSD Controller 1210 of Fig. 17), to: determine a command queue depth for a memory device of the plurality of memory devices (…it is possible to indicate a state of the write buffer 115 using an empty ratio (ER). That is, the empty ratio ER means a ratio of an empty memory size to the whole memory size (E+D). Thus, the empty ratio ER is expressed by E/(E+D) (page 5, paragraph [0079]). That the empty ratio ER is great means that the amount of data to be written at a nonvolatile memory device 120 is small. This also means that a little of memory blocks are erased to write data. Thus, probability that a decrease in performance does not occur although a memory block is erased using a slow erase mode may be high… (page 5, paragraph [0080])), wherein the memory device includes a plurality of portions of memory (The nonvolatile memory device 120 has a plurality of memory blocks BLK1 to BLKi, each of which includes a plurality of memory cells arranged in rows and columns (page 3, paragraph [0044])); select an erase operation from a plurality of erase operations using the determined command queue depth (An erase mode about a selected memory block may be decided using a set feature function or other control signals (page 3, paragraph [0041]). …erase method according to at least one example embodiment of the inventive concepts. A method of determining an erase mode according to an empty ratio ER will be more fully described with reference to Fig. 8 (page 6, paragraph [0082])); and execute the selected erase operation on a portion of memory of the plurality of portions of memory (If the empty ratio ER is less than or equal to the first threshold value TH1, the method proceeds to operation S135… In operation S135, the memory controller 110 selects a fast erase mode F_EM as an erase mode about a selected memory block (page 6, paragraphs [0085] - [0086]). If the empty ratio ER is smaller than the second threshold value TH2, the method proceeds to operations S145… In operation S145, the memory controller 110 selects a first slow erase mode S_EM1 as an erase mode about the selected memory block (page 6, paragraph [0087])). While Moon describes fast erase and slow erase (see above), it does not specifically disclose wherein the plurality of erase operations comprises an alternating erase operation and a uniform erase operation.
Oowada discloses a non-volatile memory with switchable erase methods. Specifically, FIG. 11 is a block diagram that describes the physics of the erase process for NAND string 900 using the All Erase method. In response to applying WLer_en on all of the word lines, holes are injected into charge trapping layer 893. Some holes are further injected into the word lines and into the dielectric/oxide between word lines. A possible result of having holes injected into the dielectric/oxide between word lines is that the memory cells may experience data retention issues over a long period of time. That is, lateral hole movement may cause changes in threshold voltages of the memory cells, which can potentially lead to errors. It has been found that holes are injected into the dielectric/oxide between word lines because of the difference in voltage between the channel and the neighboring word line. FIG. 12 is a block diagram that describes the physics of the erase process for NAND string 900 using the Separate Erase Groups method. On the left side of FIG. 12, only memory cells connected to even word numbered lines are receiving WLer_en (e.g., n is an even number). On the right side of FIG. 12, only memory cells connected to odd numbered word lines are receiving WLer_en. Note that for purposes of this document, an even word line is an even numbered word line (e.g., WL0, WL2, WL4, etc.) and an odd word line is an odd numbered word line (e.g., (WL1, WL3, etc.) Because neighboring word lines are not receiving an erase enable voltage, hole injection into the space between word lines is suppressed. As a result using the Separate Erase Groups method reduces the above-described data retention issue. It has also been found that using the Separate Erase Groups method results in a tighter and more accurate erase threshold voltage distribution (e.g., see S0 of FIG. 5), which can improve programming accuracy. However, because odd word lines are erased separate from even word lines, more time is needed to erase using the Separate Erase Groups method than erasing using the All Erase method (page 11, paragraphs [0120] – [0121]). Therefore the All Erase method is a faster erase than the Separate Erase Groups method, while the Separate Erase Groups method provides an erase that reduces data retention issues caused by the All Erase method.
Therefore, it would have been obvious to a person of ordinary skill in the computer art before the effective filing date of the claimed invention to incorporate the Oowada teachings in the Moon system. Skilled artisan would have been motivated to incorporate the All Erase method and Separate Erase Group method as taught by Oowada in the Moon system for effectively reducing data retention issues while also having a faster erase method as necessary. In addition, both of the references teach features that are directed to analogous art and they are directed to the same field of endeavor, such as non-volatile memory erase management. This close relation between both of the references highly suggests an expectation of success.
Regarding claim 17, Moon in view of Oowada describe the system of claim 15 (see above), wherein the processing device is further to: select the uniform erase operation in response to determining that the command queue depth satisfies a workload threshold (If the empty ratio ER is less than or equal to the first threshold value TH1, the method proceeds to operation S135… In operation S135, the memory controller 110 selects a fast erase mode F_EM as an erase mode about a selected memory block (Moon, page 6, paragraphs [0085] – [0086]). All Erase method (Oowada, page 11, paragraph [0120])).
Regarding claim 18, Moon in view of Oowada describe the system of claim 15 (see above), wherein the processing device is further to: select the alternating erase operation in response to determining that the command queue depth does not satisfy a workload threshold (If the empty ratio is smaller than the second threshold value TH2, the method proceeds to operation S145… In operation S145, the memory controller 110 selects a first slow erase mode S_EM1 as an erase mode about the selected memory block (Moon, page 6, paragraph [0087]). Separate Erase Groups method (Oowada, page 11, paragraph [0121])).
Regarding claim 19, Moon in view of Oowada describe the system of claim 18 (see above), wherein the portion of memory comprises even numbered subportions and odd numbered subportions (…the memory cells are divided into two groups: (1) memory cells connected to even word lines and memory cells connected to odd word lines (Oowada, page 11, paragraph [0119])), wherein the alternating erase operation comprises at least two erase pulses comprising a first erase pulse and a second erase pulse (VERA pulses are applied for Separate Erase Groups… (Oowada, page 12, paragraph [0124])), and wherein executing the erase operation comprises: executing the first erase pulse with a first erase voltage on the even numbered subportions and a second erase voltage on the odd numbered subportions (…odd word lines receive erase enable voltage WLer_en while even word lines receive erase inhibit voltage WLer_inh… (Oowada, page 11, paragraph [0119])); and executing the second erase pulse with the second erase voltage on the even numbered subportions and the first erase voltage on the odd numbered subportions (…first memory cells connected to even word lines are erased, while memory cells connected to odd word lines are inhibited from erase… even word lines receive erase enable voltage WLer_en while odd word lines receive erase inhibit voltage WLer_inh (Oowada, page 11, paragraph [0119])), wherein the first erase voltage is a higher voltage than the second erase voltage (WLer_en<<WLer_inh (Oowada, page 11, paragraph [0119])).
Allowable Subject Matter
Claims 2, 7, 9, 14, 16 and 20 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The identified claims all describe that selecting the erase operation further uses the bit density of the portion of memory. While Moon suggests checking for power saving mode before determining an erase mode (Moon, page 8, paragraph [0117]), claims 7, 14, and 20 each specifically disclose that bit density is used as part of erase mode determination. The prior art cited above does not teach or suggest this combination of limitations. Lakshmi et al. US Patent Application Publication No. 2024/0143170 describes a specific set of commands include an SLC erase command and a separate MLC erase command. If a block is to be used in SLC mode, then the controller 115 causes an SLC erase to be performed before storing data to the block. Similarly, if a different block needs is to be used in MLC mode, then controller 115 causes this different block to be erased in MLC mode before storing data to the different block (page 6, paragraph [0056]). However, Lakshmi does not explicitly teach or suggest all of the limitations presented in the identified claims. Yeung et al. US Patent Application Publication No. 2024/0069735 describes that conventional approaches blindly pre-erase memory blocks. In such conventional approaches, memory blocks are erased without regard to future programming operations. Blindly erasing memory blocks can introduce further complications. For example, memory cells that are erased in single-level cell (SLC) mode cannot be programmed with triple-level cell (TLC) data. Conversely, memory cells that are erased in TLC mode cannot be programmed with SLC data. A conventional approach may blindly erase all available memory blocks (e.g., substantially all available memory blocks) in SLC mode. Thus, there may be no memory blocks left to service a TLC write operation. One or more already-erased memory blocks are then re-erased in TLC mode to service the TLC write operation. The re-erase introduces further latency to the programming operation and multiple re-erase operations may damage the memory cells over time (page 1, paragraph [0019]). However, Lakshmi does not explicitly teach or suggest all of the limitations presented in the identified claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RALPH A VERDERAMO III whose telephone number is (571)270-1174. The examiner can normally be reached Monday through Friday 8:30 AM - 5:00 PM.
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/RALPH A VERDERAMO III/Examiner, Art Unit 2139
/REGINALD G BRAGDON/Supervisory Patent Examiner, Art Unit 2139
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September 26, 2026
