DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,436,879. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the issued patent make obvious the claims of the pending application in that the claims are directed to substantially the same subject matter as the parent case though not necessarily presented in the same sequential order or the same claim numbering as shown in the table below (for purposes of illustration rather than limitation).
Instant Application: 19/305,202
Patent: 12,436,879
Claim 1. A memory system, comprising: a memory device, and a memory controller coupled to the memory device and comprising an interface, wherein the memory controller is configured to: send, through the interface, a first mapping relationship comprising P pieces of mapping information of a first logical block and a second logical block; and send, through the interface, a second mapping relationship comprising Q pieces of mapping information of the first logical block and the second logical block; wherein the first mapping relationship and the second mapping relationship are sent sequentially; wherein the first mapping relationship are comprised in a first logical block management table, the second mapping relationship are comprised in a second logical block management table, each of the first logical block management table and the second logical block management table comprises a first sequence corresponding to identities of M first logical blocks, the identities of the M first logical blocks are constructed as a queue, M is an integer greater than or equal to 2, and both P and Q are integers greater than or equal to 1 and less than or equal to M; and wherein P first logical blocks corresponding to the P pieces of mapping information and Q first logical blocks corresponding to the Q pieces of mapping information are arranged in sequence in the queue.
Claim 1. A method of operating a memory system, comprising: providing a logical block management table, wherein the logical block management table comprises a first sequence corresponding to identities of M first logical blocks, the identities of the M first logical blocks are constructed as a ring queue, and allocation states of the M first logical blocks are managed through the logical block management table, wherein M is an integer greater than or equal to 2; and allocating, according to an order of the identities of the M first logical blocks in the ring queue, one first logical block whose allocation state is a first state representing an unallocated state to one second logical block among N second logical blocks, wherein N is an integer greater than M, and updating the allocation state of the one first logical block in the logical block management table from the first state to a second state representing an allocated state.
“A later patent claim is not patentably distinct from an earlier patent claim if the later claim is obvious over, or anticipated by, the earlier claim. In re Longi, 759 F.2d at 896, 225 USPQ at 651 (affirming a holding of obviousness-type double patenting because the claims at issue were obvious over claims in four prior art patents); In re Berg, 140 F.3d at 1437, 46 USPQ2d at 1233 (Fed. Cir. 1998) (affirming a holding of obviousness-type double patenting where a patent application claim to a genus is anticipated by a patent claim to a species within that genus). “ELI LILLY AND COMPANY v BARR LABORATORIES, INC., United States Court of Appeals for the Federal Circuit, ON PETITION FOR REHEARING EN BANC (DECIDED: May 30, 2001).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Hu (11,755,471) discloses a host device provides a logical address of target data and memory controller utilizes L2P mapping tables to identify a physical page address of the target data; AMAKI et al. (2021/0286671) discloses a memory system wherein a logical address used by the host for addressing memory system, the management of mapping between each logical address and each physical address is executed using address conversion table, the controller manages mapping using the conversion table, the logical block management table includes entries corresponding to blocks, each entry includes a block ID; Lee discloses a storage device wherein the information structure includes number of buffers of the ring buffer, logical block address LBA value assigned to each of the buffers in the ring buffer; Shveidel et al. (2024/0338322) discloses a LBA array being configured as a ring buffer, allocating free or reclaimed LBAs , update bins structures that contain free or un-allocated logical addresses of MD pages..
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/MARDOCHEE CHERY/Primary Examiner, Art Unit 2133
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