DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 9-11 and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Kwon (US 2020/0336716) in view of Qiu (US 2015/0186303), and further in view of Chuang et al. (US 10,785,386, cited in IDS dated 08/20/2025).
Regarding claim 1, Kwon discloses a display apparatus (Fig. 2; [0045], e.g., display apparatus 100) comprising:
a display (e.g., display panel 110);
a second standard port configured to be connected to a second standard port of an external device ([0126], e.g., a HDMI standard port is connected to a HDMI standard port of an external device 100);
communication circuitry (Fig. 3; [0061], e.g., receiver 120) configured to receive a second standard image and variable refresh rate information through the second standard port ([0128]-[0129], e.g., receive a HDMI standard image with variable refresh rate information (VRR) through the HDMI standard port);
a controller comprising at least one processor (Fig. 3; [0106], e.g., controller 170 comprises a processor 170),
wherein the controller is configured to: change an image processing mode based on the variable refresh rate information ([0130]), and control the display to display a second standard image (Figs 13A-13C; [0161], e.g., display an HDMI image).
Kwon further discloses wherein the external device comprises a first standard port ([0126], [0132], e.g., a display Port standard (DP)).
Kwon does not specifically disclose wherein the second standard port configured to be connected to the first standard port of the external device, wherein the communication circuitry is configured to receive a first standard image, and wherein the controller is configured to convert the first standard image to a second standard image based on the variable refresh rate information.
However, Qiu discloses a display apparatus (Fig. 1; [0013], e.g., the display unit 160)
comprising:
a second standard port ([0013], e.g., the display unit 160 complies with a Dual mode Display Port (DP++) standard) configured to be connected to a first standard port of an external device ([0013], e.g., the signal source unit 120 complies with the DP standard); and
communication circuitry (Fig. 1; [0024],[0032], e.g., a receiving circuit) configured to receive a first standard image and variable refresh rate information through the second standard port ([0013], [0032], e.g., receive a Display Port standard (DP) image signal through the Dual mode Display Port (DP++) standard).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use the teachings of Qiu in the invention of Kwon for receiving a Display Port (DP) standard image through a HDMI standard port because Qiu teaches a display device provides a simpler user interface that allows the users to operate a display device easily without purchasing an extra adapter (see [0035] of Qiu).
Kwon in view of Qiu does not specifically disclose wherein the controller is configured to convert the first standard image to a second standard image based on the variable refresh rate information.
However, Chuang discloses a display apparatus (Fig. 1; col. 2, lines 20-31, e.g., a computer, or any other electronic device capable of providing the HDMI signals to a display) comprising:
a signal converter (Fig. 1; col. 32-67, e.g., 120) configured to convert a first standard image (e.g., the DP signals comprises a DisplayPort (DP) standard image with variable frame rate) to a second standard image (Fig. 2; e.g., HDMI standard image or the image frame 200) based on variable refresh rate information (e.g., converting the DisplayPort (DP) standard image to the HDMI standard image by generating the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync based on the variable refresh rate VRR).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use the teachings of Chuang in the invention of Kwon in view of Qiu for integrating a signal converter into a controller and converting a DisplayPort (DP) standard image to tan HDMI standard image by generating a vertical synchronization signal and a horizontal synchronization signal based on a variable refresh rate in order to improve the display quality (see col. 1, lines 18-28 of Chuang).
Regarding claim 2, Kwon further discloses the display apparatus of claim 1, wherein the controller is further configured to change the image processing mode of a reproduced image based on a vertical synchronization signal included in the variable refresh rate information being in an unstable state ([0130]-[0131], [0136], e.g., when a vertical frequency included in the variable refresh rate information exceeds a preset range, it indicates that the vertical frequency is unstable).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the invention of Kwon in view of Qiu and Chuang for converting a DisplayPort (DP) standard image to an HDMI standard image based on a vertical synchronization signal included in the variable refresh rate information being in an unstable state in order to improve the image quality (see [0136] of Kwon).
Regarding claim 9, Kwon in view of Qiu and Chuang further discloses the display apparatus of claim 1, wherein the first standard port and the first standard image have a DisplayPort (DP) format (Kwon, [0126], [0132], e.g., a DP format. Qiu, [0013], [0032], e.g., a DisplayPort (DP) format), and the second standard port and the second standard image have a High Definition Multimedia Interface (HDMI) format (Kwon, [[0126], 0129], e.g., a HDMI format).
Regarding claim 10, Kwon discloses a method of controlling a display apparatus (Fig. 2; [0045], e.g., display apparatus 100) including a second standard port connected to a second standard port of an external device ([0126], e.g., a HDMI standard port is connected to a HDMI standard port of an external device 100) and communication circuitry (Fig. 3; [0061], e.g., receiver 120) configured to receive a second standard image and variable refresh rate information through the second standard port ([0128]-[0129], e.g., receive a HDMI standard image with variable refresh rate information (VRR) through the HDMI standard port), the method comprising:
changing an image processing mode based on the variable refresh rate information ([0130]), and displaying a second standard image (Figs 13A-13C; [0161], e.g., display an HDMI image).
Kwon further discloses wherein the external device comprises a first standard port ([0126], [0132], e.g., a display Port standard (DP)).
Kwon does not specifically disclose wherein the second standard port is connected to the first standard port of the external device and the communication circuitry is configured to receive a first standard image through the second standard port, and the method comprising: converting the first standard image to a second standard image based on the variable refresh rate information.
However, Qiu discloses a method of controlling a display apparatus (Fig. 1; [0013], e.g., display apparatus 160) including a second standard port ([0013], e.g., a Dual mode Display Port (DP++) standard) connected to a first standard port of an external device ([0013], e.g., the signal source unit 120 comprises a Display Port (DP) standard) and communication circuitry ([0013], e.g., a receiving unit in the display apparatus 160) configured to receive a first standard image through the second standard port ([0013], [0024], [0032], e.g., receive the DP image through the Dual mode Display Port (DP++) standard).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use the teachings of Qiu in the invention of Kwon for receiving a Display Port (DP) standard image through a HDMI standard port because Qiu teaches a display device provides a simpler user interface that allows the users to operate a display device easily without purchasing an extra adapter (see [0035] of Qiu).
Kwon in view of Qiu does not specifically disclose the method comprising: converting the first standard image to a second standard image based on the variable refresh rate information.
However, Chuang discloses a display apparatus (Fig. 1; col. 2, lines 20-31, e.g., a computer, or any other electronic device capable of providing the HDMI signals to a display) comprising:
a signal converter (Fig. 1; col. 32-67, e.g., 120) configured to convert a first standard image (e.g., the DP signals comprises a DisplayPort (DP) standard image with variable frame rate) to a second standard image (Fig. 2; e.g., HDMI standard image or the image frame 200) based on variable refresh rate information (e.g., converting the DisplayPort (DP) standard image to the HDMI standard image by generating the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync based on the variable refresh rate VRR).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use the teachings of Chuang in the invention of Kwon in view of Qiu for integrating a signal converter into a controller and converting a DisplayPort (DP) standard image to tan HDMI standard image by generating a vertical synchronization signal and a horizontal synchronization signal based on a variable refresh rate in order to improve the display quality (see col. 1, lines 18-28 of Chuang).
Regarding claim 11, Kwon further discloses the method of claim 10, comprising changing the image processing mode of a reproduced image based on a vertical synchronization signal included in the variable refresh rate information being in an unstable state ([0130]-[0131], [0136], e.g., when a vertical frequency included in the variable refresh rate information exceeds a preset range, it indicates that the vertical frequency is unstable).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the invention of Kwon in view of Qiu and Chuang for converting a DisplayPort (DP) standard image to an HDMI standard image based on a vertical synchronization signal included in the variable refresh rate information being in an unstable state in order to improve the image quality (see [0136] of Kwon).
Regarding claim 18, Kwon discloses a non-transitory computer readable medium storing one or more programs (Fig. 3; [0107], e.g., a memory stores a control program), the one or more programs comprising instructions to, when executed by an electronic device (Figs 2-3; e.g., a display device 100), cause the electronic device to:
change an image processing mode based on a variable refresh rate information ([0130]), and displaying a second standard image (Figs 13A-13C; [0161], e.g., display an HDMI image),
wherein the variable refresh rate information is received through a standard port ([0087], [0128]-[0129], e.g., receive variable refresh rate (VRR) information from received image through a HDMI standard).
Kwon does not specifically disclose the electronic device is configured to:
receive a first standard image is received through the standard port; and
convert the first standard image to the second standard image based on the variable refresh rate information.
Qiu discloses a display apparatus (Fig. 1; [0013], e.g., the display unit) configured to receive a first standard image through a standard port ([0013], [0032], e.g., the display unit 160 complies configured to receive a Display Port standard image through a Dual mode Display Port (DP++) standard).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use the teachings of Qiu in the invention of Kwon for receiving a Display Port (DP) standard image through a HDMI standard port because Qiu teaches a display device provides a simpler user interface that allows the users to operate a display device easily without purchasing an extra adapter (see [0035] of Qiu).
Kwon in view of Qiu does not specifically disclose the electronic device configured to convert the first standard image to the second standard image based on the variable refresh rate information.
However, Chuang discloses a display apparatus (Fig. 1; col. 2, lines 20-31, e.g., a computer, or any other electronic device capable of providing the HDMI signals to a display) comprising:
a signal converter (Fig. 1; col. 32-67, e.g., 120) configured to convert a first standard image (e.g., the DP signals comprises a DisplayPort (DP) standard image with variable frame rate) to a second standard image (Fig. 2; e.g., HDMI standard image or the image frame 200) based on variable refresh rate information (e.g., converting the DisplayPort (DP) standard image to the HDMI standard image by generating the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync based on the variable refresh rate VRR).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use the teachings of Chuang in the invention of Kwon in view of Qiu for integrating a signal converter into a controller and converting a DisplayPort (DP) standard image to an HDMI standard image by generating a vertical synchronization signal and a horizontal synchronization signal based on a variable refresh rate in order to improve the display quality (see col. 1, lines 18-28 of Chuang).
Regarding claim 19, Kwon further discloses the non-transitory computer readable storage medium of claim 18, wherein the image processing mode is changed based on a vertical synchronization signal included in the variable refresh rate information being in an unstable state ([0130]-[0131], [0136], e.g., when a vertical frequency included in the variable refresh rate information exceeds a preset range, it indicates that the vertical frequency is unstable).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the invention of Kwon in view of Qiu and Chuang for converting a DisplayPort (DP) standard image to an HDMI standard image based on a vertical synchronization signal included in the variable refresh rate information being in an unstable state in order to improve the image quality (see [0136] of Kwon).
Claim(s) 3 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Kwon (US 2020/0336716) in view of Qiu (US 2015/0186303), and further in view of Chuang et al. (US 10,785,386), and further in view of Huang et al. (US 2021/0090523).
Regarding claim 3, Kwon in view of Qiu and Chuang does not specifically disclose the display apparatus of claim 2, wherein the controller is further configured to determine that the vertical synchronization signal is in an unstable state based on variation in a timing at which the vertical synchronization signal transitions to a high level.
However, Huang discloses a display apparatus (Fig. 1; [0051], e.g. 102) comprising a processor (Fig. 1; 118) configured to determine that a vertical synchronization signal is in an unstable state based on variation in a timing at which a vertical synchronization signal transitions to a high level (Figs 4A and 4F; [0078], [0091]-[0092], e.g., detecting a variable VSYNC frequency based on a time duration between a rising edge of a first VSYNC signal and a rising edge of a second VSYNC signal).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use the teachings of Huang in the invention of Kwon in view of Qiu and Chuang for detecting a vertical synchronization signal having various frequencies based on variation in a timing at which the vertical synchronization signal transitions to a high level in order to determine that the vertical synchronization signal is unstable.
Regarding claim 12, Kwon in view of Qiu and Chuang does not specifically disclose the method of claim 11, wherein the vertical synchronization signal is determined to be in an unstable state based on variation in a timing at which the vertical synchronization signal transitions to a high level.
However, Huang discloses a display apparatus (Fig. 1; [0051], e.g. 102) comprising
a processor (Fig. 1; 118) configured to determine that a vertical synchronization signal is in an unstable state based on variation in a timing at which a vertical synchronization signal transitions to a high level (Figs 4A and 4F; [0078], [0091]-[0092], e.g., detecting a variable VSYNC frequency based on a time duration between a rising edge of a first VSYNC signal and a rising edge of a second VSYNC signal).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use the teachings of Huang in the invention of Kwon in view of Qiu and Chuang for detecting a vertical synchronization signal having various frequencies based on variation in a timing at which the vertical synchronization signal transitions to a high level in order to determine that the vertical synchronization signal is unstable.
Claim(s) 4-8, 13-17 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kwon (US 2020/0336716) in view of Qiu (US 2015/0186303), and further in view of Chuang et al. (US 10,785,386), and further in view of Lin (US 7,486,283).
Regarding claim 4, Kwon in view of Qiu and Chuang does not specifically disclose the display apparatus of claim 1, wherein the controller is further configured to match an output clock count of the second standard image with an output clock count of the first standard image.
However, Lin discloses a display device (Fig. 1; col. 4, lines 43-53, e.g., a display device 200) wherein a controller configured to match an output clock count of a standard out image with an input clock count of a standard input image (Figs 2 and 8; col. 1, lines 52-60, col. 4, lines 50-60, col. 5, lines 40-67, col. 6, lines 1-9, col. 13, lines 45-50; e.g., synchronize an output clock count PCLK2 of a standard output image (VGA or Super VGA) with an input clock count PCLK1 of a standard input image (VGA or Super VGA)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use the teachings of Lin in the invention of Kwon in view of Qiu and Chuang for synchronizing a pixel clock count of a second standard image with a pixel clock count of a first standard image in order to display an improved image by a display panel (col. 6, lines 1-9 of Lin).
Regarding claim 5. Kwon in view of Qiu and Chuang does not specifically disclose the display apparatus of claim 1, wherein the controller is further configured to match a horizontal synchronization signal of the second standard image with a horizontal synchronization signal of the first standard image.
However, Lin discloses a display device (Fig. 1; col. 4, lines 43-53, e.g., a display device 200) wherein a controller configured to match a horizontal synchronization signal of a standard output image with a horizontal synchronization signal of a standard output image (Figs 2 and 8; col. 1, lines 52-60, col. 10, lines 1-5, col. 13, lines 45-50; e.g., the horizontal synchronization signal (HSYNC2) of a standard output image (VGA or Super VGA) is synchronized to the horizontal synchronization signal (HSYNC1) of a standard input image (VGA or Super VGA)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use the teachings of Lin in the invention of Kwon in view of Qiu and Chuang for synchronizing a horizontal synchronization signal of a second standard image with a horizontal synchronization signal of a first standard image in order to provide an image in a format suitable for display by a display device (col. 5, lines 10-12 of Lin).
Regarding claim 6, Kwon in view of Qiu and Chuang does not specifically disclose the display apparatus of claim 1, wherein the controller is further configured to match a vertical synchronization signal of the second standard image with a vertical synchronization signal of the first standard image.
However, Lin discloses a display device (Fig. 1; col. 4, lines 43-53, e.g., a display device 200) wherein a controller is configured to match a vertical synchronization signal of a standard output image with a vertical synchronization signal of a standard input image (Figs 2 and 10; col. 1, lines 52-60, col. 11, lines 19-34, col. 13, lines 45-50; e.g., the vertical synchronization signal (VSYNC2) of a standard output image (VGA or Super VGA) is synchronized to the vertical synchronization signal (VSYNC1) of a standard input image (VGA or Super VGA)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use the teachings of Lin in the invention of Kwon in view of Qiu and Chuang for synchronizing a vertical synchronization signal of a second standard image with a vertical synchronization signal of a first standard image in order to provide an image in a format suitable for display by a display device (col. 5, lines 10-12 of Lin).
Regarding claim 7, Kwon in view of Qiu and Chuang does not specifically disclose the display apparatus of claim 1, wherein the controller is further configured to match a synchronization pulse duration of a horizontal synchronization signal of the second standard image with a synchronization pulse duration of a horizontal synchronization signal of the first standard image.
However, Lin discloses a display device (Fig. 1; col. 4, lines 43-53, e.g., a display device 200) wherein a controller configured to match a synchronization pulse duration of a horizontal synchronization signal of a standard output image with a synchronization pulse duration of a horizontal synchronization signal of a standard input image (Figs 2 and 8; col. 1, lines 52-60, col. 10, lines 1-5, col. 13, lines 45-50; e.g., match a synchronization pulse duration of the horizontal synchronization signal (HSYNC2) of a standard output image (VGA or Super VGA) with a synchronization pulse duration of the horizontal synchronization signal (HSYNC1) of a standard input image (VGA or Super VGA)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use the teachings of Lin in the invention of Kwon in view of Qiu and Chuang for matching a synchronization pulse duration of a horizontal synchronization signal of a second standard image with a synchronization pulse duration of a horizontal synchronization signal of a first standard image in order to provide an image in a format suitable for display by a display device (col. 5, lines 10-12 of Lin).
Regarding claim 8, Kwon in view of Qiu and Chuang does not specifically disclose the display apparatus of claim 1, wherein the controller is further configured to match a back porch of the second standard image with a back porch of the first standard image.
However, Lin discloses a display device (Fig. 1; col. 4, lines 43-53, e.g., a display device 200) wherein a controller configured to match a back porch of an output standard image with a back porch of an input standard image (Figs 2 and 8; col. 1, lines 52-60, col. 10, lines 1-5, col. 13, lines 45-62; e.g., match a back porch (K clock cycles) of an output standard image with a back porch (K clock cycles) of an input standard image by synchronizing the horizontal synchronization signal (HSYNC2) of a standard output image (VGA or Super VGA) with the horizontal synchronization signal (HSYNC1) of a standard input image (VGA or Super VGA)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use the teachings of Lin in the invention of Kwon in view of Qiu and Chuang for matching a back porch of a second standard image with a back porch of a first standard image in order to provide an image in a format suitable for display by a display device (col. 5, lines 10-12 of Lin).
Regarding claim 13, Kwon in view of Qiu and Chuang does not specifically disclose the method of claim 10, wherein the converting the first standard image to the second standard image comprises matching an output clock count of the second standard image with an output clock count of the first standard image to convert the first standard image to the second standard image.
However, Lin discloses a display device (Fig. 1; col. 4, lines 43-53, e.g., a display device 200) wherein a controller configured to match an output clock count of a standard out image with an input clock count of a standard input image (Figs 2 and 8; col. 1, lines 52-60, col. 4, lines 50-60, col. 5, lines 40-67, col. 6, lines 1-9, col. 13, lines 45-50; e.g., synchronize an output clock count PCLK2 of a standard output image (VGA or Super VGA) with an input clock count PCLK1 of a standard input image (VGA or Super VGA)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use the teachings of Lin in the invention of Kwon in view of Qiu and Chuang for synchronizing a pixel clock count of a second standard image with a pixel clock count of a first standard image in order to display an improved image by a display panel (col. 6, lines 1-9 of Lin).
Regarding claim 14, Kwon in view of Qiu and Chuang does not specifically disclose the method of claim 10, wherein the converting the first standard image to the second standard image comprises matching a horizontal synchronization signal of the second standard image with a horizontal synchronization signal of the first standard image to convert the first standard image to the second standard image.
However, Lin discloses a display device (Fig. 1; col. 4, lines 43-53, e.g., a display device 200) wherein a controller configured to match a horizontal synchronization signal of a standard output image with a horizontal synchronization signal of a standard output image (Figs 2 and 8; col. 1, lines 52-60, col. 10, lines 1-5, col. 13, lines 45-50; e.g., the horizontal synchronization signal (HSYNC2) of a standard output image (VGA or Super VGA) is synchronized to the horizontal synchronization signal (HSYNC1) of a standard input image (VGA or Super VGA)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use the teachings of Lin in the invention of Kwon in view of Qiu and Chuang for synchronizing a horizontal synchronization signal of a second standard image with a horizontal synchronization signal of a first standard image in order to provide an image in a format suitable for display by a display device (col. 5, lines 10-12 of Lin).
Regarding claim 15, Kwon in view of Qiu and Chuang does not specifically disclose the method of claim 10, wherein the converting the first standard image to the second standard image comprises matching a vertical synchronization signal of the second standard image with a vertical synchronization signal of the first standard image to convert the first standard image to the second standard image.
However, Lin discloses a display device (Fig. 1; col. 4, lines 43-53, e.g., a display device 200) wherein a controller is configured to match a vertical synchronization signal of a standard output image with a vertical synchronization signal of a standard input image (Figs 2 and 10; col. 1, lines 52-60, col. 11, lines 19-34, col. 13, lines 45-50; e.g., the vertical synchronization signal (VSYNC2) of a standard output image (VGA or Super VGA) is synchronized to the vertical synchronization signal (VSYNC1) of a standard input image (VGA or Super VGA)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use the teachings of Lin in the invention of Kwon in view of Qiu and Chuang for synchronizing a vertical synchronization signal of a second standard image with a vertical synchronization signal of a first standard image in order to provide an image in a format suitable for display by a display device (col. 5, lines 10-12 of Lin).
Regarding claim 16, Kwon in view of Qiu and Chuang does not specifically disclose the method of claim 10, wherein the converting the first standard image to the second standard image comprises matching a synchronization pulse duration of a horizontal synchronization signal of the second standard image with a synchronization pulse duration of a horizontal synchronization signal of the first standard image to convert the first standard image to the second standard image.
However, Lin discloses a display device (Fig. 1; col. 4, lines 43-53, e.g., a display device 200) wherein a controller configured to match a synchronization pulse duration of a horizontal synchronization signal of a standard output image with a synchronization pulse duration of a horizontal synchronization signal of a standard input image (Figs 2 and 8; col. 1, lines 52-60, col. 10, lines 1-5, col. 13, lines 45-50; e.g., match a synchronization pulse duration of the horizontal synchronization signal (HSYNC2) of a standard output image (VGA or Super VGA) with a synchronization pulse duration of the horizontal synchronization signal (HSYNC1) of a standard input image (VGA or Super VGA)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use the teachings of Lin in the invention of Kwon in view of Qiu and Chuang for matching a synchronization pulse duration of a horizontal synchronization signal of a second standard image with a synchronization pulse duration of a horizontal synchronization signal of a first standard image in order to provide an image in a format suitable for display by a display device (col. 5, lines 10-12 of Lin).
Regarding claim 17, Kwon in view of Qiu and Chuang does not specifically disclose the method of claim 10, wherein the converting the first standard image to the second standard image comprises matching a back porch of the second standard image with a back porch of the first standard image to convert the first standard image to the second standard image.
However, Lin discloses a display device (Fig. 1; col. 4, lines 43-53, e.g., a display device 200) wherein a controller configured to match a back porch of an output standard image with a back porch of an input standard image (Figs 2 and 8; col. 1, lines 52-60, col. 10, lines 1-5, col. 13, lines 45-62; e.g., match a back porch (K clock cycles) of an output standard image with a back porch (K clock cycles) of an input standard image by synchronizing the horizontal synchronization signal (HSYNC2) of a standard output image (VGA or Super VGA) with the horizontal synchronization signal (HSYNC1) of a standard input image (VGA or Super VGA)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use the teachings of Lin in the invention of Kwon in view of Qiu and Chuang for matching a back porch of a second standard image with a back porch of a first standard image in order to provide an image in a format suitable for display by a display device (col. 5, lines 10-12 of Lin).
Regarding claim 20, Kwon in view of Qiu and Chuang does not specifically disclose the non-transitory computer readable storage medium of claim 18, wherein the non-transitory computer readable storage medium further store instructions to match an output clock count of the second standard image with an output clock count of the first standard image to convert the first standard image to the second standard image.
However, Lin discloses a display device (Fig. 1; col. 4, lines 43-53, e.g., a display device 200) wherein a controller configured to match an output clock count of a standard out image with an input clock count of a standard input image (Figs 2 and 8; col. 1, lines 52-60, col. 4, lines 50-60, col. 5, lines 40-67, col. 6, lines 1-9, col. 13, lines 45-50; e.g., synchronize an output clock count PCLK2 of a standard output image (VGA or Super VGA) with an input clock count PCLK1 of a standard input image (VGA or Super VGA)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use the teachings of Lin in the invention of Kwon in view of Qiu and Chuang for synchronizing a pixel clock count of a second standard image with a pixel clock count of a first standard image in order to display an improved image by a display panel (col. 6, lines 1-9 of Lin).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lee (US 2011/0193884) discloses a display system (Fig. 3) comprising a first standard port ([0012]) configured to transmit a first standard image from a source to a second standard portion of a display device ([0012], [0014]).
Sharma et al. (US 2013/0227631) discloses a display system (Fig. 1) comprising a video processing system configured to convert a first standard image to a second standard image (Fig. 3; [0025]-[0027]).
Liu et al. (US 2010/0091180) discloses a display system comprising a host device, a signal conversion apparatus and a display device (Fig. 1; [0017), wherein the signal conversion apparatus is configured to convert a first standard image to a second standard image ([0017]-[0018]).
Lee et al. (US 7,548,233) discloses a display device comprising an image scaling circuit configured to convert a first image to a second image by matching an input vertical synchronization signal of the first image with an output vertical synchronization signal of the second image (Figs 6-7; col. 4, lines 30-43, e.g., the input Vsync signal 610 and the output Vsync signal 630 are synchronized to prevent the appearance of short lines and long lines).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HONG ZHOU whose telephone number is (571)270-5372. The examiner can normally be reached 9:00-5:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, BENJAMIN C LEE can be reached at 571-272-2963. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/HONG ZHOU/Primary Examiner, Art Unit 2629
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