DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Action is in response to communications filed 08/20/2025.
Claims 1-24 are pending.
Claims 1-24 are rejected.
The Examiner notes the current action does not include prior art rejections over the current presentation of the claims 7-12 and 19-24. The cited relevant prior art references made of record below are considered as pertinent to the claims and disclosed details provided in the Specification.
The claims are subject to the rejections provided herein which must be addressed accordingly.
Priority
Applicant’s priority claim as a divisional to US Application 19/237,999 filed 06/13/2025 which claims priority to provisional US Application 63/667,695 filed 07/04/2024 is herein acknowledged.
Information Disclosure Statement
As required by M.P.E.P. 609(C), the applicant’s submission of the Information Disclosure Statement dated 08/20/2025 is acknowledged by the examiner and the cited references have been considered in the examination of the claims now pending. As required by M.P.E.P 609 C(2), a copy of the PTOL-1449 initialed and dated by the examiner is attached to the instant office action.
Drawings
The applicant’s drawings submitted on 08/20/2025 are acceptable for examination purposes.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2, 7-12, 15, and 19-24 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 2 recites “a host device for providing direct memory access (DMA) requests” and herein the recitation of “DMA requests” lacks proper antecedent basis with respect to the recitation of “DMA requests” provided by the non-host device as recited in claim 1 from which claim 2 depends. This results in lack of clarity for subsequent limitation recited in claim 1 regarding the steps pertaining to the DMA requests which specifically indicate the DMA request “received from the non-host device”. Appropriate amendments should be made to clearly indicate the processing performed by the request manager as also processing the requests from the host device.
Claim 15, with respect to claim 14, recites the similar issue as identified for claim 2.
Claim 7 recites “wherein the DMA request and the plurality of DMA commands are provided in the non-host device address space…” (Emphasis added). Herein use of the phrase “provided in” is unclear as prior recitation of the term “provided” as used in claim 1, from which claim 7 depends, utilizes the term in the form of “making available for use” or “supply” wherein data from the first memory is transferred to the second memory. Therefore in the present claim language, the term “provided in” is indefinite referring to the DMA request and DMA commands as while the subsequent limitations of claim 7 recite “an address translating unit for translating non-host device address space addresses”, it is not made clear and evident that the prior limitation indicates explicitly “provided in” refers to the addresses of the DMA request and plurality of DMA commands. It is suggested to amend the language to indicate clear reference to the addresses of the DMA request and plurality of DMA commands.
Claims 8-12 with respect to Claim 1 and Claims 19-24 with respect to Claim 14 recite the similar issue as Claim 7 identified above.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103(a) are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-6, 14-15, and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Barry et al. (US 2007/0088868) in view of Rochford et al. (US 2018/0203815) and further in view of Bonola et al. (US 2006/0010261).
Regarding claim 1, Barry discloses, in the italicized portions, a system comprising: a first memory having a first address space; a second memory having a second address space (Claim 7. A processor system for fetching direct memory access (DMA) instructions and directing the transfer of data, the processor system comprising: a first memory having a first address space; a second memory having a second address space); a non-host device for providing direct memory access (DMA) requests, the non-host device having a non-host device address space; and a DMA controller system (Claim 7. … a DMA controller comprising a DMA processor operating within the DMA controller to fetch DMA instructions beginning at a memory address location within the first address space or the second address space as directed by the data bus master, the DMA processor operating in response to the fetched DMA instructions to direct the transfer of data between the first memory and the second memory.) including: a request manager for receiving a DMA request for transferring data from the first memory and providing the data to the second memory, the DMA request received from the non-host device, the request manager forming a plurality of DMA commands from the DMA request; and an agent coupled to the request manager and operating in the address spaces of the first and second memories, the agent for receiving the plurality of DMA commands from the request manager and performing a read transaction from the first memory and a write transaction to the second memory for each DMA command. Herein Barry discloses the system which performs steps for executing direct memory access (DMA) operations by a DMA controller for transferring data between a first memory and second memory each having a respective address space. Barry does not explicitly address the elements of the non-host device having a non-host address space and providing DMA requests and the elements of the DMA system including the request manager for forming a plurality of DMA commands from the DMA request and an agent to receive the plurality of DMA commands to perform the read transaction from the first memory and write transaction to the second memory for each DMA command. Regarding the request manager and agent and corresponding elements, Rochford discloses in Paragraph [0002] “In addition, multiple DMA channels corresponding to particular DMA transfers or devices are typically supported by having a processor initiate a DMA-mediated transfer (e.g., by setting values in DMA registers to specify, for a particular DMA channel, source and destination addresses as well as a counter to control the number of units of data to be transferred) and then having a corresponding one of the auxiliary processor handle the DMA transfer. In some existing systems, the auxiliary processor is embodied as a multi-channel DMA (MCDMA) controller…” Herein Rochford discloses the multi-channel DMA system which may be configured in a plurality of modes to execute DMA operations without host processor intervention. Specifically, Rochford further discloses in Paragraph [0009] “In a second “link list configuration” mode, a sequence of commands may be written directly into the command queue structure for initiating a fetch of a linked list descriptor chain for loading into the context registers.” In this case, the MCDMA engine or controller 14 is determined, under broadest reasonable interpretation of the term, as a request manager which receives the DMA request to then generate a plurality of DMA commands in response to the request and the MCDMA engine also functions as the agent which performs the write and read transactions to the requested memory as noted in Paragraph [0018]. In this manner, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the DMA controller as disclosed by Barry with the controller configuration as taught by Rochford in order to handle the read and write transactions between the first and second memories in order to offload work from the host processors (Rochford [0009]). Rochford does not explicitly address the non-host device and the corresponding limitations. Regarding this aspect of the claim, Bonola discloses in Paragraphs [0033] and [0043] “[0033] More particularly, a client can attempt to acquire a DMA channel from HCDMA controller 320. If the HCDMA controller 320 has a free DMA channel as indicated by its control block (not shown), the HCDMA controller 320 returns the address of that free DMA channel to the client… As can be appreciated, the client can continue to "walk" the chain until it finds a HCDMA controller with a free DMA channel. Further, the client can "walk" the chain of HCDMA controllers without the intervention of the OS. Accordingly, non-host based entities, such as bus masters, can acquire DMA channels. [0044] To render a DMA transaction (step 445), the client could write to the descriptor the length of the data being transferred (field 610), the source of the data (field 620) and the destination of the data (field 625).” Herein Bonola discloses that non-host based entities may acquire DMA channels to perform DMA transactions. The clients in Bonola are a plurality of non-host entities including bus masters. In view of Barry wherein claim 8 recites the processor system as having a third address space belonging to a data bus master, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the requests may be provided from a non-host device, including the data bus master, having a respective address space to execute DMA transactions without requiring processor intervention (Bonola [0004]). Barry, Rochford, and Bonola are analogous art because they are from the same field of endeavor of managing DMA operations.
Regarding claim 2, Barry, Rochford, and Bonola in combination further disclose the system of claim 1, further comprising: a host device for providing direct memory access (DMA) requests, wherein the request manager further receives DMA requests from the host device (Rochford [0022] In an example embodiment, the processing shown in FIG. 3 may be performed by a multi-channel direct memory access (MCDMA) hardware engine interface that is connected to receive DMA requests from one or more host processors and to execute direct memory access transfers between one or more memory and/or other peripheral interfaces in response to the DMA transfer request(s). and Bonola [0009] Additionally, a DMA controller is needed that allows access by both host processors and non-host processor devices to dynamically acquire and release DMA channels.). Herein Rochford and Bonola both acknowledge that host processors may transmit DMA transfer requests to the DMA controller.
Regarding claim 3, Barry, Rochford, and Bonola in combination further disclose the system of claim 1, wherein the first and second memories are different (Rochford [0011] In addition, memory 18 may include storage of any suitable type, such as, for example, read only memory (ROM), random access memory (RAM), non-volatile memory (e.g., Flash), etc.). Herein Rochford discloses the plurality of memory types that may be included in the system. One of ordinary skill in the art may recognize that the first and second memories may be of different types as there are a plurality of memory types supported.
Regarding claim 4, Barry, Rochford, and Bonola in combination further disclose the system of claim 1, wherein the first and second memories are the same (Rochford [0011] In addition, memory 18 may include storage of any suitable type, such as, for example, read only memory (ROM), random access memory (RAM), non-volatile memory (e.g., Flash), etc.). Herein Rochford discloses the plurality of memory types that may be included in the system. One of ordinary skill in the art may recognize that the first and second memories may be of same type as a plurality of memory types are supported and under the broadest reasonable interpretation of the claim language. The claim does not otherwise identify distinguishing detail through the use of the same memory over the prior art.
Regarding claim 5, Barry, Rochford, and Bonola in combination further disclose the system of claim 1, wherein the agent includes a multi-channel DMA controller which receives the plurality of DMA commands (Rochford [0010] In the illustrated configuration, the data processing system 10 includes one or more processors 12, a multi-channel direct memory access (MCDMA) engine or controller 14, I/O devices 16, and memory 18.). Herein Rochford explicitly identifies use of a MCDMA engine or controller 14 for handling the DMA transactions.
Regarding claim 6, Barry, Rochford, and Bonola in combination further disclose the system of claim 5, wherein the request manager includes a distribution controller for selecting the channel of the DMA controller to receive the plurality of DMA commands (Rochford [0016] In addition, software controlled inputs to the steering/multiplex circuitry 220-223 are used to enable each CMDQFIFO to be masked as a resource for the CMDQDMA Controller 210 to insert commands into selected CMDQFIFOs, while the other CMDQFIFOs are manually driven by the APB Interface 204.). Herein Rochford discloses as part of the transaction handling that the selected FIFO receives the commands from the CMDQDMA controller which is determined under the broadest reasonable interpretation of the claim language to meet the requirements of distribution controller.
Regarding claim 14, Barry discloses, in the italicized portions, a direct memory access (DMA) controller system for transferring data between a first memory having a first address space and a second memory having a second address space based on DMA requests (Claim 7. A processor system for fetching direct memory access (DMA) instructions and directing the transfer of data, the processor system comprising: a first memory having a first address space; a second memory having a second address space … a DMA controller comprising a DMA processor operating within the DMA controller to fetch DMA instructions beginning at a memory address location within the first address space or the second address space as directed by the data bus master, the DMA processor operating in response to the fetched DMA instructions to direct the transfer of data between the first memory and the second memory.) provided by a non-host device, the non- host device having a non-host device address space, the DMA controller system comprising: a request manager for receiving a DMA request for transferring data from the first memory and providing the data to the second memory, the DMA request received from the non-host device, the request manager forming a plurality of DMA commands from the DMA request; and an agent coupled to the request manager and operating in the address spaces of the first and second memories, the agent for receiving the plurality of DMA commands from the request manager and performing a read transaction from the first memory and a write transaction to the second memory for each DMA command. Herein Barry discloses the system which performs steps for executing direct memory access (DMA) operations by a DMA controller for transferring data between a first memory and second memory each having a respective address space. Barry does not explicitly address the elements of the non-host device having a non-host address space and providing DMA requests and the elements of the DMA system including the request manager for forming a plurality of DMA commands from the DMA request and an agent to receive the plurality of DMA commands to perform the read transaction from the first memory and write transaction to the second memory for each DMA command. Regarding the request manager and agent and corresponding elements, Rochford discloses in Paragraph [0002] the multi-channel DMA system which may be configured in a plurality of modes to execute DMA operations without host processor intervention. Specifically, Rochford further discloses in Paragraph [0009] “In a second “link list configuration” mode, a sequence of commands may be written directly into the command queue structure for initiating a fetch of a linked list descriptor chain for loading into the context registers.” In this case, the MCDMA engine or controller 14 is determined, under broadest reasonable interpretation of the term, as a request manager which receives the DMA request to then generate a plurality of DMA commands in response to the request and the MCDMA engine also functions as the agent which performs the write and read transactions to the requested memory as noted in Paragraph [0018]. In this manner, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the DMA controller as disclosed by Barry with the controller configuration as taught by Rochford in order to handle the read and write transactions between the first and second memories in order to offload work from the host processors (Rochford [0009]). Rochford does not explicitly address the non-host device and the corresponding limitations. Regarding this aspect of the claim, Bonola discloses in Paragraphs [0033] and [0043] that non-host based entities may acquire DMA channels to perform DMA transactions. The clients in Bonola are a plurality of non-host entities including bus masters. In view of Barry wherein claim 8 recites the processor system as having a third address space belonging to a data bus master, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the requests may be provided from a non-host device, including the data bus master, having a respective address space to execute DMA transactions without requiring processor intervention. Claim 14 is rejected on a similar basis as claim 1.
Regarding claim 15, Barry, Rochford, and Bonola in combination further disclose the DMA controller system of claim 14, wherein the DMA controller system further receives DMA requests provided by a host device (Rochford [0022] and Bonola [0009]). Claim 15 is rejected on a similar basis as claim 2.
Regarding claim 17, Barry, Rochford, and Bonola in combination further disclose the DMA controller system of claim 14, wherein the agent includes a multi-channel DMA controller which receives the plurality of DMA commands (Rochford [0010]). Claim 17 is rejected on a similar basis as claim 5.
Regarding claim 18, Barry, Rochford, and Bonola in combination further disclose the DMA controller system of claim 17, wherein the request manager includes a distribution controller for selecting the channel of the DMA controller to receive the plurality of DMA commands (Rochford [0016]). Claim 18 is rejected on a similar basis as claim 6.
Claims 13 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Barry in view of Rochford and further in view of Bonola and still further in view of Kachare et al. (US 2017/0083463).
Regarding claim 13, Barry, Rochford, and Bonola do not explicitly disclose the system of claim 1, wherein the DMA request and DMA commands are transferred in a control plane and the read and write transactions are performed in a data plane. Regarding this limitation, Kachare discloses in Paragraph [0019] “The front end processing unit 142 receives read and/or write requests operating in a control plane, and the data transfer arbiter 110 transfers the data across interface 102 between the computing host 120 and storage controller 100 in a data plane. The control plane and data plane are illustrated in FIG. 2 as control plane 240 and data plane 230.” Herein Kachare discloses utilizing a control plane and data plane for communications when handling transactions including DMA operations. It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the sectioned interface planes as discussed by Kachare into the system configuration as taught by Barry for organizing handling communications between memory components while processing DMA requests (Kachare [0038]). Barry, Rochford, Bonola, and Kachare are analogous art because they are from the same field of endeavor of managing DMA operations.
Regarding claim 16, Barry, Rochford, and Bonola in combination further disclose the DMA controller system of claim 14, wherein the DMA request and DMA commands are transferred in a control plane and the read and write transactions are performed in a data plane. Regarding this limitation, Kachare discloses in Paragraph [0019] “The front end processing unit 142 receives read and/or write requests operating in a control plane, and the data transfer arbiter 110 transfers the data across interface 102 between the computing host 120 and storage controller 100 in a data plane. The control plane and data plane are illustrated in FIG. 2 as control plane 240 and data plane 230.” Herein Kachare discloses utilizing a control plane and data plane for communications when handling transactions including DMA operations. It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the sectioned interface planes as discussed by Kachare into the system configuration as taught by Barry for organizing handling communications between memory components while processing DMA requests (Kachare [0038]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Arumilli (US 12,645,618) – Column 3 wherein non-host device handling memory access requests is disclosed.
Greathouse et al. (US 2023/0132931) – Paragraphs [0024-25] wherein DMA engines handling DMA transfers is discussed.
Deidda (US 2023/0259467) – Paragraph [0059] wherein an agent handling a data transfer task is disclosed.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDER J YOON whose telephone number is (408)918-7629. The examiner can normally be reached on Monday-Friday 8am-3pm ET. The examiner’s email is alexander.yoon2@uspto.gov.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jared Rutz can be reached on 571-272-5535. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ALEXANDER YOON/
Examiner, Art Unit 2135
/JARED I RUTZ/ Supervisory Patent Examiner, Art Unit 2135
