DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4 and 7-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Qiu et al. (US 2022/0393044).
Regarding claim 1, Qiu discloses a solar cell in Figure 1, comprising:
a substrate (10, [90]), having a first surface (back surface) and a second surface (front surface) opposite to the first surface, the first surface (back surface) including an edge region (region under second conductive regions 30) and a center region (region under first conductive regions 20), the edge region surrounding the center region (Figure 1), and the edge region being substantially flush with, or closer to the second surface than, the center region (As shown in Figure 1, the edge region is closer to the second surface than the center region);
a dielectric layer (first dielectric layer 21), formed on the center region and not on the edge region (Figure 1, [87] and [92]);
a doped semiconductor layer (22), formed over a surface of the dielectric layer (21) facing away from the substrate (10) ([87] and [91]);
a passivation layer (second dielectric layer 40), formed over the edge region and a surface of the doped semiconductor layer (22) facing away from the dielectric layer (21) (Figure 1 and [88]);
a first electrode (middle electrode 50) formed over the center region (region under first conductive region 20) to be in electrical contact with the doped semiconductor layer (22) (Figure 1 and [100]);
a second electrode formed over the edge region to be in electrical contact with the edge region (As shown in Figure 1 and [100], the outer electrodes 50 are in the edge region).
Regarding claim 2, Qiu discloses all of the claim limitations as set forth above. Qiu additionally discloses that the substrate has a first boundary, and the center region has a second boundary facing the edge region; the first boundary and the second boundary form opposite boundaries of the edge region; and a spacing between the second boundary and the first boundary is less than 300 µm (The term “edge region” is broad and the edge region can be defined to be a distance of less than 300 µm from the outer boundary of the substrate.).
Regarding claims 3 and 4, Qiu discloses all of the claim limitations as set forth above. Qiu additionally discloses that substrate has a textured structure in the edge region, and the passivation layer (40) covers the textured structure and wherein the textured structure includes a tower base structure, a pyramid structure, or a platform raised structure ([116], the entire back surface of the silicon substrate can have a textured structure including the edge region which is covered by the passivation layer 40 and has a pyramid structure).
Regarding claim 7, Qiu discloses all of the claim limitations as set forth above. Qiu additionally discloses that the passivation layer (40) include a first portion abutting the edge region (portion over region 30) and a second portion abutting the surface of the doped semiconductor layer (22) facing away from the dielectric layer (21) (Figure 1).
Regarding claim 8, Qiu discloses all of the claim limitations as set forth above. Qiu additionally discloses that the first electrode penetrates the second portion of the passivation layer (40) in a thickness direction to be in electrical contact with the doped semiconductor layer (22) (Figure 1), and the second electrode penetrates the first portion of the passivation layer to be in electrical contact with the edge region (Figure 1).
Regarding claim 9, Qiu discloses all of the claim limitations as set forth above. Qiu additionally discloses that the dielectric layer (21) is a tunneling dielectric layer having a thickness of 0.5 nm to 5 nm ([93] and [96]).
Regarding claim 10, Qiu discloses all of the claim limitations as set forth above. Qiu additionally discloses an emitter (front doped region), formed over the second surface (front surface) ([134]).
Regarding claim 11, Qiu discloses all of the claim limitations as set forth above. Qiu additionally discloses that the doped semiconductor layer (22) is doped with a doped element of the same type as a doped element of the substrate (10) ([90]-[91]), and a concentration of the doped element of the doped semiconductor layer is greater than a concentration of the concentration of the doped element of the substrate ([99], see N-type substrate and N+ doped region).
Regarding claim 12, Qiu discloses all of the claim limitations as set forth above. Qiu additionally discloses a third electrode including a first portion and a second portion arranged along an arrangement direction of the electrodes; wherein the first portion is formed over the center region, and the second portion is formed over the edge region (Figure 1, the edge region can be defined to include only part of the outer electrodes 50 with part of the outer electrodes being in the center region).
Regarding claim 13, Qiu discloses all of the claim limitations as set forth above. Qiu additionally discloses that the doped semiconductor layer (22) includes at least one of a doped amorphous silicon layer, a doped polycrystalline silicon layer, a doped microcrystalline silicon layer, a doped silicon carbide layer, or a doped crystalline silicon layer ([97]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 5 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Qiu et al. (US 2022/0393044), as applied to claims 1 and 4 above.
Regarding claims 5 and 6, Qiu discloses all of the claim limitations as set forth above. Qiu additionally discloses that a height difference between a top of the textured structure and the center region is in a range of 0.01 μm to 10 μm ([25] and [98]) and the substrate has a recessed depth in the edge region with respect to the center region in a range of 0.01 μm to 10 μm ([25] and [98]). Qiu does not disclose the specifically claimed range of a height difference between a top of the textured structure and the center region is in a range of 1 μm to 14 μm and the substrate has a recessed depth in the edge region with respect to the center region in a range of 1.5 μm to 15 μm; however, in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Claims 14-20 are rejected under 35 U.S.C. 103 as being unpatentable over Qiu et al. (US 2022/0393044) in view of Hayashi et al. (US 2016/0197210).
Regarding claim 14, Qiu discloses a solar cell in Figure 1, comprising:
a substrate (10, [90]), having a first surface (back surface) and a second surface (front surface) opposite to the first surface, the first surface (back surface) including an edge region (region under second conductive regions 30) and a center region (region under first conductive regions 20), the edge region surrounding the center region (Figure 1), and the edge region being substantially flush with, or closer to the second surface than, the center region (As shown in Figure 1, the edge region is closer to the second surface than the center region);
a dielectric layer (first dielectric layer 21), formed on the center region and not on the edge region (Figure 1, [87] and [92]);
a doped semiconductor layer (22), formed over a surface of the dielectric layer (21) facing away from the substrate (10) ([87] and [91]);
a passivation layer (second dielectric layer 40), formed over the edge region and a surface of the doped semiconductor layer (22) facing away from the dielectric layer (21) (Figure 1 and [88]);
a first electrode (middle electrode 50) formed over the center region (region under first conductive region 20) to be in electrical contact with the doped semiconductor layer (22) (Figure 1 and [100]);
a second electrode formed over the edge region to be in electrical contact with the edge region (As shown in Figure 1 and [100], the outer electrodes 50 are in the edge region).
Qiu does not disclose a photovoltaic module, comprising: at least one cell string, each formed by connecting solar cells; an encapsulation glue film, each configured to cover a surface of the at least one cell string; and a cover plate, configured to cover a surface of the encapsulation glue film facing away the at least one cell string.
Hayashi discloses a photovoltaic module in Figure 10, comprising:
at least one cell string (70), each formed by connecting solar cells ([93]);
an encapsulation glue film (sealing layer 42), each configured to cover a surface of the at least one cell string (70) ([93] and [96]); and
a cover plate (40), configured to cover a surface of the encapsulation glue film (42) facing away the at least one cell string (70) ([93] and [95]),
wherein each of the solar cells (Figures 1 and 2) includes:
a substrate (10), having a first surface and a second surface opposite to the first surface, the first surface including an edge region and a center region, the edge region surrounding the center region, and the edge region being substantially flush with, or closer to the second surface than, the center region (entire second surface of the substrate is flush including edge region and center region, Figure 2 and [43]);
a dielectric layer (12i), formed on the center region and not on the edge region (Figures 1-2 and [42]);
a doped semiconductor layer (12n), formed over a surface of the dielectric layer facing away from the substrate ([42]);
a passivation layer (13i), formed over the edge region and a surface of the doped semiconductor layer (12n) facing away from the dielectric layer (12i) ([32]);
the passivation layer (13i) including a first portion adjacent the edge region and a second portion adjacent the surface of the doped semiconductor layer (12n) facing away from the dielectric layer (Figures 1-2, it is noted that the term “adjacent” does not require direct contact or a particular order of the layers. The term “adjacent” merely requires that the components be near or close to each other which is satisfied by layer 13i of Hayashi); and
electrodes (14, 15), including a first plurality of electrodes (14) formed over the center region and penetrating the second portion of the passivation layer (13i) in a thickness direction to be in electrical contact with the doped semiconductor layer (12n) ([51]).
It would have been obvious to one having ordinary skill in the art at the time the invention was filed to add at least one cell string, each formed by connecting solar cells; an encapsulation glue film, each configured to cover a surface of the at least one cell string; and a cover plate, configured to cover a surface of the encapsulation glue film facing away the at least one cell string to form a photovoltaic module with the solar cell of Qiu, as taught by Hayashi, in order to protect the device from damage and increase the output capacity of the device.
Regarding claim 15, modified Qiu discloses all of the claim limitations as set forth above. Qiu additionally discloses that the substrate has a first boundary, and the center region has a second boundary facing the edge region; the first boundary and the second boundary form opposite boundaries of the edge region; and a spacing between the second boundary and the first boundary is less than 300 µm (The term “edge region” is broad and the edge region can be defined to be a distance of less than 300 µm from the outer boundary of the substrate.).
Regarding claims 16 and 17, modified Qiu discloses all of the claim limitations as set forth above. Qiu additionally discloses that substrate has a textured structure in the edge region, and the passivation layer (40) covers the textured structure and wherein the textured structure includes a tower base structure, a pyramid structure, or a platform raised structure ([116], the entire back surface of the silicon substrate can have a textured structure including the edge region which is covered by the passivation layer 40 and has a pyramid structure).
Regarding claims 18 and 19, modified Qiu discloses all of the claim limitations as set forth above. Qiu additionally discloses that a height difference between a top of the textured structure and the center region is in a range of 0.01 μm to 10 μm ([25] and [98]) and the substrate has a recessed depth in the edge region with respect to the center region in a range of 0.01 μm to 10 μm ([25] and [98]). Qiu does not disclose the specifically claimed range of a height difference between a top of the textured structure and the center region is in a range of 1 μm to 14 μm and the substrate has a recessed depth in the edge region with respect to the center region in a range of 1.5 μm to 15 μm; however, in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Regarding claim 20, modified Qiu discloses all of the claim limitations as set forth above. Qiu additionally discloses that the passivation layer (40) include a first portion abutting the edge region (portion over region 30) and a second portion abutting the surface of the doped semiconductor layer (22) facing away from the dielectric layer (21) (Figure 1).
Terminal Disclaimer
The terminal disclaimer filed on 9/01/2025 disclaiming the terminal portion of any patent granted on this application which would extend beyond the expiration date of US Patent No. 12/471,389 granted on application 18/595,876, has been reviewed and is accepted. The terminal disclaimer has been recorded.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LINDSEY A BUCK whose telephone number is (571)270-1234. The examiner can normally be reached Monday-Friday 9am-5:30pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Martin can be reached at (571)270-7871. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LINDSEY A BUCK/Primary Examiner, Art Unit 1728
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