Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The applicant has amended their application as follows:
Amended: 1, 9, 11, 13-15 and 19
Cancelled: 7-8, 12
Added: None
Therefore, claims 1-6, 9-11 and 13-20 are currently pending in the instant application.
Response to Arguments
Applicant's arguments filed 08/05/2026 have been fully considered but they are not persuasive. The office has to respectfully disagree with an argument that Shin does not disclose the limitation “a first voltage switch circuit configured to set a lower reference of a range of an operating voltage of the first sampling capacitor”. Shin discloses a switch (SW1; Fig. 4) that transmits a reference voltage Vr1. The reference voltage Vr1 is interpreted to read on limitation “a lower reference of a range of an operating voltage of the first sampling capacitor”. Furthermore, the voltage difference between Vi and Vr1 is stored in the sampling capacitor Cs1. Therefore, the voltage difference between Vi and Vr1 has to be equal or less than the operating voltage range of the capacitor to function properly. Hence, the claim 11 is rejected under 102(a)(2).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 11-16 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Shin et al. (US 2025/0061854 A1, hereinafter “Shin”).
As to claim 11, Shin (Fig. 1) discloses a sensing circuit (22) configured to sense information received from a display panel (50) and generate sensing data corresponding thereto (Para. 0029), the sensing circuit comprising:
a sample and hold circuit (Fig. 4) comprising a sampling capacitor (Cs1), the sample and hold circuit being configured to:
generate a first voltage difference (ΔV) between a sensing voltage (Vi) and an initial reference voltage (Vr1) by sampling the sensing voltage (Vi) and the initial reference voltage (Vr1; Para. 0045), and
maintain the first voltage difference as a constant (Para. 0045); and
an amplifying circuit (223) configured to amplify the first voltage difference to generate an output voltage (V0; Para. 0046), wherein the sampling capacitor comprises:
a first sampling capacitor (Cs1) configured to sample the sensing voltage (Vi); and
a second sampling capacitor (Cs2) configured to sample the initial reference voltage (Vr1),
a first voltage switch circuit (SW1) configured to set a lower reference of a range of an operating voltage of the first sampling capacitor (Vr1; Para. 0045, since the sampling voltage is difference between the reference voltage Vr1 and the input voltage Vi, the reference voltage Vr1 is interpreted to be a lower reference of a range of an operating voltage of the first sampling capacitor),
wherein the range of the operating voltage of the first sampling capacitor is equal to or less than a second voltage difference (Vi-Vr1) between a first voltage level (Vi) corresponding to the sensing voltage and a second voltage level corresponding to the initial reference voltage (Vr1; Para. 0045, 0051, the operating range first sampling capacitor has to be equal or less than Vi-Vr1 for it to work).
As to claim 13, Shin (Fig. 4) discloses the sensing circuit of claim 12, wherein the first voltage switch circuit is configured to set the lower reference to the initial reference voltage (Vr1).
As to claim 14, Shin (Fig. 4) discloses the sensing circuit of claim 12, wherein the sample and hold circuit comprises a second voltage switch circuit (SW3) configured to level-shift a voltage (Vr2) applied to one end of the first sampling capacitor (Cs1) and one end of the second sampling capacitor (CS2) while maintaining the range of the operating voltage of the first sampling capacitor (Para. 0045).
As to claim 15, Shin (Fig. 4) discloses the sensing circuit of claim 14, wherein the first voltage switch circuit comprises a first voltage-setting switch (SW1) and a second voltage-setting switch (SW2b) that are configured to set one end of the first sampling capacitor (Cs1) and one end of the second sampling capacitor (Cs2) to a first level (Vr1) upon turn-on of a first voltage-setting signal (SC1, SC2; Fig. 5),
wherein the second voltage switch circuit comprises a third voltage-setting switch (Fig. 4 element SW2a) and a fourth voltage-setting switch (SW3) that are configured to set the one end of the first sampling capacitor (Cs1) and the one end of the second sampling capacitor (Cs2) to a second level (Vr2) lower than the first level (Vr1; Para. 0045) upon turn-on of a second voltage-setting signal (SC2, SC3).
As to claim 16, Shin (Fig. 4) discloses the sensing circuit of claim 14, wherein the sample and hold circuit comprises one or more bias transistors (SW4a, SW4b) configured to control electrical connection between the first voltage switch circuit (SW1, SW2b) and the second voltage switch circuit (SW2a, SW3).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Shin as applied to claim 11 above, and further in view of Lee et al. (US 2021/0043148 A1, hereinafter “Lee”).
As to claim 17, Shin does not disclose the sensing circuit of claim 11, wherein the sample and hold circuit comprises a reset circuit configured to reset voltages at first and second ends of the first sampling capacitor and the second sampling capacitor.
However, Lee (Fig. 11) teaches wherein the sample and hold circuit comprises a reset circuit (SW_RST) configured to reset voltages at first and second ends of the first sampling capacitor (Cs1) and the second sampling capacitor (Cs2; Para. 0073; Fig. 12, SW_SP1 And SW_RST are turned on from t1-t4).
It would have been obvious to one of ordinary skill in the art to combine the teaching of Lee’148 to include a reset circuit in the device disclosed by Shin. The motivation would have been to supply reset voltage to the capacitors.
As to claim 18, Shin discloses the sensing circuit of claim 17. Lee’148 further teaches wherein the reset circuit comprises a first reset switch (upper reset switch) and a second reset switch (lower reset switch) that are configured to reset voltages at the first and second ends of the first sampling capacitor and the second sampling capacitor upon turn-on of a reset signal (SW_RST; Para. 0080).
Allowable Subject Matter
Claims 1-6, 9-10 and 19-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
With respect to independent claims 1 and 19, The prior art, alone or in an obvious combination, does not disclose the limitations “a first voltage switch circuit configured to set a voltage applied to a first end of the first sampling capacitor and a first end of the second sampling capacitor to a first level, wherein the first level is the voltage level of the initial reference voltage” when combined with other limitations.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant‘s disclosure.
Hwang (US 10,290,263 B2) discloses two sampling capacitors (Fig. 6).
Huang (US 2011/0140939 A1) discloses reset switches parallel to sampling capacitors (Fig. 8 elements SW4, SW5).
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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BIPIN GYAWALI
Primary Examiner
Art Unit 2625
/BIPIN GYAWALI/Primary Examiner, Art Unit 2625
