Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claims 2-8, and 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 9 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al., US 20240290266 A1 (hereinafter “Park”) in view of Lee US 20210312848 A1 (hereinafter “Lee”), and Liu et al., US 20120075280 A1 (hereinafter “Liu”).
Regarding claim 1, Park discloses a display device (fig. 1, display device 100), comprising:
a display panel including a plurality of subpixels (fig. 1, paragraph 49, display panel 110 with plurality of subpixels SP);
a gate driving circuit configured to supply a gate signal to the display panel (fig. 1, paragraph 50, gate driving circuit 130); and
a power management integrated circuit (fig. 5) including:
a first boost converter configured to convert the input voltage into a power voltage to be supplied to the display panel (fig. 5, paragraphs 95-105, first boost converter 510 convert input voltage Vin to source voltage SVDD to be supplied to display panel);
a second boost converter configured to convert the power voltage into a gate high voltage to be supplied to the gate driving circuit (fig. 5, paragraphs 95-105, second boost converter 520 convert power voltage into gate high voltage VGH, “The power supply device 500 may output the gate high voltage VGH based on the input voltage Vin. The input voltage Vin may be supplied to the first boost converter 510 and then to the second boost converter 520. The voltage output from the second boost converter 520 may be the gate high voltage VGH”).
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Park does not disclose in particular:
a selection signal generating circuit configured to compare an input voltage with a first reference voltage and to output a selection signal;
In similar field of endeavor, Lee discloses a power manage circuit which manage input and output voltage of display device (see abstract), wherein a selection signal is generated by circuit configured to compare an input voltage with first reference voltage and to output a selection signal, and output voltage signal supplied to display device is adjusted accordingly (fig. 1, fig. 3, paragraphs 68-74, claim 1, “wherein the regulator control block compares the input voltage with a reference input voltage, and wherein when the input voltage is higher than or equal to the reference input voltage, the regulator control block increases the reference boosting voltage to increase the boosted voltage, enables the voltage regulator to generate a regulated voltage by regulating the increased boosted voltage, turns off the bypass transistor such that the regulated voltage is output as the pixel power supply voltage at the output node, and maintains an enable state of the voltage regulator for a minimum enable time.”)
It would have been obvious to one of ordinary skill in the art at the time of filing to incorporate the concept of monitor input voltage to generate selection by comparing input voltage with reference voltage, such as disclosed by Lee into the display device of Park, to constitute a selection signal generating circuit configured to compare an input voltage with a first reference voltage and to output a selection signal, in order to achieve the predictable result of allowing input voltage to be monitor and output voltage of display device dynamically adjusted based on input voltage.
Park in view of Lee does not disclose in particular a multiplexer configured to select a trigger signal based on the selection signal; and wherein the gate high voltage is supplied to gate driving circuit based on the selected trigger signal.
In similar field of endeavor, Liu discloses a multiplexer configured to select a trigger signal based on the selection signal; and wherein the gate high voltage is supplied to gate driving circuit based on the selected trigger signal (see Liu, paragraphs 29-33, multiplexer 555 configured to select trigger signal supplied to second boost converter 543 based on selection signal Ref_SEL in order to dynamically select supply of gate high voltage / gate low voltage Vgh1 / Vgh1 to gate driver 530).
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It would have been obvious to one of ordinary skill in the art at the time of filing to incorporate the known concept of multiplex selecting trigger signal to change supply of gate driver voltage to gate driver based on selection signal, such as disclosed by Liu, into the known display device to Park in view of Lee, to constitute a multiplexer configured to select a trigger signal based on the selection signal; and wherein the gate high voltage is supplied to gate driving circuit based on the selected trigger signal, in order to achieve the predictable result of allowing dynamic selection of gate high / gate low activation signal to gate driver, to achieve the intended of function of scanning gate lines to enable display operation.
Regarding claim 9, Park in view of Lee and Liu discloses the display device of claim 1, wherein the power voltage has a high level than the input voltage, and the gate high voltage has a higher level than the power voltage (see Park, paragraph 95-105, input voltage is boosted in sequence by first boost converter and second booster converter, with each stage being boosted, i.e. being higher than previous stage).
Regarding claim 11, this is power manage integrate circuit counterpart of display device claim 1 comprising the power manage integrated circuit, both reciting similar subject matter. Therefore claim 11 is rejected for the same reason as claim 1.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PEIJIE SHEN whose telephone number is (571)272-5522. The examiner can normally be reached Monday - Friday 10AM - 6PM.
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/PEIJIE SHEN/Examiner, Art Unit 2622
/PATRICK N EDOUARD/Supervisory Patent Examiner, Art Unit 2622
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