DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-5, 10-14 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Teodorescu et al. [US 2016/0335182 A1] in view of Dean et al. [US 2018/0210933 A1].
Claim 1 is rejected over Teodorescu and Dean.
Teodorescu teaches “A system for providing a first memory group, the system comprising:” as “ In some such embodiments, column data of a column (i.e., different rows or groups of rows) can also be stored in different memory devices and/or data servers.” [¶0058]
“a first memory device associated with a first host, the first memory device comprising:” as “the system 100 includes an application host 102, a periodic data import host 104, a query server host 106, a long-term file server 108, and a user data import host 110. ” [¶0039]
“a first memory, at least a first portion of the first memory being a first shared memory that is configured to receive a first transaction request associated with a first data operation, the first transaction request from outside of the first host;” as “The TDCP-enabled server computer can comprise a cache memory device having at least a portion being a shared memory portion.” [¶0005]
Teodorescu does not explicitly teach a first local-memory manager configured to manage the first shared memory; and
a first access gateway of the first memory device, the first access gateway configured to determine, based on a first data structure of the first memory device, to route the first transaction request to the first shared memory.
However, Dean teaches “a first local-memory manager configured to manage the first shared memory; and” as “For data to he located in shared memory 312, operation optimization mechanism 302 determines whether a portion of data in local memory 310 is being utilized by multiple one of processors 304 each running at least one application,” [¶0050]
“a first access gateway of the first memory device, the first access gateway configured to determine, based on a first data structure of the first memory device, to route the first transaction request to the first shared memory.” as “For data to he located in shared memory 312, operation optimization mechanism 302 determines whether a portion of data in local memory 310 is being utilized by multiple one of processors 304 each running at least one application,” [¶0050]
Teodorescu and Dean are analogous arts because they teach local and shared memory and storage system management.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Teodorescu and Dean before him/her, to modify the teachings of Teodorescu to include the teachings of Dean with the motivation of efficient data retrieval in big-data processing systems. [Dean, ¶0001]
Claim 2 is rejected over Teodorescu and Dean.
Teodorescu teaches “wherein the first data structure comprises a memory routing table comprising shared-memory location information indicating a first location within the first shared memory corresponding to the first transaction request.” as “ Although references have been made herein to tables and table data, it will be appreciated that the disclosed systems and methods can be applied with various computer data objects to, for example, provide flexible data routing and caching for such objects in accordance with the disclosed subject matter.” [¶0133]
Claim 3 is rejected over Teodorescu and Dean.
Teodorescu does not explicitly teach wherein the first local-memory manager manages the first shared memory by:
dividing the first memory to generate the first shared memory; and
generating first shared-memory information indicating one or more performance attributes of the first shared memory.
However, Dean teaches “wherein the first local-memory manager manages the first shared memory by:” as “the operation optimization mechanism moves the portion of data from the local memory to a shared memory, the shared memory being accessible by the multiple processing systems. Thus, the operation optimization mechanism is then able to redirect accesses to the portion of data to the shared memory.” [¶0021]
“dividing the first memory to generate the first shared memory; and” as “For data to be located in global memory 314, operation optimization mechanism 302 determines whether a portion of data in local memory 310 or shared memory 312 is being utilized across processors 304 each running at least one application,” [¶0054]
“generating first shared-memory information indicating one or more performance attributes of the first shared memory.” as “ any functionality attributed to an engine may be equally performed by multiple engines, incorporated into and/or combined with the functionality of another engine of the same or different type, or distributed across one or more engines of various configurations.” [¶0027]
Claim 4 is rejected over Teodorescu and Dean.
Teodorescu does not explicitly teach a global manager communicatively connected to the first access gateway and to a second access gateway of a second memory device associated with a second host, wherein the global manager is configured to create the first memory group comprising the first shared memory and a second shared memory of the second memory device.
However, Dean teaches “a global manager communicatively connected to the first access gateway and to a second access gateway of a second memory device associated with a second host, wherein the global manager is configured to create the first memory group comprising the first shared memory and a second shared memory of the second memory device.” as “the operation optimization mechanism may determine whether a portion of data in the local memory is being utilized by more than one application. If the operation optimization mechanism determines that the portion of data in the local memory is being utilized by more than one application, the operation optimization mechanism marks the portion of data such that the portion of data is persisted within the local memory for a longer time than unmarked portions of data.” [¶0018]
Claim 5 is rejected over Teodorescu and Dean.
Teodorescu does not explicitly teach wherein a global manager is configured to create the first memory group based on one or more performance attributes of the first shared memory or based on one or more performance attributes of a second shared memory.
However, Dean teaches “wherein a global manager is configured to create the first memory group based on one or more performance attributes of the first shared memory or based on one or more performance attributes of a second shared memory.” as “any functionality attributed to an engine may be equally performed by multiple engines, incorporated into and/or combined with the functionality of another engine of the same or different type, or distributed across one or more engines of various configurations.” [¶0027]
Claim 10 is rejected over Teodorescu and Dean under the same rationale of rejection of claim 1.
Claim 11 is rejected over Teodorescu and Dean under the same rationale of rejection of claim 2.
Claim 12 is rejected over Teodorescu and Dean under the same rationale of rejection of claim 3.
Claim 13 is rejected over Teodorescu and Dean under the same rationale of rejection of claim 4.
Claim 14 is rejected over Teodorescu and Dean under the same rationale of rejection of claim 5.
Claim 19 is rejected over Teodorescu and Dean under the same rationale of rejection of claim 1.
Claim(s) 7-9 and 16-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Teodorescu et al. [US 2016/0335182 A1] in view of Dean et al. [US 2018/0210933 A1] and in further view of Appu et al. [US 2018/0300074 A1].
Claim 7 is rejected over Teodorescu, Dean and Appu.
The combination of Teodorescu and Dean does not explicitly teach wherein the first transaction request is configured to operate using an interconnect protocol.
However, Appu teaches “wherein the first transaction request is configured to operate using an interconnect protocol.” as “Various interconnect protocols may be used including, but not limited to, PCIe 4.0 or 5.0 and NVLink 2.0. ” [¶0073]
Teodorescu, Dean and Appu are analogous arts because they teach local and shared memory and storage system management.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Teodorescu, Dean and Appu before him/her, to modify the teachings of combination of Teodorescu and Dean to include the teachings of Appu with the motivation of allowing partition units to write portions of each render target in parallel to efficiently use the available bandwidth of parallel processor memory. [Appu, ¶0049]
Claim 8 is rejected over Teodorescu, Dean and Appu.
The combination of Teodorescu and Dean does not explicitly teach wherein the first access gateway comprises: a first port configured to receive the first transaction request; and a second port configured to receive a second transaction request.
However, Appu teaches “wherein the first access gateway comprises: a first port configured to receive the first transaction request; and a second port configured to receive a second transaction request.” as “Each bank 18 can be accessed by a read port 22 and a write port 24. Multi-ported read may also be used in some embodiments.” [¶0132]
Teodorescu, Dean and Appu are analogous arts because they teach local and shared memory and storage system management.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Teodorescu, Dean and Appu before him/her, to modify the teachings of combination of Teodorescu and Dean to include the teachings of Appu with the motivation of allowing partition units to write portions of each render target in parallel to efficiently use the available bandwidth of parallel processor memory. [Appu, ¶0049]
Claim 9 is rejected over Teodorescu, Dean and Appu.
The combination of Teodorescu and Dean does not explicitly teach wherein the first port is configured to receive a first participation request to provide the first shared memory to the first memory group.
However, Appu teaches “wherein the first port is configured to receive a first participation request to provide the first shared memory to the first memory group.” as “Each bank 18 can be accessed by a read port 22 and a write port 24.” [¶0132]
Claim 16 is rejected over Teodorescu, Dean and Appu under the same rationale of rejection of claim 7.
Claim 17 is rejected over Teodorescu, Dean and Appu under the same rationale of rejection of claim 8.
Claim 18 is rejected over Teodorescu, Dean and Appu under the same rationale of rejection of claim 9.
Allowable Subject Matter
Claims 6, 15 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The prior art of record, including Teodorescu et al. (US 2016/0335182 A1), Dean et al. (US 2018/0210933 A1), and Appu et al. (US 2018/0300074 A1), either individually or in combination, fails to teach or fairly suggest the claimed memory management arrangement.
In particular, the prior art does not teach or suggest a first local-memory manager configured to determine one or more performance attributes of both (i) a first shared memory and (ii) a second shared memory of a second memory device of a second host, and to store the performance attributes of both shared memories in a second data structure on the first memory device, as presently claimed.
Although Teodorescu et al., Dean et al., and Appu et al. generally disclose techniques relating to memory management, shared or distributed memory resources, and/or monitoring or characterization of memory or system resources, the cited references do not disclose the claimed combination in which a local-memory manager associated with a first memory device obtains performance information not only for its associated first shared memory, but also for a shared memory located on a different memory device associated with a second host, and locally maintains the performance attributes of both memories in a data structure on the first memory device.
Thus, the claimed arrangement provides the first local-memory manager with locally maintained performance information concerning shared-memory resources spanning different hosts. The cited prior art does not disclose or provide sufficient teaching or suggestion for modifying its respective memory-management arrangements to arrive at this particular cross-host performance-attribute determination and local storage configuration. Accordingly, the claimed subject matter, considered as a whole, is not taught or rendered obvious by Teodorescu et al., Dean et al., and Appu et al., either alone or in combination.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MASUD K KHAN whose telephone number is (571)270-0606. The examiner can normally be reached Monday-Friday (8am-5pm).
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/MASUD K KHAN/ Primary Examiner, Art Unit 2132
