CTNF 19/308,363 CTNF 85750 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Double Patenting 08-33 AIA The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA/25, or PTO/AIA/26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. 08-34 AIA Claim s 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim s 1-20 of U.S. Patent No. 12,437,697 . Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the present application represent an obvious variation of the patented claims . Present Application U.S. Patent No. 12,437, 697 1 . A pixel drive circuit, comprising: a plurality of scan drive circuits cascaded in a pixel column direction, wherein the plurality of scan drive circuits are coupled to a plurality of rows of pixels via a plurality of gate lines; and each of the scan drive circuits is further coupled to a scan drive line and is configured to transmit a gate drive signal to a gate line coupled to the scan drive circuit based on a drive signal provided by the scan drive line; a plurality of emission drive circuits cascaded in the pixel column direction, wherein the plurality of emission drive circuits are coupled to the plurality of rows of pixels via a plurality of emission control lines; and each of the emission drive circuits is further coupled to an emission drive line and is configured to transmit an emission control signal to an emission control line coupled to the emission drive circuit based on a drive signal provided by the emission drive line; a plurality of compensation drive circuits cascaded in the pixel column direction, wherein the plurality of compensation drive circuits are coupled to the plurality of rows of pixels via a plurality of compensation lines; and each of the compensation drive circuits is further coupled to a compensation drive line and is configured to transmit a compensation signal to a compensation line coupled to the compensation drive circuit based on a drive signal provided by the compensation drive line; and a plurality of reset drive circuits cascaded in the pixel column direction, wherein the plurality of reset drive circuits are coupled to the plurality of rows of pixels via a plurality of reset lines; and each of the reset drive circuits is further coupled to a reset drive line and is configured to transmit a reset signal to a reset line coupled to the reset drive circuit based on a drive signal provided by the reset drive line; wherein a scan drive circuit, a emission drive circuit, a compensation drive circuit, and a reset drive circuit that are coupled to a same row of pixels are arranged in a pixel row direction, in the pixel row direction, a length of the scan drive circuit is greater than a length of the emission drive circuit and greater than a length of the compensation drive circuit, and the length of the compensation drive circuit is greater than the length of the emission drive circuit. 1. A pixel drive circuit, comprising: a plurality of scan drive circuits cascaded in a pixel column direction, wherein the plurality of scan drive circuits are coupled to a plurality of rows of pixels via a plurality of gate lines; and each of the scan drive circuits is further coupled to a scan drive line and is configured to transmit a gate drive signal to a gate line coupled to the scan drive circuit based on a drive signal provided by the scan drive line; a plurality of emission drive circuits cascaded in the pixel column direction, wherein the plurality of emission drive circuits are coupled to the plurality of rows of pixels via a plurality of emission control lines; and each of the emission drive circuits is further coupled to an emission drive line and is configured to transmit an emission control signal to an emission control line coupled to the emission drive circuit based on a drive signal provided by the emission drive line; a plurality of compensation drive circuits cascaded in the pixel column direction, wherein the plurality of compensation drive circuits are coupled to the plurality of rows of pixels via a plurality of compensation lines; and each of the compensation drive circuits is further coupled to a compensation drive line and is configured to transmit a compensation signal to a compensation line coupled to the compensation drive circuit based on a drive signal provided by the compensation drive line; and a plurality of reset drive circuits cascaded in the pixel column direction, wherein the plurality of reset drive circuits are coupled to the plurality of rows of pixels via a plurality of reset lines; and each of the reset drive circuits is further coupled to a reset drive line and is configured to transmit a reset signal to a reset line coupled to the reset drive circuit based on a drive signal provided by the reset drive line; wherein a scan drive circuit, a emission drive circuit, a compensation drive circuit, and a reset drive circuit that are coupled to a same row of pixels are arranged sequentially in a pixel row direction, and the scan drive circuit is disposed on a side distal to the pixels; and among signal lines as coupled in the pixel drive circuit, a plurality of the signal lines is overlapped with each other, and cutouts are provided at overlapping portions of the plurality of signal lines. 19 . A display apparatus, comprising: a plurality of pixels, and a pixel drive circuit; wherein the pixel drive circuit is coupled to the plurality of pixels and is configured to drive emission of the plurality of pixels; and the pixel drive circuit comprises: a plurality of scan drive circuits cascaded in a pixel column direction, wherein the plurality of scan drive circuits are coupled to a plurality of rows of pixels via a plurality of gate lines; and each of the scan drive circuits is further coupled to a scan drive line and is configured to transmit a gate drive signal to a gate line coupled to the scan drive circuit based on a drive signal provided by the scan drive line; a plurality of emission drive circuits cascaded in the pixel column direction, wherein the plurality of emission drive circuits are coupled to the plurality of rows of pixels via a plurality of emission control lines; and each of the emission drive circuits is further coupled to an emission drive line and is configured to transmit an emission control signal to an emission control line coupled to the emission drive circuit based on a drive signal provided by the emission drive line; a plurality of compensation drive circuits cascaded in the pixel column direction, wherein the plurality of compensation drive circuits are coupled to the plurality of rows of pixels via a plurality of compensation lines; and each of the compensation drive circuits is further coupled to a compensation drive line and is configured to transmit a compensation signal to a compensation line coupled to the compensation drive circuit based on a drive signal provided by the compensation drive line; and a plurality of reset drive circuits cascaded in the pixel column direction, wherein the plurality of reset drive circuits are coupled to the plurality of rows of pixels via a plurality of reset lines; and each of the reset drive circuits is further coupled to a reset drive line and is configured to transmit a reset signal to a reset line coupled to the reset drive circuit based on a drive signal provided by the reset drive line; wherein a scan drive circuit, a emission drive circuit, a compensation drive circuit, and a reset drive circuit that are coupled to a same row of pixels are arranged in a pixel row direction, in the pixel row direction, a length of the scan drive circuit is greater than a length of the emission drive circuit and greater than a length of the compensation drive circuit, and the length of the compensation drive circuit is greater than the length of the emission drive circuit. 19. A display apparatus, comprising: a plurality of pixels, and a pixel drive circuit; wherein the pixel drive circuit is coupled to the plurality of pixels and is configured to drive emission of the plurality of pixels; and the pixel drive circuit comprises: a plurality of scan drive circuits cascaded in a pixel column direction, wherein the plurality of scan drive circuits are coupled to a plurality of rows of pixels via a plurality of gate lines; and each of the scan drive circuits is further coupled to a scan drive line and is configured to transmit a gate drive signal to a gate line coupled to the scan drive circuit based on a drive signal provided by the scan drive line; a plurality of emission drive circuits cascaded in the pixel column direction, wherein the plurality of emission drive circuits are coupled to the plurality of rows of pixels via a plurality of emission control lines; and each of the emission drive circuits is further coupled to an emission drive line and is configured to transmit an emission control signal to an emission control line coupled to the emission drive circuit based on a drive signal provided by the emission drive line: a plurality of compensation drive circuits cascaded in the pixel column direction, wherein the plurality of compensation drive circuits are coupled to the plurality of rows of pixels via a plurality of compensation lines; and each of the compensation drive circuits is further coupled to a compensation drive line and is configured to transmit a compensation signal to a compensation line coupled to the compensation drive circuit based on a drive signal provided by the compensation drive line; and a plurality of reset drive circuits cascaded in the pixel column direction, wherein the plurality of reset drive circuits are coupled to the plurality of rows of pixels via a plurality of reset lines; and each of the reset drive circuits is further coupled to a reset drive line and is configured to transmit a reset signal to a reset line coupled to the reset drive circuit based on a drive signal provided by the reset drive line: wherein a scan drive circuit, a emission drive circuit, a compensation drive circuit, and a reset drive circuit that are coupled to a same row of pixels are arranged sequentially in a pixel row direction, and the scan drive circuit is disposed on a side distal to the pixels; and among signal lines as coupled in the pixel drive circuit, a plurality of the signal lines is overlapped with each other, and cutouts are provided at overlapping portions of the plurality of signal lines. Claims 2-18 and 20 of the present application are mapped to claims 2-18 and 20 of the U.S. Patent, respectively. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHAYCE R BIBBEE whose telephone number is (571)270-7222. The examiner can normally be reached Mon-Thurs 8:00-6:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Eason can be reached at 571-270-7230. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CHAYCE R BIBBEE/Examiner, Art Unit 2624 Application/Control Number: 19/308,363 Page 2 Art Unit: 2624 Application/Control Number: 19/308,363 Page 3 Art Unit: 2624
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