DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1 – 20 are pending.
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in Republic of Korea on 03 December 2024. It is noted, however, that applicant has not filed a certified copy of the 10-2024-0177529 application as required by 37 CFR 1.55. Therefore, this Application is not entitled to the foreign priority.
Claim Objections
Claim 7 is objected to because of the following informalities. Appropriate correction is required.
Claim 7 should be amended to “wherein a number of logical addresses, corresponding to one bit of the bitmap, corresponds to a ratio between the second capacity and the first capacity”. This is so that it is clear what (number of LAs or bitmap) corresponds to a ratio between the second capacity and the first capacity.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 2 and 16 – 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Song (US 20180293174).
Regarding claim 1, Song teaches
A storage controller (storage controller = Fig. 2 controller 110) for controlling a non-volatile memory device (non-volatile memory device = Fig. 2 non-volatile memory 104), the storage controller comprising:
a memory storing one or more instructions; and
at least one processor configured to individually or collectively execute the one or more instructions, wherein the one or more instructions, when executed by the at least one processor, cause the storage controller to: (Song teaches controller 110 comprising FEP 110 (see Fig. 2, ¶[49]) that includes memory processor (at least one processor) that uses (storing) SRAM 160 (memory) to perform (execute) various memory operations (one or more instructions) (see Fig. 3, ¶[50]).)
based on a request received from a host indicating a sequential operation, identify a type of a mapping entry between a logical address included in the request and a physical address of the non-volatile memory device; (Song teaches receiving, from host (host), compiled code (request), with instructions, including a logical address (logical address) for target data, and an indication of whether said target data is sequentially accessed data (sequential operation) (see Fig. 25, ¶[110]) wherein when (based on) said indication is sequentially accessed data, accessing (identifying) L2P entry (mapping entry) in a coarse (type) L2P table, and using said L2P entry to translate said logical address to physical address (physical address) in non-volatile memory (see Fig. 25, ¶[115]). Song also teaches said L2P entry of said coarse L2P table maps (mapping) said logical address to said physical address (see ¶[99], also Fig. 27).)
manage a first mapping table comprising one or more mapping entries of a first type; and
manage a second mapping table comprising one or more mapping entries of a second type,
wherein the one or more mapping entries of the first type correspond to data of a first capacity, and
wherein the one or more mapping entries of the second type correspond to data of a second capacity (Song teaches i) fine (first type) L2P table (first mapping table) with fine entries (one or more mapping entries of first type) for each page (first capacity) of data (data), and ii) said coarse (second type) L2P table (second mapping table) with coarse entries (one or more mapping entries of second type) for each block (second capacity) of data (data) (see ¶[99]) wherein said fine L2P table and said coarse L2P table are maintained (manage) by controller (see Fig. 23 and corresponding paragraphs).)
Regarding claim 2, Song teaches the storage controller of claim 1 where Song also teaches
wherein the second capacity is greater than the first capacity (Song teaches plural of said page (first capacity) are combined to form a block (second capacity) (see Fig. 21 and corresponding paragraphs). Note that said block is greater than said page.)
Regarding claim 16, Song teaches
A storage device (storage device = Fig. 2 solid state drive 100) comprising:
a non-volatile memory device (non-volatile memory device = Fig. 2 non-volatile memory 104) configured to store data (Song teaches configuring non-volatile memory with second portion to store random data (data) (see Fig. 22, ¶[99]).)
a storage controller (storage controller = Fig. 2 controller 110) configured to control the non-volatile memory device, the storage controller comprising:
a memory storing one or more instructions; and
at least one processor configured to individually or collectively execute the one or more instructions, wherein the one or more instructions, when executed by the at least one processor, cause the storage controller to: (Song teaches controller 110 comprising FEP 110 (see Fig. 2, ¶[49]) that includes memory processor (at least one processor) that uses (storing) SRAM 160 (memory) to perform (execute) various memory operations (one or more instructions) (see Fig. 3, ¶[50]).)
receive a request and one or more logical addresses from a host
identify, based on the request, a type of a mapping entry between the one or more logical addresses and a physical address of the non-volatile memory device, (Song teaches receiving, from host (host), compiled code (request), with instructions, including a logical address (one or more logical addresses) for target data, and an indication of whether said target data is sequentially accessed data or randomly accessed data (see Fig. 25, ¶[110]) wherein i) when (based on) said indication is sequentially accessed data, accessing (identify) coarse L2P entry (mapping entry) in a coarse (second type) L2P table, and using said L2P entry to translate said logical address to physical address (physical address) in said non-volatile memory (see Fig. 25, ¶[115]), and ii) when said indication is randomly accessed data, accessing (identify) fine L2P entry (mapping entry) in a fine (first type) L2P table, and using said L2P entry to translate said logical address to physical address (physical address) in said non-volatile memory (see Fig. 25, ¶[113]).)
wherein the mapping entry comprises a first type mapping entry corresponding to data of a first capacity and a second type mapping entry corresponding to data of a second capacity (Song teaches i) said fine L2P entry (mapping entry, first type mapping entry), in said fine (first type) L2P table, is for each page (first capacity) of data (data), and ii) said coarse L2P entry (mapping entry, second type mapping entry), in said coarse (second type) L2P table, is for each block (second capacity) of data (data) (see ¶[99]).)
Regarding claim 17, Song teaches the storage device of claim 16 where Song also teaches
manage a plurality of mapping tables (plurality of mapping tables = fine L2P table + coarse L2P table), and
wherein the plurality of mapping tables comprises:
a first mapping table comprising the first type mapping entry; and
a second mapping table comprising the second type mapping entry (Song teaches i) fine L2P entry (first type mapping entry), in fine (first type) L2P table (first mapping table), is for each page (first capacity) of data (data), and ii) coarse L2P entry (second type mapping entry), in said coarse (second type) L2P table (second mapping table0, is for each block (second capacity) of data (data) (see ¶[99]). Song also teaches said fine L2P table and said coarse L2P table are maintained (manage) by controller (see Fig. 23 and corresponding paragraphs).)
Regarding claim 18, Song teaches the storage device of claim 16 where Song also teaches
wherein the first capacity is smaller than the second capacity, and (Song teaches plural of said page (first capacity) are combined to form a block (second capacity) (see Fig. 21 and corresponding paragraphs). Note that said block is greater than said page.)
wherein the one or more instructions, when executed by the at least one processor, further cause the storage controller to, based on the request indicating a sequential operation, generate the second type mapping entry of the one or more logical addresses (Song teaches receiving, from host (host), compiled code (request), with instructions, including a logical address (one or more logical address) for target data, and an indication of whether said target data is sequentially accessed data or randomly accessed data (see Fig. 25, ¶[110]) wherein when (based on) said indication is sequentially accessed data (sequential operation), accessing coarse L2P entry (second type mapping entry) in a coarse (second type) L2P table, and using said L2P entry to translate said logical address to physical address (physical address) in said non-volatile memory wherein said coarse L2P entry is fetched (generate) into cache (see Fig. 25, ¶[115].)
Regarding claim 19, Song teaches the storage device of claim 17 where Song also teaches
wherein a number of the first type mapping entry is less than a threshold value (Song teaches i) fine L2P tables with said fine entry (first type mapping entry) for each page of data and ii) coarse L2P table with said coarse entry for each block of data (see Fig. 23 and corresponding paragraphs). In exemplary embodiment, there are 8 (number) of said fine entry (first type mapping entry) per physical block (see Fig. 26). Note that, in Fig. 26, 8 fine entries per block is less than total of 16 fine entries (threshold value) of 2 blocks.)
Regarding claim 20, Song teaches the storage device of claim 17 where Song also teaches
wherein the one or more instructions, when executed by the at least one processor, further cause the storage controller to load the first mapping table (Song teaches fetching (load), into cache, i) fine L2P table (first mapping table) (see Fig. 25, ¶[113]), and ii) coarse L2P table (see Fig. 25, ¶[115]).)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Song in view of Fukutomi (US 20220156182).
Regarding claim 3, Song teaches the storage controller of claim 2.
As noted in claim 2, Song teaches a base storage controller where a block (second capacity) is formed from plural of a page (first capacity). The claimed invention improves upon said base storage controller where a ratio between said first capacity and said second capacity is a power of 2.
This improvement to said base storage controller is an application of known technique from Fukutomi – block size is 512KB and page size is 4KB. In particular, Fukutomi teaches a block constructed from plural pages where said block is 512KB and said pages, each is 4KB (see Fukutomi ¶[4-5]). Note that ratio of 4KB/512KB is 2^3/2^9 (which is power of 2).
One of ordinary skill in the art would recognize that this known technique of configuring block size to 512KB from multiple page of 4B can also be applied to configure Song’s block and page, and the result would have been predictable. In this instance, said block is 512KB and said page (plural of which used to form said block) is 4KB. It would have been obvious to one of ordinary skill in the art at the time of filing to recognize that applying Fukutomi’s known technique would have yielded i) predictable result of said block (second capacity) is 512KB and said page (first capacity) (plural of which used to form said block) is 4KB, ratio of which is 2^3/2^9 (which is power of two), and ii) the improved claimed invention (see MPEP 2143(I)(D)).
Claims 5 – 15 are rejected under 35 U.S.C. 103 as being unpatentable over Song in view of Jang (US 20160378359).
Regarding claim 5, Song teaches the storage controller of claim 1.
As noted in claim 1, Song teaches a base storage controller that manages first and second mapping tables with mapping entries. The claimed invention improves upon said base storage controller by using a bitmap to indicate mapping type of one or more corresponding logical addresses of said mapping entries (see also limitation below).
manage a bitmap corresponding to one or more logical addresses, wherein the bitmap indicates a mapping type of the one or more corresponding logical addresses
This improvement to said base method is an application of known technique from Jang – using tag to indicate whether a logical address and physical address mapping is sequential or not. In particular, Jang teaches
manage a bitmap corresponding to one or more logical addresses, wherein the bitmap indicates a mapping type of the one or more corresponding logical addresses (Jang teaches plural entries, each entry include i) a LBA (one or more logical addresses) and PBA pair (mapping), and ii) TAG_L1 and TAG_L2 indicating whether said entry has sequential data or not (mapping type) (see Fig. 4, Fig. 7 and corresponding paragraphs). Note that all the TAG_L1 and TAG_L2 are a set (bitmap).)
One of ordinary skill in the art would recognize that this known technique of using tags to indicate whether LBA/PBA pair has sequential data or not can also be used to indicate whether Song’s mapping entries have sequential data or not, and the result would have been predictable. In this instance, Song is modified such that, for said mapping entries, each entry has LBA/PBA pair, and TAG_L1 and TAG_L2 indicating whether said entry has sequential data or not, wherein all the TAG_L1 and TAG_L2 form a set. It would have been obvious to one of ordinary skill in the art at the time of filing to recognize that applying Jang’s known technique would have yielded i) predictable result of, for said mapping entries, each entry has LBA (one or more logical addresses)/PBA pair, and TAG_L1 and TAG_L2 indicating whether said entry has sequential data (mapping type) or not, wherein all the TAG_L1 and TAG_L2 are a set (bitmap), and ii) the improved claimed invention (see MPEP 2143(I)(D)).
Regarding claim 6, Song in view of Jang teach the storage controller of claim 5 where Jang already teaches, in claim 5,
wherein a value of each respective bit of the bitmap corresponds to an indication that one or more logical addresses corresponding to the respective bit is included in either a first type of mapping entries or a second type of mapping entries (Jang teaches plural entries, each entry include i) a LBA (one or more logical addresses) and PBA pair, and ii) TAG_L1 and TAG_L2 (each respective bit) indicating whether said entry has sequential data (second type of mapping entries) or not (first type of mapping entries) (see Fig. 4, Fig. 7 and corresponding paragraphs). Note that all the TAG_L1 and TAG_L2 are a set (bitmap).)
Regarding claim 7, Song in view of Jang teach the storage controller of claim 5 where Song also teaches
wherein the second capacity is greater than the first capacity, and
wherein a number of logical addresses corresponding to one bit of the bitmap corresponds to a ratio between the second capacity and the first capacity (Song teaches i) fine L2P tables (first mapping table) with fine entries (one or more mapping entries) for each page (first capacity) of data and ii) coarse L2P table (second mapping table) with coarse entries (one or more mapping entries) for each block (second capacity) of data (see Fig. 23 and corresponding paragraphs) wherein plural of said page (first capacity) are combined to form a block (second capacity) (see Fig. 21 and corresponding paragraphs). Note that said block (which is sum of more than one of said page) is greater than one of said page. In exemplary embodiment, said course entries, each indicates one logical address (a number of logical addresses) that maps (corresponds) to four pages (first capacity) per (ratio) block (second capacity) (see Fig. 27 and corresponding paragraphs). Note that in claim 5, said fine and coarse entries (one or more mapping entries), each entry has been modified to have (corresponding) TAG_L1 and TAG_L2 (one bit) indicating whether said entry has sequential data or not, wherein all the TAG_L1 and TAG_L2 are a set (bitmap).)
Regarding claim 8, Song in view of Jang teach the storage controller of claim 5 where Song also teaches
load the first mapping table and the second mapping table and to store data (Song teaches fetching (load), into cache, i) fine L2P table (first mapping table) (see Fig. 25, ¶[113]), and ii) coarse L2P table (second mapping table) (see Fig. 25, ¶[115]). Song also teaches configuring non-volatile memory with second portion to store random data (data) (see Fig. 22, ¶[99]).)
Regarding claim 9, Song teaches
A data write operation method of a storage controller, the method comprising: (Song teaches controller 110 (storage controller) connected to non-volatile memory device 104 (see Fig. 2).)
receiving a request and one or more logical addresses from a host;
identifying, based on the request, a mapping type between the one or more logical addresses and one or more physical addresses of a non-volatile memory device of the storage controller; (Song teaches receiving, from host (host), compiled code (request), with instructions, including a logical address (one or more logical address) for target data, and an indication of whether said target data is sequentially accessed data (see Fig. 25, ¶[110]) wherein when (based on) said indication is sequentially accessed data, accessing (identifying) L2P entry (mapping entry) in a coarse (mapping type) L2P table, and using said L2P entry to translate said logical address to physical address (physical address) in non-volatile memory (non-volatile memory device) (see Fig. 25, ¶[115]). Song also teaches said L2P entry of said coarse L2P table maps (mapping) said logical address to said physical address (see ¶[99], also Fig. 27).)
generating a mapping entry between the one or more logical addresses and the one or more physical addresses;
writing data to a physical address included in the mapping entry (Song teaches when said L2P entry is not found in cache, fetching (generating) said L2P entry (mapping entry) into said cache, and using said L2P entry to translate said logical address to said physical address, wherein said target data is accessed at said physical address (see Fig. 25, ¶[115]). In exemplary embodiment, said sequentially accessed data is for writing (writing) said target data (see ¶[106], [112]).)
As noted in claim 9, Song teaches a base method that generates a mapping entry between logical address and physical address. The claimed invention improves upon said base method by updating relationship between types of the mapping entry.
This improvement to said base method is an application of known technique from Jang – using tag to indicate whether a logical address and physical address mapping is sequential or not. In particular, Jang teaches
updating a relationship between types of [the] mapping entry (Jang teaches plural entries, each entry (mapping entry) include i) a LBA (one or more logical addresses) and PBA (one or more physical addresses) pair (mapping), and ii) TAG_L1 and TAG_L2 indicating (relationship) whether said entry has sequential data or not (types) wherein said TAG_L1 and TAG_L2 are marked (updating) when said entry has sequential data (see Fig. 4, Fig. 7 and corresponding paragraphs). Note that all the TAG_L1 and TAG_L2 are a set.)
One of ordinary skill in the art would recognize that this known technique of using tags to indicate whether LBA/PBA pair has sequential data or not can also be used to indicate whether Song’s mapping entry have sequential data or not, and the result would have been predictable. In this instance, Song is modified such that, said mapping entry (between logical address and physical address) also has TAG_L1 and TAG_L2 indicating whether said mapping entry has sequential data or not, wherein said TAG_L1 and TAG_L2 are marked when said mapping entry has sequential data. It would have been obvious to one of ordinary skill in the art at the time of filing to recognize that applying Jang’s known technique would have yielded i) predictable result of, said mapping entry (between logical address and physical address) also has TAG_L1 and TAG_L2 indicating (relationship) whether said mapping entry has sequential data or not (types), wherein said TAG_L1 and TAG_L2 are marked (updating) when said mapping entry has sequential data, and ii) the improved claimed invention (see MPEP 2143(I)(D)).
Regarding claim 10, Song in view of Jang teach the method of claim 9 where Song also teaches
wherein the mapping entry is included in a plurality of mapping tables, and
wherein the plurality of mapping tables comprises:
a first mapping table comprising one or more mapping entries of a first type corresponding to data of a first capacity; and
a second mapping table comprising one or more mapping entries of a second type corresponding to data of a second capacity (Song teaches i) fine (first type) L2P table (first mapping table) with fine entries (one or more mapping entries of first type) for each page (first capacity) of data (data), and ii) said coarse (second type) L2P table (second mapping table) with coarse entries (one or more mapping entries of second type) for each block (second capacity) of data (data) (see ¶[99]) wherein i) said L2P entry (mapping entry), in said coarse L2P table, is accessed (see Fig. 25, ¶[115]), and ii) said fine L2P table and said coarse L2P table are maintained (manage) by controller (see Fig. 23 and corresponding paragraphs).)
Regarding claim 11, Song in view of Jang teach the method of claim 10 where Song already teaches, in claim 9,
wherein the identifying the mapping type further comprises identifying the mapping type based on whether an operation indicated by the request is a sequential operation (Song teaches receiving, from host (host), compiled code (request), with instructions, including a logical address (one or more logical address) for target data, and an indication of whether said target data is sequentially accessed data (operation is a sequential operation) (see Fig. 25, ¶[110]) wherein when (based on) said indication is sequentially accessed data, accessing (identifying) L2P entry (mapping entry) in a coarse (mapping type) L2P table, and using said L2P entry to translate said logical address to physical address (physical address) in non-volatile memory (non-volatile memory device) (see Fig. 25, ¶[115]). Song also teaches said L2P entry of said coarse L2P table maps (mapping) said logical address to said physical address (see ¶[99], also Fig. 27).)
Regarding claim 12, Song in view of Jang teach the method of claim 10 where Song already teaches, in claim 10,
managing the first mapping table and the second mapping table (Song teaches said fine L2P table and said coarse L2P table are maintained (manage) by controller (see Fig. 23 and corresponding paragraphs).)
Regarding claim 13, Song in view of Jang teach the method of claim 12 where Song also teaches
wherein a number of the one or more mapping entries of the first type is less than a threshold value (Song teaches i) fine L2P tables (first mapping table) with fine entries (one or more mapping entries) for each page (first capacity) of data and ii) coarse L2P table with coarse entries for each block of data (see Fig. 23 and corresponding paragraphs). In exemplary embodiment, there are 8 (number) of said fine entries (the one or more mapping entries) per physical block (see Fig. 26). Note that, in Fig. 26, 8 fine entries per block is less than total of 16 fine entries (threshold value) of 2 blocks.)
Regarding claim 14, Song in view of Jang teach the method of claim 12.
As noted in claim 10, modified Song teaches a base method of managing first and second mapping tables with mapping entries that include mapping entry of one or more logical addresses. The claimed invention improves upon said base method by using a bitmap to indicate mapping type in the following manner.
managing a mapping type of the one or more logical addresses; and
managing a bitmap, and
wherein one bit of the bitmap indicates a type of a mapping entry comprising one or more corresponding logical addresses
This improvement to said base method is an application of known technique from Jang – using tag to indicate whether a logical address and physical address mapping is sequential or not. In particular, Jang teaches
managing a mapping type of [the] one or more logical addresses; and
managing a bitmap, and
wherein one bit of the bitmap indicates a type of a mapping entry comprising one or more corresponding logical addresses (Jang teaches plural entries, each entry (mapping entry) include i) a LBA (one or more logical addresses) and PBA pair (mapping), and ii) TAG_L1 (one bit) and TAG_L2 (one bit), indicating whether said entry has sequential data or not (mapping type, type) (see Fig. 4, Fig. 7 and corresponding paragraphs). Note that i) all the TAG_L1 and TAG_L2 are a set (bitmap), and ii) there is one entry (bit) for TAG_L1 and TAG_L2 respectively.)
One of ordinary skill in the art would recognize that this known technique of using tags to indicate whether LBA/PBA pair has sequential data or not can also be used to indicate whether modified Song’s mapping entries have sequential data or not, and the result would have been predictable. In this instance, modified Song is further modified such that, for said mapping entries (that include mapping entry between one or more logical addresses), each entry has LBA/PBA pair and TAG_L1 and TAG_L2 indicating whether said entry has sequential data or not, wherein all the TAG_L1 and TAG_L2 form a set, and there is only one entry (bit) for said TAG_L1 and said TAG_L2 respectively. It would have been obvious to one of ordinary skill in the art at the time of filing to recognize that applying Jang’s known technique would have yielded i) predictable result of, for said mapping entries (that include mapping entry between one or more logical addresses), each entry has LBA (one or more logical addresses)/PBA pair, and TAG_L1 (one bit) and TAG_L2 (one bit) indicating whether said entry has sequential data (mapping type, type) or not, wherein all the TAG_L1 and TAG_L2 are a set (bitmap), and there is only one entry (bit) for said TAG_L1 and said TAG_L2 respectively, and ii) the improved claimed invention (see MPEP 2143(I)(D)).
Regarding claim 15, Song in view of Jang teach the method of claim 11 where Song also teaches
wherein the second capacity is greater than the first capacity, and (Song teaches plural of said page (first capacity) are combined to form a block (second capacity) (see Fig. 21 and corresponding paragraphs). Note that said block is greater than said page.)
wherein the identifying the mapping type further comprises identifying the mapping entry as the second type based on an operation indicated by the request being the sequential operation (Song teaches receiving, from host (host), compiled code (request), with instructions, including a logical address (one or more logical address) for target data, and an indication of whether said target data is sequentially accessed data (operation is a sequential operation) (see Fig. 25, ¶[110]) wherein when (based on) said indication is sequentially accessed data, accessing (identifying) L2P entry (mapping entry) in a coarse (mapping type, second type) L2P table, and using said L2P entry to translate said logical address to physical address (physical address) in non-volatile memory (non-volatile memory device) (see Fig. 25, ¶[115]).)
Allowable Subject Matter
Claim 4 recites (maximum value of first type mapping entry / maximum value of total allocable mapping entries in both first and second mapping tables) < threshold value. This subject matter is reflected in its entirety in claim 4.
As noted in claim 1, Song teaches coarse (second type) L2P table (second mapping table) with entries (one or more mapping entries), and fine (first type) L2P table (first mapping table) with entries (one or more mapping entries). Song teaches in an exemplary embodiment, said entries of said fine (first type) L2P table is 16 (value) (see Song Fig. 26 and corresponding paragraphs), and said entries of said coarse (second type) L2P table is 4 (value) (see Song Fig. 27 and corresponding paragraphs). Note that number of entries of said fine L2P table / total (maximum) number of entries of said fine and coarse L2P tables is 16//20. Note that said number of entries of said fine L2P table is a fraction of said total number of entries of said fine and coarse L2P tables, resulting in less than said total number of entries of said fine and coarse L2P tables (threshold value). However, Song does not appear to explicitly teach said entries of said fine L2P table (which is 16) is maximum value. In addition, absent hindsight reconstruction, it would not be obvious to set said entries of said fine L2P table to be maximum value. Therefore, claim 4 is allowable over prior art of record.
Conclusion
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/CHIE YEW/ Primary Examiner, Art Unit 2139
