DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Election/Restrictions
Claims 21-26 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on July 2, 2026.
Allowable Subject Matter
Claims 4, 6, 8-14, and 17-20 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the objected to dependent claims are not disclosed by the closest related prior art which includes Zhang et al. (US 20240379045 A1), Yamazaki et al. (US 20220383783 A1), Son et al. (US 20210091163 A1), Ding et al. (US 20250248245 A1), Feng et al. (US 20240268171 A1), Hu et al. (US 20260011287 A1), and Tanikame (US 20090046041 A1).
Regarding claim 4, the closest related art cited above does not teach each and all the claim limitations.
Regarding claim 6, the closest related art cited above does not teach each and all the claim limitations.
Regarding claim 8, the closest related art cited above does not teach each and all the claim limitations. Claim 9 is objected to as dependent upon claim 8.
Regarding claim 10, the closest related art cited above does not teach each and all the claim limitations. Claims 11-14 are objected to as dependent upon claim 10.
Regarding claim 17, the closest related art cited above does not teach each and all the claim limitations.
Regarding claim 18, the closest related art cited above does not teach each and all the claim limitations. Claims 19-20 are objected to as dependent upon claim 18.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (US 20240379045 A1) in view of Yamazaki et al. (US 20220383783 A1), Son et al. (US 20210091163 A1), Ding et al. (US 20250248245 A1), and Feng et al. (US 20240268171 A1).
Regarding claim 1, Zhang teaches a display device (Title, “display device”) comprising:
a substrate (Fig. 3, [0086] a substrate 21);
a first light-blocking layer on the substrate (Fig. 3, [0148], light shielding layer 22 is on substrate 21);
an active layer including a semiconductor area of a first transistor (Fig. 3, [0087] a first active layer 241 is a semiconductor area of a transistor), the active layer on the first light-blocking layer (Fig .3, first active layer 241 is on light shielding layer 22);
a gate layer including a gate electrode of the first transistor (Fig. 3, see first metal layer 243 which is a gate electrode), the gate layer on the active layer (Fig. 3, first metal layer 243 is on first active layer 241);
a pixel electrode on a source metal layer (Fig. 3, [0148], pixel electrode layer 261 is on a source-drain layer 256), the pixel electrode directly connected to an anode connection electrode (Fig. 3, [0148], pixel electrode 261 is directly connected to the first source-drain layer 252 and a second source-drain layer 254, both of which correspond to an anode connection electrode);
a light-emitting layer on the pixel electrode (Fig. 3, [0148], a light-emitting material layer 263 is on pixel electrode layer 261); and
a common electrode on the light-emitting layer (Fig. 3, [0148], a common electrode layer 264 on the light-emitting material layer 263).
Zhang teaches a second transistor that receives a first scan signal from the first scan line and supplies a data voltage (Fig. 1, see transistor T2 which receives a scan signal from Pscan1 and supplies a data voltage Data), however, does not teach the second transistor supplies a data voltage to the gate electrode of the first transistor. Zhang instead teaches the second transistor supplies a data voltage to the drain of a first driving transistor T1.
Zhang does not teach the first light-blocking layer including a first scan line extending in a first direction;
a second transistor that receives a first scan signal from the first scan line and supplies a data voltage to the gate electrode of the first transistor;
a source metal layer on the gate layer, the source metal layer including an anode connection electrode that is directly connected to the active layer (shown at ANE connected to SE5 in fig. 4) and receives a driving current flowing in the first transistor.
Yamazaki teaches a second transistor that receives a first scan signal from the first scan line and supplies a data voltage to the gate electrode of the first transistor (Figs. 27B and 41, see transistor 552 that receives a scan signal from wire 31 and supplies a data voltage supplied from column wire 32 to the gate electrode of transistor 554. See [0399] which teaches, “the conductor 917 having a function of the gate electrode of the transistor 552 and the conductor 925 having a function of a scan line are electrically connected to each other through the conductor 920”).
It would have been obvious to one skilled in the art, before the effective filing date of the invention, to modify Zhang with Yamazaki such that a second transistor supplies a data voltage to the gate electrode of the first driving transistor as this amounts to combining prior art elements according to known methods to yield predictable results. See MPEP 2143, rationale A. Zhang and Yamazaki included each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference. One of ordinary skill in the art could have combined the elements as claimed by known methods, and that in combination, each element merely performs the same function as it does separately One of ordinary skill in the art would have recognized that the results of the combination were predictable as it is well-known in the pixel driving art that the second or source transistor, which connects the data line to the driving transistor, can be connected to either of the drain or the gate of the driving transistor as evidenced by the teachings of Zhang and Yamazaki, and that in either connection configuration the data signal will be fed through to the pixel.
Zhang and Yamazaki do not teach the first light-blocking layer including a first scan line extending in a first direction;
and a source metal layer on the gate layer, the source metal layer including an anode connection electrode that is directly connected to the active layer and receives a driving current flowing in the first transistor.
Son teaches a source metal layer on a gate layer (Figs. 16-18, See conductive capping layer CAP on gate electrode 1335/1375), the source metal layer including an anode connection electrode that is directly connected to the active layer (Figs. 16-18, [0134] See CAP connection to conductive layer 1100 which corresponds to an active layer and includes power supply line 1110 and lower electrode 1125. [0155] also teaches a CAP on gate electrode 1375 a first semiconductor pattern 1210 corresponds to an active layer) and receives a driving current flowing in the first transistor (Fig. 16-1, See driving transistor region DTR wherein CAP is connected to driving transistor first electrode 1371 which will receive a driving current);
a pixel electrode on the source metal layer (Fig. 16-18, See pixel electrode PXE which is on CAP layer), the pixel electrode directly connected to the anode connection electrode (Fig. 15-18, [0136] See pixel electrode PXE which is directly connected to driving transistor DTR electrode 1373).
It would have been obvious to one skilled in the art, before the effective filing date of the invention, to modify Zhang and Yamazaki with Son such that a source metal layer on a gate layer includes an anode connection electrode that is directly connected to the active layer as this amounts to combining prior art elements according to known methods to yield predictable results. See MPEP 2143, rationale A. Zhang. Yamazaki, and Son included each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference. One of ordinary skill in the art could have combined the elements as claimed by known methods, and that in combination, each element merely performs the same function as it does separately One of ordinary skill in the art would have recognized that the results of the combination were predictable as it is well-known in the pixel driving art to provide a source metal layer as this provides the necessary connections between pixel elements.
Zhang, Yamazaki, and Son do not teach the first light-blocking layer including a first scan line extending in a first direction.
Ding teaches a display device wherein a first light-blocking layer including a first scan line extending in a first direction ([0243], “A scan signal line is disposed in a light shielding layer and the scan signal line”).
It would have been obvious to one skilled in the art, before the effective filing date of the invention to modify Zhang, Yamazaki and Son with Ding such that a first light-blocking layer including a first scan line extending in a first direction as Ding teaches an advantage of this arrangement is that it optimizes the structure of a pixel circuit by reducing the occupied area of the pixel drive circuit (Ding, [0243]).
Zhang, Yamazaki, Son, and Ding do not teach the limitation of a second light-blocking layer between the first light-blocking layer and the active layer.
Applicant specification [0076] teaches, “the second light-blocking layer may include a capacitor electrode.”
Likewise, Feng teaches a display device wherein a conductive layer can be provided between a light shielding layer and an active layer of a transistor as a plate of a storage capacitor ([0128], “For example, a conductive layer can be provided between the light shielding layer and the active layer 621 as a plate of the storage capacitor”). Feng, therefore, teaches the limitation of a second light-blocking layer between the first light-blocking layer and the active layer ([0128]).
It would have been obvious to one skilled in the art, before the effective filing date of the invention, to modify Zhang, Yamazaki, Son, and Ding with Feng such that a conductive layer is provided between the light shielding layer and the active layer as Feng teaches this provides a storage capacitor C, shown in Feng fig. 8, which stores data signal voltage Vdata that can control the conduction degree of the driving transistor (Feng, [0121, 0128]).
Regarding claim 2, Zhang teaches the display device comprising:
a data line that supplies the data voltage (Fig. 1, see DATA and [0139] which teaches, “a data signal line Data”).
Zhang does not disclose the data line on the source metal layer and extending in a second direction that intersects the first direction.
Son teaches a data line (Fig. 16, [0134], see data line 1130) on the source metal layer (Figs. 16-18, See conductive capping layer CAP. Data line 1130 is on capping layer CAP via CNT24. Note, this limitation does not state the data line is “on top of the source metal layer” therefore the limitation of “on” is being interpreted as requiring physical connection) and extending in a second direction that intersects the first direction (Fig. 3 shows data line DTL extending in a second direction DR2 that intersects a first direction DR1).
It would have been obvious to one skilled in the art, before the effective filing date of the invention, to modify Zhang and Yamazaki with Son such that a data line is on the source metal layer as this amounts to combining prior art elements according to known methods to yield predictable results. See MPEP 2143, rationale A. Zhang. Yamazaki, and Son included each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference. One of ordinary skill in the art could have combined the elements as claimed by known methods, and that in combination, each element merely performs the same function as it does separately. One of ordinary skill in the art would have recognized that the results of the combination were predictable as it is well-known in the pixel driving art to provide a data line on the source metal layer as this provides the necessary connections between pixel elements.
Regarding claim 3, Zhang, Yamazaki, and Son are not relied upon for teaching the claim limitations.
Ding teaches a second scan line (Fig. 1, see scan line S2) in the first light-blocking layer ([0243], “A scan signal line is disposed in a light shielding layer and the scan signal line”), the second scan line extending in the first direction (Fig. 1 shows S2 extending in the first direction); and
a third transistor (Fig. 3, see transistor T1) that receives a second scan signal from the second scan line (Fig. 3, transistor T1 receive a scan signal from a scan line 30) and supplies a reference voltage to the gate electrode of a first transistor (Fig. 3, see node N1 wherein transistor T1 will supply a voltage to the gate electrode of a first transistor T2).
It would have been obvious to one skilled in the art, before the effective filing date of the invention to modify Zhang, Yamazaki and Son with Ding such that a first light-blocking layer including a second scan line extending in a first direction as Ding teaches an advantage of this arrangement is that it optimizes the structure of a pixel circuit by reducing the occupied area of the pixel drive circuit (Ding, [0243]).
Claims 5 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (US 20240379045 A1) in view of Yamazaki et al. (US 20220383783 A1), Son et al. (US 20210091163 A1), Ding et al. (US 20250248245 A1) and Feng et al. (US 20240268171 A1), as applied to claim 3, above, and further in view of Hu et al. (US 20260011287 A1).
Regarding claim 5, Zhang, Yamazaki, Son, Ding, and Feng are not relied upon for teaching the claim limitations.
Hu teaches a display device further comprising:
a first light-emitting control line in the gate layer (Fig. 11, [0104], “the first gate conductive layer Gate1 includes second light-emitting control signal lines EM2.” [0085], “in some other embodiments…the first light-emitting control signal line EM1 and the second light-emitting control signal line EM2 may be located in the same conductive layer.” Examiner notes this means the gate layer Gate1 may include control signal line EM1), the first light-emitting control line extending in the first direction (Figs. 2 and 9 show light emitting control signal line EM1 extending in the first direction); and
a fourth transistor (Fig. 9, see transistor T1) that receives a first light-emitting signal from the first light-emitting control line (Fig. 9, see EM1) and supplies a driving voltage to a drain electrode of the first transistor ([0079], “A first electrode of the first light-emitting control transistor T1 is electrically connected to a first voltage signal line VDD, and a second electrode of the first light-emitting control transistor T1 is electrically connected to a first electrode of the driving transistor T3”).
It would have been obvious to one skilled in the art, before the effective filing date of the invention, to modify Zhang, Yamazaki, Son, Ding, and Feng with Hu such that a first light-emitting control line is in the gate layer as this amounts to as this amounts to combining prior art elements according to known methods to yield predictable results. See MPEP 2143, rationale A. Zhang. Yamazaki, Son, Ding, Feng, and Hu included each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference. One of ordinary skill in the art could have combined the elements as claimed by known methods, and that in combination, each element merely performs the same function as it does separately. One of ordinary skill in the art would have recognized that the results of the combination were predictable as it is well-known in the pixel driving art to provide a first light-emitting control line in the gate layer as this provides the necessary connections between pixel elements.
Regarding claim 7, Zhang, Yamazaki, Son, Ding, and Feng are not relied upon for teaching the claim limitations.
Hu teaches a display device further comprising:
a second light-emitting control line in the gate layer (Fig. 11, [0104], “the first gate conductive layer Gate1 includes…second light-emitting control signal lines EM2”), the second light-emitting control line extending in the first direction (Fig. 2 shows EM2 extending in the first direction); and
a fifth transistor (Fig. 9, See T2) that receives a second light-emitting signal from the second light- emitting control line (Fig. 9, see T2 receives EM2), the fifth transistor electrically connecting a source electrode of the first transistor to the pixel electrode ([0079], “A first electrode of the second light-emitting control transistor T2 is electrically connected to a second electrode of the driving transistor T3”).
It would have been obvious to one skilled in the art, before the effective filing date of the invention, to modify Zhang, Yamazaki, Son, Ding, and Feng with Hu such that a second light-emitting control line is in the gate layer as this amounts to as this amounts to combining prior art elements according to known methods to yield predictable results. See MPEP 2143, rationale A. Zhang. Yamazaki, Son, Ding, Feng, and Hu included each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference. One of ordinary skill in the art could have combined the elements as claimed by known methods, and that in combination, each element merely performs the same function as it does separately. One of ordinary skill in the art would have recognized that the results of the combination were predictable as it is well-known in the pixel driving art to provide a second light-emitting control line in the gate layer as this provides the necessary connections between pixel elements.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (US 20240379045 A1) in view of Yamazaki et al. (US 20220383783 A1), Ding et al. (US 20250248245 A1), and Tanikame (US 20090046041 A1).
Regarding claim 15, Zhang teaches a display device (Title, “display device”) comprising:
a substrate (Fig. 3, [0086] a substrate 21);
a first light-blocking layer on the substrate (Fig. 3, [0148], light shielding layer 22 is on substrate 21),
a first scan line that supplies a first scan signal extends in a first direction (Fig. 1, see scan signal from Pscan1 extending in a first direction);
a second scan line that supplies a second scan signal extends in the first direction (Fig. 1, see scan signal from Nscan2);
an active layer including a semiconductor area of a first transistor (Fig. 3, [0087] a first active layer 241 is a semiconductor area of a transistor), the active layer on the first light-blocking layer (Fig. 3, first active layer 241 is on light shielding layer 22);
a gate layer including a gate electrode of the first transistor (Fig. 3, see first metal layer 243 which is a gate electrode), the gate layer on the active layer (Fig. 3, first metal layer 243 is on first active layer 241);
a first light-emitting control line that supplies a first light-emitting signal (Fig. 1, [0141], see a light-emitting controlling signal line EM), the first light-emitting control line extends in the first direction (Fig. 1 shows light-emitting controlling signal line EM extending in a first direction);
a second transistor that receives the first scan signal and supplies a data voltage to the first transistor (Fig. 1, see transistor T2 which receives Pscan1 and supplies data voltage Data to transistor T1);
a third transistor that receives the second scan signal and supplies a reference voltage to the gate electrode of the first transistor (Fig. 1, see T4 which receives Nscan2 and supplies an initialization voltage Vi1, which corresponds to a reference voltage, to the gate of transistor T1); and
a fourth transistor that receives the first light-emitting signal and supplies a driving voltage to a drain electrode of the first transistor (Fig. 1, [0141], see first light-emitting control transistor T5 which receives light-emitting control signal EM and supplies a driving voltage VDD to a drain electrode of transistor T1);
a first reference voltage line that supplies the reference voltage to the third transistor (Fig. 1, See first initialization line Vi1 which corresponds to a reference voltage line and supplies a voltage to T4);
and a second reference voltage line that is electrically connected to the first reference voltage line (Fig. 1, See second initialization line Vi2 noting that the entire circuit of fig. 1 is electrically connected thereby teaching Vi1 is connected to Vi2 via intervening circuitry),
wherein the first reference voltage line and the second reference voltage line are disposed in different layers (See [0101, 0122, 0149] which teaches that different parts or lines can be arranged or rearranged in different layers).
Zhang teaches a second transistor that receives a first scan signal from the first scan line and supplies a data voltage (Fig. 1, see transistor T2 which receives a scan signal from Pscan1 and supplies a data voltage Data), however, does not teach the second transistor supplies a data voltage to the gate electrode of the first transistor. Zhang instead teaches the second transistor supplies a data voltage to the drain of a first driving transistor T1.
Zhang does not teach the first scan line in the first light-blocking layer;
the second scan line in the first light-blocking layer;
the first light-emitting control line in the gate layer;
a second transistor that receives the first scan signal and supplies a data voltage to the gate electrode of the first transistor.
Yamazaki teaches a second transistor that receives a first scan signal from the first scan line and supplies a data voltage to the gate electrode of the first transistor (Figs. 27B and 41, see transistor 552 that receives a scan signal from wire 31 and supplies a data voltage supplied from column wire 32 to the gate electrode of transistor 554. See [0399] which teaches, “the conductor 917 having a function of the gate electrode of the transistor 552 and the conductor 925 having a function of a scan line are electrically connected to each other through the conductor 920”).
It would have been obvious to one skilled in the art, before the effective filing date of the invention, to modify Zhang with Yamazaki such that a second transistor supplies a data voltage to the gate electrode of the first driving transistor as this amounts to combining prior art elements according to known methods to yield predictable results. See MPEP 2143, rationale A. Zhang and Yamazaki included each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference. One of ordinary skill in the art could have combined the elements as claimed by known methods, and that in combination, each element merely performs the same function as it does separately One of ordinary skill in the art would have recognized that the results of the combination were predictable as it is well-known in the pixel driving art that the second or source transistor, which connects the data line to the driving transistor, can be connected to either of the drain or the gate of the driving transistor as evidenced by the teachings of Zhang and Yamazaki, and that in either connection configuration the data signal will be fed through to the pixel.
Zhang and Yamazaki do not teach the first scan line in the first light-blocking layer;
the second scan line in the first light-blocking layer; and
the first light-emitting control line in the gate layer.
Ding teaches a display device wherein the first scan line in the first light-blocking layer ([0243], “A scan signal line is disposed in a light shielding layer and the scan signal line”).
While Ding does not explicitly discuss a second scan line, the combination of Zhang, Yamazaki, and Ding teaches the second scan line in the first light-blocking layer as this is merely a duplication of parts. See MPEP 2144.04, In re Harza, 274 F.2d 669, 124 USPQ 378. In the current instance, Ding [0243] teaches an advantage of providing a single scan line disposed in a light shielding layer optimizes the structure of a pixel circuit by reducing the occupied area of the pixel drive circuit. The same advantages will be achieved by providing the second scan line in the first light-blocking layer.
Zhang, Yamazaki, and Ding do not teach the first light-emitting control line in the gate layer.
Tanikame teaches a display device wherein a first light-emitting control line is in the gate layer (Figs. 3 and 8, [0116], “...the light emission control scan line 32,...and the gate electrodes of the transistors 22 to 26 are disposed on the glass substrate 201 (refer to FIG. 3) as the first layer” Note [0127] has the same teaching as [0116]).
Tanikame teaches the advantage of his pixel layout, which designates where the gate layer and the light emission control scan line are arranged, is that the parasitic capacitance coupled to the gate electrode of a drive transistor can be reduced (Tanikame, [0136]). Therefore, it would have been obvious to one skilled in the art, before the effective filing date of the invention, to modify Zhang, Yamazaki, and Ding with Tanikame such that the light-emitting control line is in the gate layer as Tanikame teaches this reduces the parasitic capacitance coupled to the gate electrode of a drive transistor.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (US 20240379045 A1) in view of Yamazaki et al. (US 20220383783 A1), Ding et al. (US 20250248245 A1), and Tanikame (US 20090046041 A1), as applied to claim 15 above, and further in view of Hu et al. (US 20260011287 A1).
Regarding claim 16, Zhang, Yamazaki, Ding, and Tanikame are not relied upon for teaching the claim limitations.
Hu teaches a display device comprising:
a second light-emitting control line that supplies a second light-emitting signal (Fig. 11, [0104], “the first gate conductive layer Gate1 includes…second light-emitting control signal lines EM2”), the second light-emitting control line in the gate layer and extends in the first direction (Fig. 2 shows EM2 extending in the first direction);
a fifth transistor (Fig. 9, See transistor T2) that receives the second light-emitting signal (Fig. 9, see T2 receives EM2), the fifth transistor connected to a source electrode of the first transistor ([0079], “A first electrode of the second light-emitting control transistor T2 is electrically connected to a second electrode of the driving transistor T3”);
a source metal layer on the gate layer (See figs. 11 and 14 [0109, 0111] wherein a first source-drain conductive layer SD1 is disposed on a side of the second conductive layer Gate2 which in turn is disposed on a side of the first gate conductive layer Gate 1), the source metal layer including an anode connection electrode that is directly connected to a source electrode of the fifth transistor (Fig. 14, shows connections between SD1 and transistor T2); and
a pixel electrode on the source metal layer, the pixel electrode directly connected to the anode connection electrode (Fig. 9 which shows a pixel circuit which is directly formed on the source-drain conductive layer SD1 wherein the pixel circuit includes transistor T2 thereby teaching a pixel electrode directly connected to an anode connection electrode of transistor T2).
It would have been obvious to one skilled in the art, before the effective filing date of the invention, to modify Zhang, Yamazaki, Ding, and Tanikame with Hu such that a second light-emitting control line is in the gate layer as this amounts to combining prior art elements according to known methods to yield predictable results. See MPEP 2143, rationale A. Zhang. Yamazaki, Son, Ding, Tanikame, and Hu included each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference. One of ordinary skill in the art could have combined the elements as claimed by known methods, and that in combination, each element merely performs the same function as it does separately. One of ordinary skill in the art would have recognized that the results of the combination were predictable as it is well-known in the pixel driving art to provide a second light-emitting control line in the gate layer as this provides the necessary connections between pixel elements.
Response to Arguments
Applicants’ arguments filed September 4, 2026, are directed towards the amended subject matter. As detailed in the rejection above, Zhang. Yamazaki, Son, Ding, Feng, and Tanikame teach all the claim limitations as currently presented.
Conclusion
Applicants’ amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicants are reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN P BRITTINGHAM whose telephone number is (571)270-7865. The examiner can normally be reached Monday-Thursday, 10 AM - 6 PM, EST.
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/NATHAN P BRITTINGHAM/Primary Examiner, Art Unit 2629
