DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
“wherein the at least one watchdog window is configured to detect a fault pulse of the electrical pulse emitted by the first FCC”
“wherein the selector is configured to toggle to the second FCC based on the detected fault pulse emitted by the first FCC” in claims 1-11.
A review of the specification shows that the following appears to be the corresponding structure for the above limitation described in the specification: (see at least Applicant Specification, para. [0040-0041]: In one embodiment, a selector 182 may be a microcontroller connected to the FCCs 112, 113 via outputs 185…In one embodiment, an integrated watchdog window 180 may be located on a chip of the selector 182. In another embodiment the watchdog window 180 may be located on an external expansion card in the FCC's chassis. The watchdog window 180 may be in communication with the at least one selector 182 to monitor the electrical pulse, or “watchdog”, emitted by each of the FCCs 112,113. )
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claim 1-5, 7-15, & 17-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
A claim that recites an abstract idea, a law of nature, or a natural phenomenon is directed to a judicial exception. Abstract ideas include the following groupings of subject matter, when recited as such in a claim limitation: (a) Mathematical concepts – mathematical relationships, mathematical formulas or equations, mathematical calculations; (b) Certain methods of organizing human activity – fundamental economic principles or practices (including hedging, insurance, mitigating risk); commercial or legal interactions (including agreements in the form of contracts; legal obligations; advertising, marketing or sales activities or behaviors; business relations); managing personal behavior or relationships or interactions between people (including social activities, teaching, and following rules or instructions); and (c) Mental processes – concepts performed in the human mind (including an observation, evaluation, judgment, opinion). See the 2019 Revised Patent Subject Matter Eligibility Guidance.
Even when a judicial element is recited in the claim, an additional claim element(s) that integrates the judicial exception into a practical application of that exception renders the claim eligible under §101. A claim that integrates a judicial exception into a practical application will apply, rely on, or use the judicial exception in a manner that imposes a meaningful limit on the judicial exception, such that the claim is more than a drafting effort designed to monopolize the judicial exception. The following examples are indicative that an additional element or combination of elements may integrate the judicial exception into a practical application:
the additional element(s) reflects an improvement in the functioning of a computer, or an improvement to other technology or technical field;
the additional element(s) that applies or uses a judicial exception to effect a particular treatment or prophylaxis for a disease or medical condition;
the additional element(s) implements a judicial exception with, or uses a judicial exception in conjunction with, a particular machine or manufacture that is integral to the claim;
the additional element(s) effects a transformation or reduction of a particular article to a different state or thing; and
the additional element(s) applies or uses the judicial exception in some other meaningful way beyond generally linking the use of the judicial exception to a particular technological environment, such that the claim as a whole is more than a drafting effort designed to monopolize the exception.
Examples in which the judicial exception has not been integrated into a practical application include:
the additional element(s) merely recites the words ‘‘apply it’’ (or an equivalent) with the judicial exception, or merely includes instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea;
the additional element(s) adds insignificant extra-solution activity to the judicial exception; and
the additional element does no more than generally link the use of a judicial exception to a particular technological environment or field of use.
See the 2019 Revised Patent Subject Matter Eligibility Guidance.
Claims 1, & 12 recite toggle to the second FCC, wherein after toggling to the second FCC, reset the power to the first FCC, toggle to the first FCC after the power has been reset to the first FCC, as drafted, is a device & process that, under its broadest reasonable interpretation, covers performance of the limitation in the mind but for the recitation of generic computer elements. The claim is practically able to be performed in the mind. For example, but for the “A system comprising, a first flight control computer (FCC) of two or more FCCs, a second FCC of the two or more FCCs, at least one selector in communication with the first FCC and the second FCC, a method, monitoring via a watchdog window, a performance of a first flight control computer (FCC) of two or more FCCs, wherein the performance is based on a first electrical pulse emitted by the first FCC, monitoring, via a watchdog window, a performance of a second FCC of the two or more FCCs, wherein the performance is based on a second electrical pulse emitted by the second FCC, ” language, “recite toggle to the second FCC, wherein after toggling to the second FCC, reset the power to the first FCC, toggle to the first FCC after the power has been reset to the first FCC,” in the context of this claim encompasses the user activate the second FCC when the first FCC malfunctions and reset the first FCC. If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the mind but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea.
This judicial exception is not integrated into a practical application. In particular, the claim only recites additional elements – using “A system comprising, a first flight control computer (FCC) of two or more FCCs, a second FCC of the two or more FCCs, at least one selector in communication with the first FCC and the second FCC, a method, monitoring via a watchdog window, a performance of a first flight control computer (FCC) of two or more FCCs, wherein the performance is based on a first electrical pulse emitted by the first FCC, monitoring, via a watchdog window, a performance of a second FCC of the two or more FCCs, wherein the performance is based on a second electrical pulse emitted by the second FCC,”. The devices are recited at a high-level of generality (i.e., device configured to reset a first FCC after malfunctioning) such that it amounts no more than mere instructions to apply the exception using generic computer components. Accordingly, this additional element does not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea. The claim is directed to an abstract idea.
The claim(s) do not include additional elements that are sufficient to amount to significantly more than the judicial exception because the additional elements, as discussed above with respect to integration of the abstract idea into a practical application, the additional elements of using “A system comprising, a first flight control computer (FCC) of two or more FCCs, a second FCC of the two or more FCCs, at least one selector in communication with the first FCC and the second FCC, a method, monitoring via a watchdog window, a performance of a first flight control computer (FCC) of two or more FCCs, wherein the performance is based on a first electrical pulse emitted by the first FCC, monitoring, via a watchdog window, a performance of a second FCC of the two or more FCCs, wherein the performance is based on a second electrical pulse emitted by the second FCC,”, amounts to no more than mere instructions to apply the exception using generic computer components. Mere instructions to apply an exception using generic computer components cannot provide an inventive concept. The claim is not patent eligible.
Similarly for claims 2-5, 7-11, 14-15, & 17-20, in the context of this claim encompasses the user setting a plurality of thresholds to detect when the first FCC has malfunctioned. If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the mind but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea.
This judicial exception is not integrated into a practical application. In particular, the claim only recites additional elements. The claim(s) do not include additional elements that are sufficient to amount to significantly more than the judicial exception. The devices are recited at a high-level of generality (i.e., device configured to reset a first FCC after malfunctioning) such that it amounts no more than mere instructions to apply the exception using generic computer components. Accordingly, this additional element does not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea. Mere instructions to apply an exception using generic computer components cannot provide an inventive concept. The claim is not patent eligible.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-10 of U.S. Patent No. 12430958B2 (“Lisoski”). Although the claims at issue are not identical, they are not patentably distinct from each other because they name the same inventive entity, claim patentably indistinct inventions made as a result of activities undertaken within the scope of a joint research agreement under pre-AIA 35 U.S.C. 103, for applications examined under pre-AIA (first to invent) law and are owned by a common inventor.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 7, 12, & 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2011/0066305A1 (“Lin”), in view of US 2019/0004515A1 (“Matsui”).
As per claim 1 Lin discloses
A system comprising (see at least Lin, para. [0020]: In accordance with one aspect of the present invention, the multi-axis serially redundant, single channel, multi-path, generic fault tolerant fly-by-wire control system…):
a first flight control computer (FCC) of two or more FCCs (see at least Lin, para. [0041]: In the illustrative embodiment, triple serial redundant Flight Control Computers FCC1, FCC2 and FCC3 perform Normal mode control/monitoring functions.);
a second FCC of the two or more FCCs (see at least Lin, para. [0041]: In the illustrative embodiment, triple serial redundant Flight Control Computers FCC1, FCC2 and FCC3 perform Normal mode control/monitoring functions.);
at least one selector in communication with the first FCC and the second FCC (see at least Lin, para. [0074]: Although not illustrated above, the FCC validity sub block may also include other means for input signal checks, such as, Cyclic Redundancy Check (CRC), watchdog timer, etc. Also, the decoded FCC commands by block 860D could be wrapped back to the FCC for comparison with the FCC original commands to ensure that the correct FCC commands have been used by the AECM3D.);
wherein the at least one selector is configured to toggle to the second FCC (see at least Lin, para. [0042]: While any single FCC (FCC1, FCC2 or FCC3) is capable of providing full control functionality in all aircraft axes, the three FCCs operate independently in an active/standby configuration, with no output command voting/comparison between the computers. In this active/standby scheme, while the three FCCs operate in synchronous fashion for failure mode operation as will be discussed in detail below, only one FCC is active at any given time: in this embodiment for example, one FCC (FCC1) is designated the default active "primary" FCC, and the other 2 FCCs (FCC2 and FCC3) each operate independently in a passive "standby" mode to serially come on-line as the "new" primary FCC in the event of failure of the prior active primary FCC (FCC1).);
the at least one selector is further configured to reset power to the first FCC (see at least Lin, para. [0051]: In the illustrative embodiment, the SMCUs also include an analog-direct-link "ultimate" backup function which provides controllability of pitch trim, one elevator and one aileron actuators per SMCU. The ultimate backup function is not active during Normal or Direct mode operation but is only activated as a contingent last resort redundancy in the event of failure of both Normal and Direct modes, and will provide short term safe flight capability, e.g., while attempting to restore the primary flight control system to the Normal/Direct mode after a temporary drop off of all AECMs.).
However Lin does not explicitly disclose
wherein after toggling to the second FCC, the at least one selector is further configured to reset power to the first FCC; and
wherein the at least one selector is configured to toggle to the first FCC after the power has been reset to the first FCC.
Matsui teaches
wherein after toggling to the second FCC, the at least one selector is further configured to reset power to the first FCC (see at least Matsui, para. [0074-0076]: With reference now to FIG. 4, an illustration of a flowchart for a process for monitoring lanes is depicted in accordance with an illustrative embodiment. The process illustrated in FIG. 4 may be implemented in flight control electronics system 202 in control system 200 in FIG. 2. This process may also be implemented in dual lane failure monitor 236 in flight control electronics system 202 in control system 200 in FIG. 2. The different operations illustrated in FIG. 2 may be implemented as program code, hardware, or combination thereof in a data processing system used to implement a flight control electronics system, such as computer system 142 in FIG. 1…The process begins by receiving a message from a transmitting lane in a controller (operation 400). The process identifies an activity indicator, a status from the transmitting lane, a status from a second operating lane, a cyclic redundancy check value generated by the transmitting lane, and a cyclic redundancy check value generated by the second operating lane (operation 402). The process determines whether an anomaly is present using the information identified in the message (operation 404). In this illustrative example, an anomaly is present, in this example, when at least one of an anomaly is indicated in the status, an activity indicator mismatch is present, or an error checking data mismatch is present in the group of messages…If an anomaly is present, the process performs a corrective action (operation 406), with the process terminating thereafter. This corrective action may take various forms. For example, the process may remove power from the controller, disconnect the controller from a communications bus, shut down the controller, reboot the controller, or take some other action.); and
wherein the at least one selector is configured to toggle to the first FCC after the power has been reset to the first FCC (see at least Matsui, para. [0074-0076]: With reference now to FIG. 4, an illustration of a flowchart for a process for monitoring lanes is depicted in accordance with an illustrative embodiment. The process illustrated in FIG. 4 may be implemented in flight control electronics system 202 in control system 200 in FIG. 2. This process may also be implemented in dual lane failure monitor 236 in flight control electronics system 202 in control system 200 in FIG. 2. The different operations illustrated in FIG. 2 may be implemented as program code, hardware, or combination thereof in a data processing system used to implement a flight control electronics system, such as computer system 142 in FIG. 1…The process begins by receiving a message from a transmitting lane in a controller (operation 400). The process identifies an activity indicator, a status from the transmitting lane, a status from a second operating lane, a cyclic redundancy check value generated by the transmitting lane, and a cyclic redundancy check value generated by the second operating lane (operation 402). The process determines whether an anomaly is present using the information identified in the message (operation 404). In this illustrative example, an anomaly is present, in this example, when at least one of an anomaly is indicated in the status, an activity indicator mismatch is present, or an error checking data mismatch is present in the group of messages…If an anomaly is present, the process performs a corrective action (operation 406), with the process terminating thereafter. This corrective action may take various forms. For example, the process may remove power from the controller, disconnect the controller from a communications bus, shut down the controller, reboot the controller, or take some other action.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lin to incorporate the teaching of wherein after toggling to the second FCC, the at least one selector is further configured to reset power to the first FCC; and wherein the at least one selector is configured to toggle to the first FCC after the power has been reset to the first FCC of Matsui in order to more effectively detect when a lane in a controller is operating in an undesirable manner and manage that lane as compared to current techniques for redundancy in a triple redundant system (see at least Matsui, para. [0046]).
As per claim 7 Lin discloses
wherein the at least one selector is configured to toggle to the second FCC based on the detected first fault pulse emitted by the first FCC if there is no detected second fault pulse of the second electrical pulse emitted by the second FCC (see at least Lin, para. [0042]: While any single FCC (FCC1, FCC2 or FCC3) is capable of providing full control functionality in all aircraft axes, the three FCCs operate independently in an active/standby configuration, with no output command voting/comparison between the computers. In this active/standby scheme, while the three FCCs operate in synchronous fashion for failure mode operation as will be discussed in detail below, only one FCC is active at any given time: in this embodiment for example, one FCC (FCC1) is designated the default active "primary" FCC, and the other 2 FCCs (FCC2 and FCC3) each operate independently in a passive "standby" mode to serially come on-line as the "new" primary FCC in the event of failure of the prior active primary FCC (FCC1).).
As per claim 12 Lin discloses
A method comprising: monitoring, via a watchdog window, a performance of a first flight control computer (FCC) of two or more FCCs, wherein the performance is based on a first electrical pulse emitted by the first FCC (see at least Lin, para. [0041]: In the illustrative embodiment, triple serial redundant Flight Control Computers FCC1, FCC2 and FCC3 perform Normal mode control/monitoring functions. para. [0074]: Although not illustrated above, the FCC validity sub block may also include other means for input signal checks, such as, Cyclic Redundancy Check (CRC), watchdog timer, etc. Also, the decoded FCC commands by block 860D could be wrapped back to the FCC for comparison with the FCC original commands to ensure that the correct FCC commands have been used by the AECM3D.);
monitoring, via a watchdog window, a performance of a second FCC of the two or more FCCs, wherein the performance is based on a second electrical pulse emitted by the second FCC (see at least Lin, para. [0041]: In the illustrative embodiment, triple serial redundant Flight Control Computers FCC1, FCC2 and FCC3 perform Normal mode control/monitoring functions. para. [0074]: Although not illustrated above, the FCC validity sub block may also include other means for input signal checks, such as, Cyclic Redundancy Check (CRC), watchdog timer, etc. Also, the decoded FCC commands by block 860D could be wrapped back to the FCC for comparison with the FCC original commands to ensure that the correct FCC commands have been used by the AECM3D.);
toggling, by a selector in communication with the watchdog window, to a second FCC (see at least Lin, para. [0042]: While any single FCC (FCC1, FCC2 or FCC3) is capable of providing full control functionality in all aircraft axes, the three FCCs operate independently in an active/standby configuration, with no output command voting/comparison between the computers. In this active/standby scheme, while the three FCCs operate in synchronous fashion for failure mode operation as will be discussed in detail below, only one FCC is active at any given time: in this embodiment for example, one FCC (FCC1) is designated the default active "primary" FCC, and the other 2 FCCs (FCC2 and FCC3) each operate independently in a passive "standby" mode to serially come on-line as the "new" primary FCC in the event of failure of the prior active primary FCC (FCC1).);
the at least one selector is further configured to reset power to the first FCC (see at least Lin, para. [0051]: In the illustrative embodiment, the SMCUs also include an analog-direct-link "ultimate" backup function which provides controllability of pitch trim, one elevator and one aileron actuators per SMCU. The ultimate backup function is not active during Normal or Direct mode operation but is only activated as a contingent last resort redundancy in the event of failure of both Normal and Direct modes, and will provide short term safe flight capability, e.g., while attempting to restore the primary flight control system to the Normal/Direct mode after a temporary drop off of all AECMs.).
However Lin does not explicitly disclose
resetting, via the selector, power to the first FCC after toggling to the second FCC; and
toggling, by the selector, to the first FCC after the power has been reset to the first FCC.
Matsui teaches
resetting, via the selector, power to the first FCC after toggling to the second FCC (see at least Matsui, para. [0074-0076]: With reference now to FIG. 4, an illustration of a flowchart for a process for monitoring lanes is depicted in accordance with an illustrative embodiment. The process illustrated in FIG. 4 may be implemented in flight control electronics system 202 in control system 200 in FIG. 2. This process may also be implemented in dual lane failure monitor 236 in flight control electronics system 202 in control system 200 in FIG. 2. The different operations illustrated in FIG. 2 may be implemented as program code, hardware, or combination thereof in a data processing system used to implement a flight control electronics system, such as computer system 142 in FIG. 1…The process begins by receiving a message from a transmitting lane in a controller (operation 400). The process identifies an activity indicator, a status from the transmitting lane, a status from a second operating lane, a cyclic redundancy check value generated by the transmitting lane, and a cyclic redundancy check value generated by the second operating lane (operation 402). The process determines whether an anomaly is present using the information identified in the message (operation 404). In this illustrative example, an anomaly is present, in this example, when at least one of an anomaly is indicated in the status, an activity indicator mismatch is present, or an error checking data mismatch is present in the group of messages…If an anomaly is present, the process performs a corrective action (operation 406), with the process terminating thereafter. This corrective action may take various forms. For example, the process may remove power from the controller, disconnect the controller from a communications bus, shut down the controller, reboot the controller, or take some other action.); and
toggling, by the selector, to the first FCC after the power has been reset to the first FCC (see at least Matsui, para. [0074-0076]: With reference now to FIG. 4, an illustration of a flowchart for a process for monitoring lanes is depicted in accordance with an illustrative embodiment. The process illustrated in FIG. 4 may be implemented in flight control electronics system 202 in control system 200 in FIG. 2. This process may also be implemented in dual lane failure monitor 236 in flight control electronics system 202 in control system 200 in FIG. 2. The different operations illustrated in FIG. 2 may be implemented as program code, hardware, or combination thereof in a data processing system used to implement a flight control electronics system, such as computer system 142 in FIG. 1…The process begins by receiving a message from a transmitting lane in a controller (operation 400). The process identifies an activity indicator, a status from the transmitting lane, a status from a second operating lane, a cyclic redundancy check value generated by the transmitting lane, and a cyclic redundancy check value generated by the second operating lane (operation 402). The process determines whether an anomaly is present using the information identified in the message (operation 404). In this illustrative example, an anomaly is present, in this example, when at least one of an anomaly is indicated in the status, an activity indicator mismatch is present, or an error checking data mismatch is present in the group of messages…If an anomaly is present, the process performs a corrective action (operation 406), with the process terminating thereafter. This corrective action may take various forms. For example, the process may remove power from the controller, disconnect the controller from a communications bus, shut down the controller, reboot the controller, or take some other action.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lin to incorporate the teaching of wherein after toggling to the second FCC, the at least one selector is further configured to reset power to the first FCC; and wherein the at least one selector is configured to toggle to the first FCC after the power has been reset to the first FCC of Matsui in order to more effectively detect when a lane in a controller is operating in an undesirable manner and manage that lane as compared to current techniques for redundancy in a triple redundant system (see at least Matsui, para. [0046]).
As per claim 20 Lin discloses
further comprising: monitoring, via the watchdog window, the performance of the first flight control computer (FCC) after the first FCC is toggled by the selector (see at least Lin, para. [0070]: Each FCC is comprised of a command lane and a monitor lane with dissimilar processors (type A processor for command lane and type B processor for monitor lane), which compare against one another. In a self-testing regime, a discrepancy outside a predetermined tolerance between the command and monitor lanes will result in the affected FCC taking itself offline and its status being set as invalid, that status indicated to the AECMs ("FCC invalid"). & para. [0074]: Although not illustrated above, the FCC validity sub block may also include other means for input signal checks, such as, Cyclic Redundancy Check (CRC), watchdog timer, etc. Also, the decoded FCC commands by block 860D could be wrapped back to the FCC for comparison with the FCC original commands to ensure that the correct FCC commands have been used by the AECM3D.).
Claim(s) 2-4, 11, & 13-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin, in view of Matsui, in view of US 4589066B1 (“Lam”).
As per claim 2 Lin does not explicitly disclose
further comprising: at least one watchdog window in communication with the at least one selector wherein the at least one watchdog window monitors a performance of the first FCC based on a first electrical pulse emitted by the first FCC and wherein the at least one watchdog window monitors a performance of the second FCC based on a second electrical pulse emitted by the second FCC.
Lam teaches
further comprising: at least one watchdog window in communication with the at least one selector wherein the at least one watchdog window monitors a performance of the first FCC based on a first electrical pulse emitted by the first FCC and wherein the at least one watchdog window monitors a performance of the second FCC based on a second electrical pulse emitted by the second FCC (see at least Lam, col. 3 lines 33-35: If two sync pulses fail, indicating two processors are out of sync, the supervisory software routine replaces the out of sync processors with good ones. & col. 8 lines 3-39: watchdog (override) circuit 88 is provided to generate an Interrupt pulse in the event that any synchronizer circuit indicates that three of the four sync pulses have not arrived; i.e., the TWO, THREE and FOUR OUT OF FOUR paths are not actuated, since this is an indication that the synchronizer is faulty and not that three processors are out of sync. This requires that synchronizer and its associated processor be removed. In the sync circuit mechanization shown in FIG. 3, no Interrupt pulse is generated if three sync pulses are missing because the decision logic circuits in the TWO, THREE and FOUR OUT OF FOUR paths will disable the clock pulse OR gates. The watchdog circuit which has an internal clock and counter, generates an Interrupt pulse if it is allowed to count for an interval larger than the minor frame (viz, 9 milliseconds vs. the 6.25 millisecond minor frame interval. The watchdog circuit includes counter 89 which has a counting period larger than the minor frame interval. The counter is coupled through the AND gate 90 to the programmable counter and the sync reset pulse line from the local processor.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lin to incorporate the teaching of at least one watchdog window in communication with the at least one selector wherein the at least one watchdog window monitors a performance of the first FCC based on a first electrical pulse emitted by the first FCC and wherein the at least one watchdog window monitors a performance of the second FCC based on a second electrical pulse emitted by the second FCC of Lam in order to provide a fault-tolerant computer including a plurality of redundant processors which are readily synchronized at the frame level (see at least Lam, col. 1 lines 57-60).
As per claim 3 Lin does not explicitly disclose
wherein the at least one watchdog window is configured to detect a first fault pulse of the first electrical pulse emitted by the first FCC, wherein the detected first fault pulse is a pulse that is outside a predetermined frequency range and a predetermined amplitude range.
Lam teaches
wherein the at least one watchdog window is configured to detect a first fault pulse of the first electrical pulse emitted by the first FCC (see at least Lam, col. 2 lines 40-51: Each of the processors includes a Bus Interface Unit for interprocessor communication and synchronization at the end of each processor minor frame. The interface units are interconnected by dedicated buses from all processors in the multiprocessor channel. A predetermined number of the total sync pulses (as, for example, four out of eight) are applied to the synchronization circuit in the bus interface unit. The synchronization logic determines whether the synchronizing pulses are received within a given "time window" (such as two microseconds, for example), which is considered synchronization in real time. & col. 3 lines 33-35: If two sync pulses fail, indicating two processors are out of sync, the supervisory software routine replaces the out of sync processors with good ones. & col. 8 lines 3-39: watchdog (override) circuit 88 is provided to generate an Interrupt pulse in the event that any synchronizer circuit indicates that three of the four sync pulses have not arrived; i.e., the TWO, THREE and FOUR OUT OF FOUR paths are not actuated, since this is an indication that the synchronizer is faulty and not that three processors are out of sync. This requires that synchronizer and its associated processor be removed. In the sync circuit mechanization shown in FIG. 3, no Interrupt pulse is generated if three sync pulses are missing because the decision logic circuits in the TWO, THREE and FOUR OUT OF FOUR paths will disable the clock pulse OR gates. The watchdog circuit which has an internal clock and counter, generates an Interrupt pulse if it is allowed to count for an interval larger than the minor frame (viz, 9 milliseconds vs. the 6.25 millisecond minor frame interval. The watchdog circuit includes counter 89 which has a counting period larger than the minor frame interval. The counter is coupled through the AND gate 90 to the programmable counter and the sync reset pulse line from the local processor.);
wherein the detected first fault pulse is a pulse that is outside a predetermined range (see at least Lam, col. 4 lines 45-60: The local reset generator 43 contains ONE OUT OF FOUR, TWO OUT OF FOUR, THREE OUT OF FOUR, and FOUR OUT OF FOUR synchronizer decision logic circuits to generate the processor Interrupt pulse upon appearance of all four pulses, or if the TWO OUT OF FOUR or THREE OUT OF FOUR circuits time out; i.e., if one or more of the remaining sync pulses are separated by an interval greater than the two microsecond "time window". Information about the states of the logic circuits and the identity of the sync pulses which have or have not arrived in the "time window" is stored in a buffer storage means. The buffer element is interrogated during the supervisory software routine to identify any failed sync pulse and to permit removal of the failed pulse or pulses and their associated processors.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lin to incorporate the teaching of wherein the at least one watchdog window is configured to detect a first fault pulse of the first electrical pulse emitted by the first FCC, wherein the detected first fault pulse is a pulse that is outside a predetermined frequency range and a predetermined amplitude range of Lam in order to provide a fault-tolerant computer including a plurality of redundant processors which are readily synchronized at the frame level (see at least Lam, col. 1 lines 57-60).
As per claim 4 Lin does not explicitly disclose
wherein the at least one watchdog window is configured to detect a second fault pulse of the second electrical pulse emitted by the second FCC
Lam teaches
wherein the at least one watchdog window is configured to detect a second fault pulse of the second electrical pulse emitted by the second FCC (see at least Lam, col. 4 lines 45-60: The local reset generator 43 contains ONE OUT OF FOUR, TWO OUT OF FOUR, THREE OUT OF FOUR, and FOUR OUT OF FOUR synchronizer decision logic circuits to generate the processor Interrupt pulse upon appearance of all four pulses, or if the TWO OUT OF FOUR or THREE OUT OF FOUR circuits time out; i.e., if one or more of the remaining sync pulses are separated by an interval greater than the two microsecond "time window". Information about the states of the logic circuits and the identity of the sync pulses which have or have not arrived in the "time window" is stored in a buffer storage means. The buffer element is interrogated during the supervisory software routine to identify any failed sync pulse and to permit removal of the failed pulse or pulses and their associated processors.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lin to incorporate the teaching of wherein the at least one watchdog window is configured to detect a second fault pulse of the second electrical pulse emitted by the second FCC of Lam in order to provide a fault-tolerant computer including a plurality of redundant processors which are readily synchronized at the frame level (see at least Lam, col. 1 lines 57-60).
As per claim 11 Lin teaches
wherein the at least one watchdog window is further configured to monitor the performance of the first FCC after the first FCC is toggled by the at least one selector (see at least Lin, para. [0070]: Each FCC is comprised of a command lane and a monitor lane with dissimilar processors (type A processor for command lane and type B processor for monitor lane), which compare against one another. In a self-testing regime, a discrepancy outside a predetermined tolerance between the command and monitor lanes will result in the affected FCC taking itself offline and its status being set as invalid, that status indicated to the AECMs ("FCC invalid"). & para. [0074]: Although not illustrated above, the FCC validity sub block may also include other means for input signal checks, such as, Cyclic Redundancy Check (CRC), watchdog timer, etc. Also, the decoded FCC commands by block 860D could be wrapped back to the FCC for comparison with the FCC original commands to ensure that the correct FCC commands have been used by the AECM3D.).
As per claim 13 Lin does not explicitly disclose
further comprising: detecting, via the watchdog window, a first fault pulse of the first electrical pulse emitted by the first FCC, wherein the detected first fault pulse is a pulse that is outside a predetermined frequency range and a predetermined amplitude range.
Lam teaches
further comprising: detecting, via the watchdog window, a first fault pulse of the first electrical pulse emitted by the first FCC (see at least Lam, col. 2 lines 40-51: Each of the processors includes a Bus Interface Unit for interprocessor communication and synchronization at the end of each processor minor frame. The interface units are interconnected by dedicated buses from all processors in the multiprocessor channel. A predetermined number of the total sync pulses (as, for example, four out of eight) are applied to the synchronization circuit in the bus interface unit. The synchronization logic determines whether the synchronizing pulses are received within a given "time window" (such as two microseconds, for example), which is considered synchronization in real time. & col. 3 lines 33-35: If two sync pulses fail, indicating two processors are out of sync, the supervisory software routine replaces the out of sync processors with good ones. & col. 8 lines 3-39: watchdog (override) circuit 88 is provided to generate an Interrupt pulse in the event that any synchronizer circuit indicates that three of the four sync pulses have not arrived; i.e., the TWO, THREE and FOUR OUT OF FOUR paths are not actuated, since this is an indication that the synchronizer is faulty and not that three processors are out of sync. This requires that synchronizer and its associated processor be removed. In the sync circuit mechanization shown in FIG. 3, no Interrupt pulse is generated if three sync pulses are missing because the decision logic circuits in the TWO, THREE and FOUR OUT OF FOUR paths will disable the clock pulse OR gates. The watchdog circuit which has an internal clock and counter, generates an Interrupt pulse if it is allowed to count for an interval larger than the minor frame (viz, 9 milliseconds vs. the 6.25 millisecond minor frame interval. The watchdog circuit includes counter 89 which has a counting period larger than the minor frame interval. The counter is coupled through the AND gate 90 to the programmable counter and the sync reset pulse line from the local processor.),
wherein the detected first fault pulse is a pulse that is outside a predetermined frequency range and a predetermined amplitude range (see at least Lam, col. 4 lines 45-60: The local reset generator 43 contains ONE OUT OF FOUR, TWO OUT OF FOUR, THREE OUT OF FOUR, and FOUR OUT OF FOUR synchronizer decision logic circuits to generate the processor Interrupt pulse upon appearance of all four pulses, or if the TWO OUT OF FOUR or THREE OUT OF FOUR circuits time out; i.e., if one or more of the remaining sync pulses are separated by an interval greater than the two microsecond "time window". Information about the states of the logic circuits and the identity of the sync pulses which have or have not arrived in the "time window" is stored in a buffer storage means. The buffer element is interrogated during the supervisory software routine to identify any failed sync pulse and to permit removal of the failed pulse or pulses and their associated processors.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lin to incorporate the teaching of detecting, via the watchdog window, a first fault pulse of the first electrical pulse emitted by the first FCC, wherein the detected first fault pulse is a pulse that is outside a predetermined frequency range and a predetermined amplitude range of Lam in order to provide a fault-tolerant computer including a plurality of redundant processors which are readily synchronized at the frame level (see at least Lam, col. 1 lines 57-60).
As per claim 14 Lin does not explicitly disclose
further comprising: detecting, via the watchdog window, a second fault pulse of the second electrical pulse emitted by the second FCC.
Lam teaches
detecting, via the watchdog window, a second fault pulse of the second electrical pulse emitted by the second FCC (see at least Lam, col. 4 lines 45-60: The local reset generator 43 contains ONE OUT OF FOUR, TWO OUT OF FOUR, THREE OUT OF FOUR, and FOUR OUT OF FOUR synchronizer decision logic circuits to generate the processor Interrupt pulse upon appearance of all four pulses, or if the TWO OUT OF FOUR or THREE OUT OF FOUR circuits time out; i.e., if one or more of the remaining sync pulses are separated by an interval greater than the two microsecond "time window". Information about the states of the logic circuits and the identity of the sync pulses which have or have not arrived in the "time window" is stored in a buffer storage means. The buffer element is interrogated during the supervisory software routine to identify any failed sync pulse and to permit removal of the failed pulse or pulses and their associated processors.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lin to incorporate the teaching of detecting, via the watchdog window, a second fault pulse of the second electrical pulse emitted by the second FCC of Lam in order to provide a fault-tolerant computer including a plurality of redundant processors which are readily synchronized at the frame level (see at least Lam, col. 1 lines 57-60).
As per claim 15 Lin discloses
wherein toggling, by the selector in communication with the watchdog window, to the second FCC is based on the detected first fault pulse emitted by the first FCC if there is no detected second fault pulse of the second electrical pulse emitted by the second FCC (see at least Lin, para. [0042]: While any single FCC (FCC1, FCC2 or FCC3) is capable of providing full control functionality in all aircraft axes, the three FCCs operate independently in an active/standby configuration, with no output command voting/comparison between the computers. In this active/standby scheme, while the three FCCs operate in synchronous fashion for failure mode operation as will be discussed in detail below, only one FCC is active at any given time: in this embodiment for example, one FCC (FCC1) is designated the default active "primary" FCC, and the other 2 FCCs (FCC2 and FCC3) each operate independently in a passive "standby" mode to serially come on-line as the "new" primary FCC in the event of failure of the prior active primary FCC (FCC1).).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin, in view of Matsui, in view of Lam, in view of US 2012/0072058A1 (“Regmi”).
As per claim 5 Lin does not explicitly disclose
further comprising: a flight termination system
Regmi teaches
further comprising: a flight termination system (see at least Regmi, para. [0042]: The level of fault (i.e. minor, major, cautious, and emergency) can be differentiated by using/reading ("sensing") the parameters of the component/equipment and comparing to their normal range. The normal, caution, danger/emergency range of the parameters could be determined/retrieved from the programmed software and or by built-in electronic circuits and compared to the current condition. If the fault is major and immediate action is necessary, then the built-in system senses and prepares the emergency landing system by transferring or communicating any necessary data or initiating any sequences. For these purposes, the onboard system senses the current aircraft position, type of fault, then enables/disenables the required systems and then implements the system as described in the emergency landing section.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lin to incorporate the teaching of a flight termination system of Regmi in order to provide automated systems for an aircraft that can adapt to emergencies and faults to provide continued safe operation of the aircraft (see at least Regmi, para. [0010]).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin, in view of Matsui, in view of Lam, in view of Regmi, in view of US 2019/0377021A1 (“Bhalwankar”).
As per claim 6 Lin does not explicitly disclose
wherein the flight termination system is configured to implement a landing procedure based on the detected first fault pulse emitted by the first FCC and the detected second fault pulse emitted by the second FCC.
Bhalwankar teaches
wherein the flight termination system is configured to implement a landing procedure based on the detected first fault pulse emitted by the first FCC and the detected second fault pulse emitted by the second FCC (see at least Bhalwankar, para. [0005]: An electrical protection/detection system may detect and appropriately respond to faults, such that (in the worst-case scenario) an aircraft is able to land safely after an electrical fault has occurred. & para. [0073-0075]: . For example and without limitation, the ECU 104 may be configured to indicate a ground fault if the first GFD unit 110 and/or the second GFD unit 120 detects ground current for a period of time. An amplitude threshold for the ground current may be lower than other ground fault detection systems, which may permit the electrical system 100 to detect higher frequency and lower amplitude ground fault currents that may damage components over time (even if such ground current is not an immediate risk).).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lin to incorporate the teaching of wherein the flight termination system is configured to implement a landing procedure based on the detected first fault pulse emitted by the first FCC and the detected second fault pulse emitted by the second FCC of Bhalwankar in order for the system to detect and appropriately respond to faults, such that (in the worst-case scenario) an aircraft is able to land safely after an electrical fault has occurred (see at least Bhalwankar, para. [0005]).
Regmi teaches
wherein the flight termination system is configured to implement a landing procedure based on the detected first fault pulse emitted by the first FCC and the detected second fault pulse emitted by the second FCC (see at least Regmi, para. [0042]: The level of fault (i.e. minor, major, cautious, and emergency) can be differentiated by using/reading ("sensing") the parameters of the component/equipment and comparing to their normal range. The normal, caution, danger/emergency range of the parameters could be determined/retrieved from the programmed software and or by built-in electronic circuits and compared to the current condition. If the fault is major and immediate action is necessary, then the built-in system senses and prepares the emergency landing system by transferring or communicating any necessary data or initiating any sequences. For these purposes, the onboard system senses the current aircraft position, type of fault, then enables/disenables the required systems and then implements the system as described in the emergency landing section.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lin to incorporate the teaching of wherein the flight termination system is configured to implement a landing procedure based on the detected first fault pulse and the second detected fault pulse of Regmi in order to provide automated systems for an aircraft that can adapt to emergencies and faults to provide continued safe operation of the aircraft (see at least Regmi, para. [0010]).
Claim(s) 8-10 & 17-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin, in view of Matsui, in view of Lam, in view of Bhalwankar.
As per claim 8 Lin does not explicitly disclose
wherein one of the detected first fault pulse and the detected second fault pulse is slower than the predetermined frequency range.
Lam teaches
wherein the detected fault pulse is slower than the predetermined range (see at least Lam, col. 9 lines 53-67: A two pulse failure in which two pulses did not arrive is ambiguous in the sense that it is not certain whether two pulses arrived "early" or two pulses arrived "late". 55 The supervisory software routine is designed to determine and correct such a situation. If the identified situation has not occurred before, one processor associated respectively with the "early" pair and one with the "late" pair is replaced. At the end of the next minor 60 frame, the remaining one of the two processors in one of the pairs will be out of sync, thus indicating whether one pair is "late" or one pair is "early". The remaining faulty processor is replaced in the next iteration, thus curing the system within three minor frames…. [Examiner Note: if the pulse is late, the pulse is interpreted to be slower than the preferred range, and if the pulse is early, the pulse is interpreted to be faster than the preferred range.]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lin to incorporate the teaching of wherein the detected fault pulse is slower than the predetermined range of Lam in order to provide a fault-tolerant computer including a plurality of redundant processors which are readily synchronized at the frame level (see at least Lam, col. 1 lines 57-60).
Bhalwankar teaches
predetermined frequency range (see at least Bhalwankar, para. [0073-0075]: For example and without limitation, a threshold of high frequency ground current may be about 1 A or less, about 500 mA or less, or other values… Embodiments of electrical systems 100 may enable detection of ground faults of transformer rectifier units, such as of multi-pulse auto-transformers. Embodiments of electrical systems 100 may not require FFT-based complex higher end microcontroller processing, DSP (digital signal processing), and/or FPGA (field programmable gate array) processing. Embodiments of electrical systems 100 may be utilized in connection with carbon composite aircraft. ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lin to incorporate the teaching of predetermined frequency range of Bhalwankar in order for the system to detect and appropriately respond to faults, such that (in the worst-case scenario) an aircraft is able to land safely after an electrical fault has occurred (see at least Bhalwankar, para. [0005]).
As per claim 9 Lin does not explicitly disclose
wherein the detected first fault pulse is faster than the predetermined frequency range.
Lam teaches
wherein the detected fault pulse is faster than the predetermined range (see at least Lam, col. 9 lines 53-67: A two pulse failure in which two pulses did not arrive is ambiguous in the sense that it is not certain whether two pulses arrived "early" or two pulses arrived "late". 55 The supervisory software routine is designed to determine and correct such a situation. If the identified situation has not occurred before, one processor associated respectively with the "early" pair and one with the "late" pair is replaced. At the end of the next minor 60 frame, the remaining one of the two processors in one of the pairs will be out of sync, thus indicating whether one pair is "late" or one pair is "early". The remaining faulty processor is replaced in the next iteration, thus curing the system within three minor frames…. [Examiner Note: if the pulse is late, the pulse is interpreted to be slower than the preferred range, and if the pulse is early, the pulse is interpreted to be faster than the preferred range.]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lin to incorporate the teaching of wherein the detected fault pulse is faster than the predetermined range of Lam in order to provide a fault-tolerant computer including a plurality of redundant processors which are readily synchronized at the frame level (see at least Lam, col. 1 lines 57-60).
Bhalwankar teaches
predetermined frequency range (see at least Bhalwankar, para. [0073-0075]: For example and without limitation, a threshold of high frequency ground current may be about 1 A or less, about 500 mA or less, or other values… Embodiments of electrical systems 100 may enable detection of ground faults of transformer rectifier units, such as of multi-pulse auto-transformers. Embodiments of electrical systems 100 may not require FFT-based complex higher end microcontroller processing, DSP (digital signal processing), and/or FPGA (field programmable gate array) processing. Embodiments of electrical systems 100 may be utilized in connection with carbon composite aircraft. ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lin to incorporate the teaching of predetermined frequency range of Bhalwankar in order for the system to detect and appropriately respond to faults, such that (in the worst-case scenario) an aircraft is able to land safely after an electrical fault has occurred (see at least Bhalwankar, para. [0005]).
As per claim 10 Lin does not explicitly disclose
wherein the detected first fault pulse is a pulse that has a frequency and amplitude outside of the predetermined frequency range and the predetermined amplitude range of a baseline pulse.
Bhalwankar teaches
wherein the detected fault pulse is a pulse that has a frequency and amplitude outside of the predetermined frequency range and the predetermined amplitude range of a baseline pulse (see at least Bhalwankar, para. [0073-0075]: An ECU 104 may be connected to the first GFD unit 110 and/or the second GFD unit 120. The ECU 104 may be configured to monitor the first GFD unit 110 and/or the second GFD unit 120 over time. For example and without limitation, the ECU 104 may be configured to indicate a ground fault if the first GFD unit 110 and/or the second GFD unit 120 detects ground current for a period of time. An amplitude threshold for the ground current may be lower than other ground fault detection systems, which may permit the electrical system 100 to detect higher frequency and lower amplitude ground fault currents that may damage components over time (even if such ground current is not an immediate risk). For example and without limitation, a threshold of high frequency ground current may be about 1 A or less, about 500 mA or less, or other values… Embodiments of electrical systems 100 may enable detection of ground faults of transformer rectifier units, such as of multi-pulse auto-transformers. Embodiments of electrical systems 100 may not require FFT-based complex higher end microcontroller processing, DSP (digital signal processing), and/or FPGA (field programmable gate array) processing. Embodiments of electrical systems 100 may be utilized in connection with carbon composite aircraft. ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lin to incorporate the teaching of wherein the detected fault pulse is a pulse that has a frequency and amplitude outside of the predetermined frequency range and the predetermined amplitude range of a baseline pulse of Bhalwankar in order for the system to detect and appropriately respond to faults, such that (in the worst-case scenario) an aircraft is able to land safely after an electrical fault has occurred (see at least Bhalwankar, para. [0005]).
As per claim 17 Lin does not explicitly disclose
wherein the detected first fault pulse is slower than the predetermined frequency range.
Lam teaches
wherein the detected fault pulse is slower than the predetermined range (see at least Lam, col. 9 lines 53-67: A two pulse failure in which two pulses did not arrive is ambiguous in the sense that it is not certain whether two pulses arrived "early" or two pulses arrived "late". 55 The supervisory software routine is designed to determine and correct such a situation. If the identified situation has not occurred before, one processor associated respectively with the "early" pair and one with the "late" pair is replaced. At the end of the next minor 60 frame, the remaining one of the two processors in one of the pairs will be out of sync, thus indicating whether one pair is "late" or one pair is "early". The remaining faulty processor is replaced in the next iteration, thus curing the system within three minor frames…. [Examiner Note: if the pulse is late, the pulse is interpreted to be slower than the preferred range, and if the pulse is early, the pulse is interpreted to be faster than the preferred range.]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lin to incorporate the teaching of wherein the detected fault pulse is slower than the predetermined range of Lam in order to provide a fault-tolerant computer including a plurality of redundant processors which are readily synchronized at the frame level (see at least Lam, col. 1 lines 57-60).
Bhalwankar teaches
predetermined frequency range (see at least Bhalwankar, para. [0073-0075]: For example and without limitation, a threshold of high frequency ground current may be about 1 A or less, about 500 mA or less, or other values… Embodiments of electrical systems 100 may enable detection of ground faults of transformer rectifier units, such as of multi-pulse auto-transformers. Embodiments of electrical systems 100 may not require FFT-based complex higher end microcontroller processing, DSP (digital signal processing), and/or FPGA (field programmable gate array) processing. Embodiments of electrical systems 100 may be utilized in connection with carbon composite aircraft. ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lin to incorporate the teaching of predetermined frequency range of Bhalwankar in order for the system to detect and appropriately respond to faults, such that (in the worst-case scenario) an aircraft is able to land safely after an electrical fault has occurred (see at least Bhalwankar, para. [0005]).
As per claim 18 Lin does not explicitly disclose
wherein the detected first fault pulse is faster than the predetermined frequency range.
Lam teaches
wherein the detected fault pulse is faster than the predetermined range (see at least Lam, col. 9 lines 53-67: A two pulse failure in which two pulses did not arrive is ambiguous in the sense that it is not certain whether two pulses arrived "early" or two pulses arrived "late". 55 The supervisory software routine is designed to determine and correct such a situation. If the identified situation has not occurred before, one processor associated respectively with the "early" pair and one with the "late" pair is replaced. At the end of the next minor 60 frame, the remaining one of the two processors in one of the pairs will be out of sync, thus indicating whether one pair is "late" or one pair is "early". The remaining faulty processor is replaced in the next iteration, thus curing the system within three minor frames…. [Examiner Note: if the pulse is late, the pulse is interpreted to be slower than the preferred range, and if the pulse is early, the pulse is interpreted to be faster than the preferred range.]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lin to incorporate the teaching of wherein the detected fault pulse is faster than the predetermined range of Lam in order to provide a fault-tolerant computer including a plurality of redundant processors which are readily synchronized at the frame level (see at least Lam, col. 1 lines 57-60).
Bhalwankar teaches
predetermined frequency range (see at least Bhalwankar, para. [0073-0075]: For example and without limitation, a threshold of high frequency ground current may be about 1 A or less, about 500 mA or less, or other values… Embodiments of electrical systems 100 may enable detection of ground faults of transformer rectifier units, such as of multi-pulse auto-transformers. Embodiments of electrical systems 100 may not require FFT-based complex higher end microcontroller processing, DSP (digital signal processing), and/or FPGA (field programmable gate array) processing. Embodiments of electrical systems 100 may be utilized in connection with carbon composite aircraft. ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lin to incorporate the teaching of predetermined frequency range of Bhalwankar in order for the system to detect and appropriately respond to faults, such that (in the worst-case scenario) an aircraft is able to land safely after an electrical fault has occurred (see at least Bhalwankar, para. [0005]).
As per claim 19 Lin does not explicitly disclose
wherein the detected first fault pulse is a pulse that has a frequency and amplitude outside of the predetermined frequency range and the predetermined amplitude range of a baseline pulse.
Bhalwankar teaches
wherein the detected fault pulse is a pulse that has a frequency and amplitude outside of the predetermined frequency range and the predetermined amplitude range of a baseline pulse (see at least Bhalwankar, para. [0073-0075]: An ECU 104 may be connected to the first GFD unit 110 and/or the second GFD unit 120. The ECU 104 may be configured to monitor the first GFD unit 110 and/or the second GFD unit 120 over time. For example and without limitation, the ECU 104 may be configured to indicate a ground fault if the first GFD unit 110 and/or the second GFD unit 120 detects ground current for a period of time. An amplitude threshold for the ground current may be lower than other ground fault detection systems, which may permit the electrical system 100 to detect higher frequency and lower amplitude ground fault currents that may damage components over time (even if such ground current is not an immediate risk). For example and without limitation, a threshold of high frequency ground current may be about 1 A or less, about 500 mA or less, or other values… Embodiments of electrical systems 100 may enable detection of ground faults of transformer rectifier units, such as of multi-pulse auto-transformers. Embodiments of electrical systems 100 may not require FFT-based complex higher end microcontroller processing, DSP (digital signal processing), and/or FPGA (field programmable gate array) processing. Embodiments of electrical systems 100 may be utilized in connection with carbon composite aircraft. ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lin to incorporate the teaching of wherein the detected fault pulse is a pulse that has a frequency and amplitude outside of the predetermined frequency range and the predetermined amplitude range of a baseline pulse of Bhalwankar in order for the system to detect and appropriately respond to faults, such that (in the worst-case scenario) an aircraft is able to land safely after an electrical fault has occurred (see at least Bhalwankar, para. [0005]).
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin, in view of Matsui, in view of Lam, in view of Bhalwankar, in view of Regmi.
As per claim 16 Lin does not explicitly disclose
further comprising: implementing, by a flight termination system, a landing procedure based on the detected first fault pulse emitted by the first FCC and the detected second fault pulse emitted by the second FCC.
Bhalwankar teaches
implementing, by a flight termination system, a landing procedure based on the detected first fault pulse emitted by the first FCC and the detected second fault pulse emitted by the second FCC (see at least Bhalwankar, para. [0005]: An electrical protection/detection system may detect and appropriately respond to faults, such that (in the worst-case scenario) an aircraft is able to land safely after an electrical fault has occurred. & para. [0073-0075]: . For example and without limitation, the ECU 104 may be configured to indicate a ground fault if the first GFD unit 110 and/or the second GFD unit 120 detects ground current for a period of time. An amplitude threshold for the ground current may be lower than other ground fault detection systems, which may permit the electrical system 100 to detect higher frequency and lower amplitude ground fault currents that may damage components over time (even if such ground current is not an immediate risk).).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lin to incorporate the teaching of wherein the flight termination system is configured to implement a landing procedure based on the detected first fault pulse emitted by the first FCC and the detected second fault pulse emitted by the second FCC of Bhalwankar in order for the system to detect and appropriately respond to faults, such that (in the worst-case scenario) an aircraft is able to land safely after an electrical fault has occurred (see at least Bhalwankar, para. [0005]).
Regmi teaches
implementing, by a flight termination system, a landing procedure based on the detected first fault pulse emitted by the first FCC and the detected second fault pulse emitted by the second FCC (see at least Regmi, para. [0042]: The level of fault (i.e. minor, major, cautious, and emergency) can be differentiated by using/reading ("sensing") the parameters of the component/equipment and comparing to their normal range. The normal, caution, danger/emergency range of the parameters could be determined/retrieved from the programmed software and or by built-in electronic circuits and compared to the current condition. If the fault is major and immediate action is necessary, then the built-in system senses and prepares the emergency landing system by transferring or communicating any necessary data or initiating any sequences. For these purposes, the onboard system senses the current aircraft position, type of fault, then enables/disenables the required systems and then implements the system as described in the emergency landing section.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lin to incorporate the teaching of wherein the flight termination system is configured to implement a landing procedure based on the detected first fault pulse and the second detected fault pulse of Regmi in order to provide automated systems for an aircraft that can adapt to emergencies and faults to provide continued safe operation of the aircraft (see at least Regmi, para. [0010]).
Conclusion
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/MOHAMED ABDO ALGEHAIM/Primary Examiner, Art Unit 3668
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