DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. If Applicant fails to provide a sufficiently descriptive title, Examiner will do so upon allowance of the claims.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, “a second gate line extending from a position of a fourth row and the first column to a position of the second row and the second column, and then extending from the position of the second row and the second column to a position of the fourth row and a fourth column” (claim 4) must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 10, 14-17, and 21-24 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kitamura et al. (US 2026/0118727).
Regarding claim 1, Kitamura discloses a display device comprising: a plurality of subpixels (abstract, fig. 1, pixels 130, see ¶ 24-29; see also figs. 3-5, ¶ 33-37);
a plurality of gate lines connected to the plurality of subpixels (figs. 3-5, ¶ 33-37, gate lines 122);
and a plurality of reference voltage lines connected to the plurality of subpixels, wherein the plurality of reference voltage lines include: a reference voltage line electrically connected to first to third subpixels (figs. 3-5, ¶ 33-37, common wiring 126),
and wherein the plurality of gate lines include: a first gate line electrically connected to the first to third subpixels disposed in a diagonal direction (figs. 3-5, ¶ 33-37; see also figs. 11-12, ¶ 51-52, pitch P2 of bending points of the zig-zag structure of the gate line may be an integer multiple of pitch P1, e.g., P2 may be 3 times as large as P1).
Regarding claim 2, Kitamura discloses wherein the first subpixel is located in a third row and a first column, the second subpixel is located in a second row and a second column, and the third subpixel is located in a first row and a third column (figs. 3-5, ¶ 33-37; see also figs. 11-12, ¶ 51-52, pitch P2 of bending points of the zig-zag structure of the gate line may be an integer multiple of pitch P1, e.g., P2 may be 3 times as large as P1).
Regarding claim 3, Kitamura discloses wherein the first gate line is disposed in a zigzag pattern, a tooth of the zigzag pattern extending in a direction from a position of the third row and the first column to a position of the first row and the third column, and then extending from the position of the first row and the third column to a position of the third row and a fourth column (figs. 3-5, ¶ 33-37; see also figs. 11-12, ¶ 51-52, pitch P2 of bending points of the zig-zag structure of the gate line may be an integer multiple of pitch P1, e.g., P2 may be 3 times as large as P1).
Regarding claim 4, Kitamura discloses a second gate line extending from a position of a fourth row and the first column to a position of the second row and the second column, and then extending from the position of the second row and the second column to a position of the fourth row and a fourth column (figs. 3-5, ¶ 33-37, gate lines 122; see also figs. 11-12, ¶ 51-52, pitch P2 of bending points of the zig-zag structure of the gate line may be an integer multiple of pitch P1, e.g., P2 may be 3 times as large as P1).
Regarding claim 5, Kitamura discloses a fifth subpixel electrically connected to the second gate line and located in the fourth row and the first column; a sixth subpixel electrically connected to the second gate line and located in the third row and the second column; and a seventh subpixel electrically connected to the second gate line and located in the second row and the third column (fig. 1, pixels 130, see ¶ 24-29; see also figs. 3-5, ¶ 33-37; see also figs. 11-12, ¶ 51-52, pitch P2 of bending points of the zig-zag structure of the gate line may be an integer multiple of pitch P1, e.g., P2 may be 3 times as large as P1).
Regarding claim 10, Kitamura discloses wherein the first subpixel is located in a third row and a first column, the second subpixel is located in a second row and a second column, and the third subpixel is located in a first row and a third column (figs. 3-5, ¶ 33-37; see also figs. 11-12, ¶ 51-52, pitch P2 of bending points of the zig-zag structure of the gate line may be an integer multiple of pitch P1, e.g., P2 may be 3 times as large as P1),
and wherein the display device further comprises: a first data line located in the first column and electrically connected to the first subpixel; a second data line located in the second column and electrically connected to the second subpixel; and a third data line located in the third column and electrically connected to the third subpixel (fig. 1, see ¶ 24-29; see also figs. 3-5, ¶ 33-37, signal lines 124; see also figs. 11-12, ¶ 51-52, pitch P2 of bending points of the zig-zag structure of the gate line may be an integer multiple of pitch P1, e.g., P2 may be 3 times as large as P1).
Regarding claim 14, Kitamura discloses wherein when a turn-on scan signal is supplied through the first gate line, the first subpixel is supplied with a first data voltage through the first data line, and the third subpixel is supplied with a third data voltage through the third data line (fig. 1, see ¶ 24-29, images created via gate signals, image signals, etc.; see also figs. 3-5, ¶ 32-37, signal lines 124; see also figs. 11-12, ¶ 51-52).
Regarding claim 15, Kitamura discloses wherein the first subpixel and the third subpixel are normal subpixels driven when a first image is displayed (fig. 1, see ¶ 24-29, images created via gate signals, image signals, etc.; see also figs. 3-5, ¶ 32-37, signal lines 124; see also figs. 11-12, ¶ 51-52).
Regarding claim 16, Kitamura discloses a display device comprising: a plurality of subpixels arranged in a row direction and a column direction (abstract, fig. 1, pixels 130, see ¶ 24-29; see also figs. 3-5, ¶ 33-37);
a gate line electrically connected to subpixels of the plurality of subpixels arranged in different rows and columns from one another (figs. 3-5, ¶ 33-37, gate lines 122; see also figs. 11-12, ¶ 51-52, zig-zag structure of the gate lines disclosed);
and a reference voltage line electrically connected to subpixels of the plurality of subpixels arranged in a same row (figs. 3-5, ¶ 33-37, common wiring 126).
Regarding claim 17, Kitamura discloses wherein the gate line is disposed in a plurality of zigzag patterns and extends in the row direction (figs. 3-5, ¶ 33-37, gate lines 122; see also figs. 11-12, ¶ 51-52, zig-zag structure of the gate lines disclosed).
Regarding claim 21, this claim is rejected under the same rationale as claims 16 and 17.
Regarding claim 22, this claim is rejected under the same rational as claim 17.
Regarding claim 23, Kitamura discloses wherein the plurality of gate lines are parallel with each other (figs. 3-5, ¶ 33-37, gate lines 122; see also figs. 11-12, ¶ 51-52).
Regarding claim 24, this claim is rejected under the same rational as claim 3.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6-9 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kitamura in view of Seo et al. (US 2024/0290246).
Regarding claim 6, Kitamura fails to disclose wherein during an active period, the first gate line and the second gate line are sequentially supplied with a turn-on scan signal, and during a blank period after the active period, one of the first gate line and the second gate line is supplied with the turn-on scan signal.
Seo teaches wherein during an active period, the first gate line and the second gate line are sequentially supplied with a turn-on scan signal (fig. 2, fig. 7, see ¶ 73, ¶ 101-103; see also ¶ 83-84),
and during a blank period after the active period, one of the first gate line and the second gate line is supplied with the turn-on scan signal (fig. 2, figs. 6-7, see ¶ 73, ¶ 101-103; see also ¶ 167-169, ¶ 193-201, real time sensing performed during blank time; see also ¶ 120, ¶ 83-84).
Kitamura and Seo are both directed to active matrix display devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the device of Kitamura with the device of Seo since such a modification provides fast response, better contrast ratio, luminous efficiency, luminance, and viewing angle (Seo, ¶ 4) and provides a real-time sensing process that reflects changes in mobility in real-time (Seo, ¶ 199).
Regarding claim 7, Seo further teaches wherein during the blank period, when the turn-on scan signal is supplied to the first gate line, characteristic value sensing of the first to third subpixels electrically connected to the first gate line is performed (fig. 2, figs. 6-7, see ¶ 73, ¶ 101-103; see also ¶ 167-169, ¶ 193-201, real time sensing performed during blank time; see also ¶ 120).
Regarding claim 8, Seo further teaches wherein during the blank period, the first to third subpixels present a low gray level or black (fig. 2, figs. 6-7, see ¶ 73, ¶ 101-103; see also ¶ 167-169, ¶ 193-201, real time sensing performed during blank time between active times).
Regarding claim 9, Seo further teaches wherein a turn-off scan signal is supplied to the second gate line during the blank period (fig. 2, figs. 6-7, see ¶ 73, ¶ 101-103; see also ¶ 167-182, e.g., SCT off during tracking period, ¶ 193-201, real time sensing performed during blank time; see also ¶ 120).
Regarding claim 20, Kitamura fails to disclose wherein each of the plurality of subpixels comprises: a light emitting element; a driving transistor electrically connected to the light emitting element; a scan transistor electrically connected between a first node, which is a gate node of the driving transistor, and a data line; and a sensing transistor electrically connected between a second node of the driving transistor and a reference voltage line.
Seo teaches wherein each of the plurality of subpixels comprises: a light emitting element (fig. 2, ¶ 88-89, light emitting element ED; see also ¶ 99-106);
a driving transistor electrically connected to the light emitting element (fig. 2, ¶ 88-89, driving transistor DRT; see also ¶ 99-106);
a scan transistor electrically connected between a first node, which is a gate node of the driving transistor, and a data line (fig. 2, ¶ 88-89, scan transistor SCT; see also ¶ 99-106);
and a sensing transistor electrically connected between a second node of the driving transistor and a reference voltage line (fig. 2, ¶ 88-89, sensing transistor SENT; see also ¶ 99-106).
Kitamura and Seo are both directed to active matrix display devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the device of Kitamura with the device of Seo since such a modification provides fast response, better contrast ratio, luminous efficiency, luminance, and viewing angle (Seo, ¶ 4) and provides a real-time sensing process that reflects changes in mobility in real-time (Seo, ¶ 199).
Claims 11-13 and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Kitamura in view of Yanagisawa et al. (US 2024/0414997).
Regarding claim 11, Kitamura discloses wherein when a turn-on scan signal is supplied through the first gate line, the first subpixel is supplied with a data voltage through the first data line (fig. 1, see ¶ 24-29, images created via gate signals, image signals, etc.; see also figs. 3-5, ¶ 32-37, signal lines 124; see also figs. 11-12, ¶ 51-52).
Kitamura fails to disclose the third subpixel is not supplied with a data voltage through the third data line.
Yanagisawa teaches the third subpixel is not supplied with a data voltage through the third data line (fig. 1, ¶ 101-102, pixel electrode of the dummy pixel is not electrically connected to a wiring or a circuit of the display; see ¶ 114-115, see also ¶ 121-129, pixels and dummy pixels arranged in a matrix).
Kitamura and Yanagisawa are both directed to active matrix display devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the device of Kitamura with the device of Yanagisawa since such a modification inhibits the adverse effect of the peripheral region of the pixel portion and allows the formation process of the light-emitting devices to be stably performed (Yanagisawa, ¶ 128) and provides a thin, lightweight, high-contrast, and low-power display apparatus (Yanagisawa, ¶ 4-5).
Regarding claim 12, Kitamura discloses wherein the first subpixel is a normal subpixel driven when a first image is displayed (fig. 1, see ¶ 24-29, images created via gate signals, image signals, etc.; see also figs. 3-5, ¶ 32-37, signal lines 124; see also figs. 11-12, ¶ 51-52).
Yanagisawa further teaches the third subpixel is a dummy subpixel not driven when the first image is displayed (fig. 1, ¶ 101-102, pixel electrode of the dummy pixel is not electrically connected to a wiring or a circuit of the display; see ¶ 114-115, see also ¶ 121-129, pixels and dummy pixels arranged in a matrix).
Regarding claim 13, Kitamura discloses a plurality of first normal subpixel groups arranged in a line in the third row (fig. 1, pixels 130, see ¶ 24-29; see also figs. 3-5, ¶ 33-37).
Yanagisawa further teaches a plurality of first dummy subpixel groups arranged in a line in the first row adjacent to one side of the display panel (fig. 1, ¶ 101-102; see ¶ 114-115, dummy pixel portion 294 outside pixel portion 284; see also ¶ 121-129, pixels and dummy pixels arranged in a matrix);
and a plurality of second dummy subpixel groups arranged in a line in a row adjacent to another side of the display panel opposite to the one side (fig. 1, ¶ 101-102; see ¶ 114-115, dummy pixel portion 294 outside pixel portion 284; see also ¶ 121-129, pixels and dummy pixels arranged in a matrix).
Regarding claim 18, this claim is rejected under the same rational as claim 12.
Kitamura and Yanagisawa are both directed to active matrix display devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the device of Kitamura with the device of Yanagisawa since such a modification inhibits the adverse effect of the peripheral region of the pixel portion and allows the formation process of the light-emitting devices to be stably performed (Yanagisawa, ¶ 128) and provides a thin, lightweight, high-contrast, and low-power display apparatus (Yanagisawa, ¶ 4-5).
Regarding claim 19, Yanagisawa further teaches wherein a first gate line is electrically connected to the plurality of normal subpixels and the plurality of dummy subpixels, and a second gate line is electrically connected to the plurality of normal subpixels (fig. 1, ¶ 101-102; see ¶ 114-115, dummy pixel portion 294 outside pixel portion 284; see also ¶ 121-129, pixels and dummy pixels arranged in a matrix).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: See attached Notice of References Cited.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KEITH L CRAWLEY whose telephone number is (571)270-7616. The examiner can normally be reached Monday - Friday 10-6 ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Temesghen Ghebretinsae can be reached at 571-272-3017. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/KEITH L CRAWLEY/ Primary Examiner, Art Unit 2626
Prosecution Insights