DETAILED ACTION
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1. Application number (checked for accuracy, including series code and serial no.).
2. Group art unit number (copied from most recent Office communication).
3. Filing date.
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5. Title of invention.
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Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in Korea on 11/15/2024. It is noted, however, that applicant has not filed a certified copy of the Korean application as required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 – 5 and 10 – 13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US 2019/0130848).
As to claim 1, Kim discloses a display panel (display panel of fig. 8 and 9) , comprising:
a first power pad (third pad from the left of fig. 9),
a second power pad (second pad from the left of fig. 9), and
a third power pad (first pad from the left of fig. 9) configured to receive a first driving voltage (a driving signal corresponding to a voltage GVSS0 or GVSS2 is applied to the GIPs [0097]);
a first wire (left most wiring in the Link region of fig. 9 connected between GIP lines of fig. 9 and first GIP of fig. 9) connected to the first power pad (third pad from the left of fig. 9);
a second wire (second wiring in the Link region of fig. 9 connected between GIP lines of fig. 9 and second GIP of fig. 9) connected to the second power pad (second pad from the left of fig. 9);
a third wire connected to the third power pad (third wiring in the Link region (not shown) of fig. 9 connected between GIP lines of fig. 9 and third GIP of fig. 9, six GIP lines corresponding to six GIPs [0118]) connected to the first power pad (interconnection line part 32 of fig. 7);
at least one transistor (GIP part 31 corresponds to an element (transistor or capacitor) constituting a stage of the GIP driving circuit, [0093], [0097]) connected to the first wire (left most wiring in the Link region of fig. 9 connected between GIP lines of fig. 9 and first GIP of fig. 9);
at least one transistor (GIP part 31 corresponds to an element (transistor or capacitor) constituting a stage of the GIP driving circuit, [0093], [0097]) connected to the second wire (second wiring in the Link region of fig. 9 connected between GIP lines of fig. 9 and second GIP of fig. 9);
and at least one transistor (GIP part 31 connected to the next GIP line provided on the substrate [0120] and corresponds to an element (transistor or capacitor) constituting a stage of the GIP driving circuit, [0093], [0097]) connected to the third wire (third wiring in the Link region (not shown) of fig. 9 connected between GIP lines of fig. 9 and third GIP of fig. 9, six GIP lines corresponding to six GIPs [0118]), but does not explicitly disclose that
the first wire, the second wire, and the third wire have the same length (as shown in fig. 9, all the wires in the link region between PAD region and Pixel region are the same length).
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As to claim 2 (dependent on 1), Kim discloses the display panel, further comprising:
a plurality of sub-pixel circuits (RGB subpixels of fig. 8), wherein
the at least one transistor (transistor of first GIP 31 of fig. 8) connected to the first wire (left most wiring in the Link region of fig. 9 connected between GIP lines of fig. 9 and first GIP of fig. 9), the at least one transistor (transistor of second GIP 31 of fig. 8) connected to the second wire (second wiring in the Link region of fig. 9 connected between GIP lines of fig. 9 and second GIP of fig. 9), and the at least one transistor (third transistor of GIP 31 of fig. 8) connected to the third wire (third wiring in the Link region (not shown) of fig. 9 connected between GIP lines of fig. 9 and third GIP of fig. 9, six GIP lines corresponding to six GIPs [0118]) are each positioned between adjacent sub-pixel circuits (fig. 8), among the plurality of sub-pixel circuits (31 is positioned between G and R subpixel circuits as shown in figs. 7 and 8), in a first direction of the display panel (in the horizontal direction of figs. 7 and 8).
As to claim 3 (dependent on 2), Kim discloses the display panel, further comprising:
gate wires connected to the sub-pixel circuits (scan line of figs. 7 and 8), and a gate driving circuit (distributed gate driving of fig. 6 comprising GIP part 31 of fig. 7 [0076], [0086 – 0088]) connected to the gate wires and configured to supply an emission signal to the gate wires (at least one stage ST of the GIP driving circuit for driving a gate line (scan line) is distributed and arranged in a plurality of unit pixel regions driven by a gate line (scan line) [0094]), wherein
the gate driving circuit includes the at least one transistor (GIP parts 31 are distributed as shown in fig. 7) connected to the first wire (left most wiring in the Link region of fig. 9 connected between GIP lines of fig. 9 and first GIP of fig. 9), the at least one transistor connected to the second wire (second wiring in the Link region of fig. 9 connected between GIP lines of fig. 9 and second GIP of fig. 9), and the at least one transistor connected to the third wire (third wiring in the Link region (not shown) of fig. 9 connected between GIP lines of fig. 9 and third GIP of fig. 9, six GIP lines corresponding to six GIPs [0118]) (multiple transistor connected to multiple voltage line shown in fig. 6).
As to claim 4 (dependent on 3), Kim discloses the display panel, wherein
the at least one transistor (transistor T5 of fig. 6) connected to the first wire (left most wiring in the Link region of fig. 9 connected between GIP lines of fig. 9 and first GIP of fig. 9) includes a feed transistor having a first electrode (an electrode of T5 of fig. 6) , a gate electrode connected to an output terminal of the emission signal (the gate of transistor T5 connected to an output node of a previous stage [0079]), and a second electrode connected to a first driving voltage wire (wire supplying to GVSS2 of fig. 6 ) configured to receive the first driving voltage (electrode of T5 connected to GVSS2 of fig. 6).
As to claim 5 (dependent on 4), Kim discloses the display panel, wherein
the at least one transistor connected to the first wire (left most wiring in the Link region of fig. 9 connected between GIP lines of fig. 9 and first GIP of fig. 9) is connected to an inverter of the gate driving circuit (inverter 24 comprising transistor T5q of fig. 6).
As to claim 10, Kim discloses a display device, comprising:
a display panel having a pad area including a first power pad (third pad from the left of fig. 9), a second power pad (second pad from the left of fig. 9), and a third power pad (third pad from the left of fig. 9),
a first wire (left most wiring in the Link region of fig. 9 connected between GIP lines of fig. 9 and first GIP of fig. 9) connected to the first power pad (third pad from the left of fig. 9), a second wire (second wiring in the Link region of fig. 9 connected between GIP lines of fig. 9 and second GIP of fig. 9) connected to the second power pad (second pad from the left of fig. 9), a third wire (third wiring in the Link region (not shown) of fig. 9 connected between GIP lines of fig. 9 and third GIP of fig. 9, six GIP lines corresponding to six GIPs [0118]) connected to the third power pad (third pad from the left of fig. 9),
at least one transistor (GIP part 31 corresponds to an element (transistor or capacitor) constituting a stage of the GIP driving circuit, [0093], [0097]) connected to the first wire (left most wiring in the Link region of fig. 9 connected between GIP lines of fig. 9 and first GIP of fig. 9),
at least one transistor (GIP part 31 corresponds to an element (transistor or capacitor) constituting a stage of the GIP driving circuit, [0093], [0097]) connected to the second wire (second wiring in the Link region of fig. 9 connected between GIP lines of fig. 9 and second GIP of fig. 9), and
at least one transistor (GIP part 31 connected to the next GIP line provided on the substrate [0120] and corresponds to an element (transistor or capacitor) constituting a stage of the GIP driving circuit, [0093], [0097]) connected to the third wire (third wiring in the Link region (not shown) of fig. 9 connected between GIP lines of fig. 9 and third GIP of fig. 9, six GIP lines corresponding to six GIPs [0118]);
and a circuit (CIP driving circuit [0097]) configured to supply a first driving voltage (a driving signal corresponding to a voltage GVSS0 or GVSS2 is applied to the GIPs [0097]) to the first power pad (third pad from the left of fig. 9), the second power pad (second pad from the left of fig. 9), and the third power pad (third pad from the left of fig. 9), wherein
the first wire (left most wiring in the Link region of fig. 9 connected between GIP lines of fig. 9 and first GIP of fig. 9), the second wire (second wiring in the Link region of fig. 9 connected between GIP lines of fig. 9 and second GIP of fig. 9), and the third wire (third wiring in the Link region (not shown) of fig. 9 connected between GIP lines of fig. 9 and third GIP of fig. 9, six GIP lines corresponding to six GIPs [0118]) have the same length (as shown in fig. 9, all the wires in the link region between PAD region and Pixel region are the same length).
As to claim 11 (dependent on 10), Kim discloses the display device, wherein
the display panel further includes a plurality of sub-pixel circuits (RGB subpixels of fig. 8), and wherein
the at least one transistor (transistor of GIP 31 of fig. 8) connected to the first wire (left most wiring in the Link region of fig. 9 connected between GIP lines of fig. 9 and first GIP of fig. 9), the at least one transistor (transistor of second GIP 31 of fig. 8) connected to the second wire (second wiring in the Link region of fig. 9 connected between GIP lines of fig. 9 and second GIP of fig. 9), and the at least one transistor (transistor of GIP 31 further provided [0120]) connected to the third wire (third wiring in the Link region (not shown) of fig. 9 connected between GIP lines of fig. 9 and third GIP of fig. 9, six GIP lines corresponding to six GIPs [0118]) are each positioned between adjacent sub-pixel circuits, among the plurality of sub-pixel circuits (31 is positioned between G and R subpixel circuits as shown in fig. 7), in a first direction of the display panel (in the horizontal direction of fig. 7).
As to claim 12 (dependent on 11), Kim discloses the display device, wherein
the display panel further includes:
gate wires connected to the sub-pixel circuits (scan line of fig. 8);
and a gate driving circuit (distributed gate driving of fig. 6 comprising GIP part 31 of fig. 7 [0076], [0086 – 0088]) connected to the gate wires and configured to supply an emission signal to the gate wires (at least one stage ST of the GIP driving circuit for driving a gate line (scan line) is distributed and arranged in a plurality of unit pixel regions driven by a gate line (scan line) [0097]), and wherein
the gate driving circuit includes the at least one transistor connected to the first wire, the at least one transistor connected to the second wire, and the at least one transistor connected to the third wire (multiple transistor connected to multiple voltage line shown in fig. 6).
As to claim 13 (dependent on 12), Kim discloses the display device, wherein
the at least one transistor connected to the first wire (transistor T5 of fig. 6) includes a feed transistor having a first electrode (an electrode of T5 of fig. 6), a gate electrode connected to an output terminal of the emission signal (the gate of transistor T5 connected to an output node of a previous stage [0079]), and a second electrode connected to a first driving voltage wire configured to receive the first driving voltage (electrode of T5 connected to GVSS2 of fig. 6).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 9 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2019/0164478 hereinafter Kim 478’) in view of Kim et al. (US 2022/0208946 hereinafter Kim 946’).
As to claim 9 (dependent on 1), Kim 478’ discloses the display panel, further comprising:
a plurality of data pads configured to receive a data signal (D-Pads of fig. 9), wherein
each of the first power pad (third pad from the left of fig. 9), the second power pad (second pad from the left of fig. 9), and the third power pad (third pad from the left of fig. 9) is positioned next to data pads (fig. 9).
but does not disclose that the power pads are positioned between adjacent data pads, among the plurality of data pads, in a first direction of the display panel.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kim 478’ and Kim 946’ such that the power pads were positioned between adjacent data pads, among the plurality of data pads, in a first direction of the display panel as disclosed by Kim 946’, with motivation to reduce display bezel (Kim 946’ [009 – 0011]).
As to claim 16 (dependent on 10), Kim discloses the display device, wherein:
the display panel further includes a plurality of data pads configured to receive a data signal (D-Pads of fig. 9), the circuit includes a data driving circuit (data driving circuit [0122]) configured to output the data signal (supplying data voltages to data lines [0112]), and
each of the first power pad (third pad from the left of fig. 9), the second power pad (second pad from the left of fig. 9), and the third power pad (third pad from the left of fig. 9) is positioned next to data pads (fig. 9),
but does not disclose that the power pads are positioned between adjacent data pads, among the plurality of data pads, in a first direction of the display panel.
In the same filed of endeavor, Kim 946’ discloses a display device wherein power pads are positioned between adjacent data pads, among the plurality of data pads, in a first direction of the display panel (as shown in figs. 3 and 6, gate pads GP1/GP2 are positioned between data pads DP1/DP2 in the first direction of the display panel).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kim 478’ and Kim 946’ such that the power pads were positioned between adjacent data pads, among the plurality of data pads, in a first direction of the display panel as disclosed by Kim 946’, with motivation to reduce display bezel (Kim 946’ [009 – 0011]).
Allowable Subject Matter
Claim 6 – 8, 14, 15 and 17 – 19 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
As to claim 6, There Prior Art of record alone or in combination with other art of record fails to disclose the display panel of claim 5, wherein:
the inverter includes a fourth transistor, a fifth transistor, and a sixth transistor, the fourth transistor has a first electrode, a gate electrode, and a second electrode connected to the first driving voltage wire, and the fifth transistor has a first electrode connected to the gate electrode of the fourth transistor, and a gate electrode and a second electrode connected to the first driving voltage wire. (Emphasis Added.)
As to claim 7, There Prior Art of record alone or in combination with other art of record fails to disclose the display panel of claim 4, wherein:
the at least one transistor connected to the third wire includes a first pull-up transistor of the gate driving circuit, the at least one transistor connected to the second wire includes a second pull-up transistor of the gate driving circuit, and each of the first and second pull-up transistors has a first electrode connected to an output terminal from which the emission signal is outputted, a gate electrode connected to a Q node, and a second electrode connected to the first driving voltage wire. (Emphasis Added.)
As to claim 14, There Prior Art of record alone or in combination with other art of record fails to disclose the display device of claim 13, wherein:
the at least one transistor connected to the first wire is connected to an inverter of the gate driving circuit, the inverter includes a fourth transistor, a fifth transistor, and a sixth transistor, the fourth transistor has a first electrode, a gate electrode, and a second electrode connected to the first driving voltage wire, and the fifth transistor has a first electrode connected to the gate electrode of the fourth transistor, and a gate electrode and a second electrode connected to the first driving voltage wire. (Emphasis Added.)
As to claim 15, There Prior Art of record alone or in combination with other art of record fails to disclose the display device of claim 13, wherein:
the at least one transistor connected to the third wire includes a first pull-up transistor of the gate driving circuit, the at least one transistor connected to the second wire includes a second pull-up transistor of the gate driving circuit, and each of the first and second pull-up transistors has a first electrode connected to an output terminal from which the emission signal is outputted, a gate electrode connected to a Q node, and a second electrode connected to the first driving voltage wire. (Emphasis Added.)
As to claim 17, There Prior Art of record alone or in combination with other art of record fails to disclose the display device of claim 16, wherein
the data driving circuit includes:
a first chip-on-film electrically connected to the first power pad;
and a second chip-on-film electrically connected to the second power pad and the third power pad. (Emphasis Added.)
As to claim 18, There Prior Art of record alone or in combination with other art of record fails to disclose the display device of claim 10,
wherein the first power pad is a first dummy pad, the second power pad is a second dummy pad, and the third power pad is a gate pad, wherein the gate pad is configured to transmit a gate signal to a gate driving circuit, the gate driving circuit including a pump part, an inverter part, a first pull-up transistor, and a second pull-up transistor. (Emphasis Added.)
Conclusion
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/DMITRIY BOLOTIN/Primary Examiner, Art Unit 2623
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