DETAILED ACTION
Claims 1-20 are pending.
Priority: Oct. 10, 2024(FP)
Assignee: Samsung
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-8, 10-12, 16, 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Parry et al.(2021/0011538).
As per claim 1, Parry discloses:
A storage device(Parry, [Fig. 1, [0011 – memory subsystem]), comprising:
a plurality of nonvolatile memory devices comprising a first nonvolatile memory device and a second nonvolatile memory device(Parry, [0013 -- The memory components 112A to 112N can include any combination of the different types of non-volatile memory components and/or volatile memory components]);
and a storage controller configured to control the plurality of nonvolatile memory devices,(Parry, [0014 -- The memory system controller 115 (hereinafter referred to as “controller”) can communicate with the memory components 112A to 112N]);
wherein the storage controller is configured to transmit a first command to the first nonvolatile memory device and a second command to the second nonvolatile memory device,(Parry, [0014 -- The memory system controller 115 (hereinafter referred to as “controller”) can communicate with the memory components 112A to 112N to perform operations such as reading data, writing data, or erasing data at the memory components 112A to 112N and other such operations]);
the first nonvolatile memory device is configured to generate, based on receiving the first command, first peak information associated with the first command,(Parry, [0009 -- Operations such as programming, erasing, and reading a memory component, however, are relatively high current operations that create greater demands on the shared power network (peak power operations)], [0017 -- The memory subsystem 110 includes a power manager 113 in each memory component 112 that can manage peak power consumption within the power network. For example, memory components 112A to 112N], [0018 -- In some embodiments, the method 200 is performed by the power manager 113 of FIG. 1], [0026 -- the first power manager 113 can determine if the first memory component 112 has any program, erase, or read commands queued that require a high current state], [0026 -- the first power manager 113 can determine if the first memory component 112 has any program, erase, or read commands queued that require a high current state.]);
the second nonvolatile memory device is configured to generate, based on receiving the second command, second peak information associated with the second command(Parry, [0026 -- the first power manager 113 can determine if the first memory component 112 has any program, erase, or read commands queued that require a high current state.]) and transmit the second peak information to the first nonvolatile memory device,(Parry, [0027 -- during an assigned time slot for the bus 114, the first power manager 113 transmits an indication that the first memory component 112 is in or entering an active current state to the other memory components], [0030 -- during an assigned time slot for the bus 114, the first power manager 113 transmits an indication that the first memory component 112 is in or entering a high current state to the other memory components]);
and the first nonvolatile memory device is configured to queue the first command in a first command queue based on the first peak information and the second peak information(Parry, [0028 -- the first power manager 113 increments a counter for each high current state signal received in the second round of activity state signal communications to determine a current sum of memory components 112 that are in or entering the high current state. In an embodiment in which the current states are represented by more than two values, the first power manager 113 determines a sum of current state values received as activity state signals], [0033 -- a first power manager 113 of a first memory component 112 can receive activity state signals from one or more power managers 113 of other memory components], [0039 -- the first power manager 113 can determine if the first memory component 112 has any queued commands or operations that correspond to a high, moderate, or low current state], [0039 -- the first power manager 113 can determine if the first memory component 112 has any queued commands or operations that correspond to a high, moderate, or low current state… The first power manager 113 additionally estimates a remaining “budget” for activity state values by, e.g., subtracting the sum of current activity state values from a maximum value for the sum of activity state values]), and to determine an execution time point of the first command based on the second peak information(Parry, [0029 -- If the power network has reached the activity threshold, the method 200 proceeds to operation 225 as described above and the memory component 112 delays its high current state operations.], [0038 -- the first power manager 113 can cause the first memory component 112 to enter the inactive state until, e.g., the expiration of time or receipt of a command from the controller 115.]).
As per claim 2, the storage device of Parry as recited in claim 1 is incorporated, in addition, Parry discloses:
The storage device according to claim 1, wherein the first nonvolatile memory device comprises a memory cell array comprising a plurality of memory cells(Parry, [0013 -- Each of the memory components 112A to 112N can include one or more arrays of memory cells ]), and a control logic configured to control an operation of the memory cell array(Parry, [0018 -- The method 200 can be performed by processing logic that can include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method 200 is performed by the power manager]), wherein the control logic is configured to determine whether a peak period associated with the second command has ended based on the second peak information(Parry, [0029 -- At operation 235, the processing device determines if the activity level of the power network is below the activity threshold. For example, the first power manager 113 determines if the power network has not yet reached the threshold number of memory components ], [0039 -- If there is sufficient remaining budget for the selected activity, at operation 335, the processing device transmits the activity state signal value for the selected activity. For example, during an assigned time slot for the bus 114, the first power manager 113 transmits an indication that the first memory component 112 is in or entering a high, moderate, or low current state to the other memory components 112 in the power network.]), and initiate, based on determining that the peak period associated with the second command has ended, execution of the first command for the memory cell array(Parry, [0031 -- The processing device can remain in this high current state for a predetermined period (e.g., based upon time, number of operations, etc.), after which the method 200 returns to operation 205.], [0043 -- At operation 340, the processing device executes one or more operations corresponding to the selected activity. The processing device can remain in this current state for a predetermined period (e.g., based upon time, number of operations, etc.), after which the method 300 returns to operation 305.]).
As per claim 3, the storage device of Parry as recited in claim 1 is incorporated, in addition, Parry discloses:
wherein the second peak information comprises a first signal indicating a peak period associated with the second command(Parry, [0020 -- the activity state signals include a first signal indicating the corresponding memory component 112 is in or entering a high current state]), and a second signal indicating a non-peak period associated with the second command(Parry, [0020 -- and a second signal indicating that the corresponding memory component 112 is in or entering an active current state…the active current state signal represents a low or moderate current state for the corresponding memory component ]).
As per claim 4, the storage device of Parry as recited in claim 1 is incorporated, in addition, Parry discloses:
wherein the plurality of nonvolatile memory devices further comprise a third nonvolatile memory device(Parry, [0013 -- The memory components 112A to 112N can include any combination of the different types of non-volatile memory components and/or volatile memory components]), the storage controller is configured to transmit a third command to the third nonvolatile memory device(Parry, [0014 -- The memory system controller 115 (hereinafter referred to as “controller”) can communicate with the memory components 112A to 112N to perform operations such as reading data, writing data, or erasing data at the memory components]), the third nonvolatile memory device is configured to generate, based on receiving the third command, third peak information associated with the third command(Parry, [0026 -- the first power manager 113 can determine if the first memory component 112 has any program, erase, or read commands queued that require a high current state.]) and transmit the third peak information to the second nonvolatile memory device(Parry, [0019 - At operation 205, the processing device receives activity state signals from memory components 112 in the power network], [0027 -- If the high current state is not needed, at operation 225, the processing device transmits an active current state signal], [0030 -- the first power manager 113 transmits an indication that the first memory component 112 is in or entering a high current state to the other memory components]), the second nonvolatile memory device is configured to queue the second command in a second command queue based on the second peak information and the third peak information(Parry, [0026 -- the first power manager 113 can determine if the first memory component 112 has any program, erase, or read commands queued that require a high current state.], [0039 -- the first power manager 113 can determine if the first memory component 112 has any queued commands or operations that correspond to a high, moderate, or low current state]), determine an execution time point of the second command based on the third peak information(Parry, [0019 -- At operation 205, the processing device receives activity state signals from memory components 112 in the power network. For example, a first power manager 113 of a first memory component 112 can receive activity state signals from one or more power managers 113 of other memory components ], [0030 -- during an assigned time slot for the bus 114, the first power manager 113 transmits an indication that the first memory component 112 is in or entering a high current state to the other memory components]), and transmit queuing period information associated with the execution time point of the second command to the first nonvolatile memory device(Parry, [0027 -- At operation 205, the processing device receives activity state signals from memory components 112 in the power network.]), and the first nonvolatile memory device is configured to queue the first command in the first command queue based on the queuing period information(Parry, [0039 -- The first power manager 113 additionally estimates a remaining “budget” for activity state values by, e.g., subtracting the sum of current activity state values from a maximum value for the sum of activity state values. ]), and determine the execution time point of the first command further based on the queuing period information(Parry, [0030 -- If the power network has not reached the activity threshold, at operation 240, the processing device transmits a high current], [0031 -- the processing device executes one or more high current state operations while in the high current state. The processing device can remain in this high current state for a predetermined period], [0042 -- the first power manager 113 transmits an indication that the first memory component 112 is in or entering a high, moderate, or low current state to the other memory components 112 in the power network.], [0043 -- At operation 340, the processing device executes one or more operations corresponding to the selected activity. The processing device can remain in this current state for a predetermined period ]).
As per claim 5, the storage device of Parry as recited in claim 4 is incorporated, in addition, Parry discloses:
wherein the first nonvolatile memory device is configured to determine whether there is a queued command in the second command queue based on the queuing period information(Parry, [0039 -- he first power manager 113 can determine if the first memory component 112 has any queued commands or operations that correspond to a high, moderate, or low current state.]), determine whether a peak period associated with the second command has ended based on the second peak information(Parry, [0030 -- during an assigned time slot for the bus 114, the first power manager 113 transmits an indication that the first memory component 112 is in or entering a high current state to the other memory components 112 in the power network]), and initiate, based on determining that the queued command is not present in the second command queue and that the peak period associated with the second command has ended(Parry, [0039 -- the first power manager 113 can determine if the first memory component 112 has any queued commands or operations that correspond to a high, moderate, or low current state]), execution of the first command(Parry, [0022 -- Likewise, before entering an inactive state, a memory component 112 can broadcast a status update to other memory components 112 that it will be in an inactive state], [0031 -- At operation 245, the processing device executes one or more high current state operations while in the high current state.], [0043 -- the processing device executes one or more operations corresponding to the selected activity. The processing device can remain in this current state for a predetermined period]).
As per claim 6, the storage device of Parry as recited in claim 4 is incorporated, in addition, Parry discloses:
wherein the third nonvolatile memory device is configured to execute the third command based on receiving the third command(Parry, [0026 -- the first power manager 113 can determine if the first memory component 112 has any program, erase, or read commands queued that require a high current state.], [0031 -- processing device executes one or more high current state operations while in the high current state]).
As per claim 7, the storage device of Parry as recited in claim 1 is incorporated, in addition, Parry discloses:
wherein the plurality of nonvolatile memory devices further comprise a third nonvolatile memory device and a fourth nonvolatile memory device(Parry, [0013 -- The memory components 112A to 112N can include any combination of the different types of non-volatile memory components and/or volatile memory components]), the first nonvolatile memory device and the second nonvolatile memory device belong to a first group(), and the third nonvolatile memory device and the fourth nonvolatile memory device belong to a second group(Parry, [0017 -- memory components 112A to 112N can be a part of a single power network. The power manager 113 can receive and transmit power consumption signals from/to other memory components 112 via the memory component bus 114 and determine a threshold number of memory components 112 permitted to be in a peak power state based upon the dynamic states of other memory components ]), the storage controller is configured to transmit a third command to the third nonvolatile memory device and a fourth command to the fourth nonvolatile memory device(Parry, [0014 -- The memory system controller 115 (hereinafter referred to as “controller”) can communicate with the memory components 112A to 112N to perform operations such as reading data, writing data, or erasing data at the memory components], [0015 -- In general, the controller 115 can receive commands or operations from the host system 120 and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory components 112A to 112N.]), based on receiving the third command, the third nonvolatile memory device is configured to generate third peak information associated with the third command(Parry, [0034 -- In one embodiment, the activity state signals include a plurality of values indicating high, moderate, low, and inactive current states… different values ranging from 1-3, 1-4, 1-5, etc. may represent different current/power needs corresponding to an idle operation, a read operation, a write operation, no internal activity ], [0039 -- At operation 325, if the processing device determines the first memory component 112 has one or more operations to perform that correspond to a low, moderate, or high current state or otherwise is not going to enter an inactive state]), based on receiving the fourth command, the fourth nonvolatile memory device is configured to generate fourth peak information associated with the fourth command(Parry, [0034 -- different values ranging from 1-3, 1-4, 1-5, etc. may represent different current/power needs corresponding to an idle operation, a read operation, a write operation, no internal activity (e.g., beside transferring data out of the component), an erase operation, etc.]) and transmit the fourth peak information to the third nonvolatile memory device(Parry, [0033 -- a first power manager 113 of a first memory component 112 can receive activity state signals from one or more power managers 113 of other memory components]), and the third nonvolatile memory device is configured to queue the third command in a third command queue based on the third peak information and the fourth peak information(Parry, [0036 -- As described below, the power manager 113 uses the summation of the activity state values to determine the ongoing power/current in the network of the other memory components 112 and estimate if there is enough power/current budget available to do pending operations], [0039 -- the first memory component 112 has one or more operations to perform that correspond to a low, moderate, or high current state or otherwise is not going to enter an inactive state, the processing device selects an activity based upon the determined sum of activity state values]), and determine an execution time point of the third command based on the fourth peak information(Parry, [0042 -- If there is sufficient remaining budget for the selected activity, at operation 335, the processing device transmits the activity state signal value for the selected activity.]).
As per claim 8, the storage device of Parry as recited in claim 1 is incorporated, in addition, Parry discloses:
wherein the plurality of nonvolatile memory devices further comprise a third nonvolatile memory device(Parry, [0013 -- The memory components 112A to 112N can include any combination of the different types of non-volatile memory components and/or volatile memory components]), the first nonvolatile memory device is configured to transmit the first peak information to the second nonvolatile memory device and the third nonvolatile memory device(Parry, [0019 -- Each memory component 112, during its assigned time slot, pulls the bus 114 low and transmits its activity state signal to the other memory components]), the second nonvolatile memory device is configured to transmit the second peak information to the third nonvolatile memory device(Parry, [0019 -- a first power manager 113 of a first memory component 112 can receive activity state signals from one or more power managers 113 of other memory components]), the storage controller is configured to transmit a third command to the third nonvolatile memory device(Parry, [0019 -- a first power manager 113 of a first memory component 112 can receive activity state signals from one or more power managers 113 of other memory components]), and based on receiving the third command, the third nonvolatile memory device is configured to generate third peak information associated with the third command(Parry, [0039 -- If the remaining budget is greater than an activity state value for the next operation for the first memory component 112, the first power manager 113 selects the next operation. If the remaining budget will not support the next operation but it will support another queued operation]) and transmit the third peak information to the first nonvolatile memory device and the second nonvolatile memory device(Parry, [0019 -- a first power manager 113 of a first memory component 112 can receive activity state signals from one or more power managers 113 of other memory components 112], [0033 -- In one embodiment, one memory component 112 serves as a bus master and assigns a time slot to each power manager 113 to transmit an activity state signal (e.g., via round robin scheduling or another bus sharing algorithm)]).
As per claim 10, the storage device of Parry as recited in claim 8 is incorporated, in addition, Parry discloses:
wherein the third nonvolatile memory device is configured to execute the third command based on receiving the third command(Parry, [0031 -- At operation 245, the processing device executes one or more high current state operations while in the high current state.], [0043 -- At operation 340, the processing device executes one or more operations corresponding to the selected activity]).
As per claim 11, the storage device of Parry as recited in claim 10 is incorporated, in addition, Parry discloses:
wherein the second nonvolatile memory device is configured to determine whether to queue the second command based on the second peak information, the third peak information, and a predetermined threshold(Parry, [0036 -- As described below, the power manager 113 uses the summation of the activity state values to determine the ongoing power/current in the network of the other memory components 112 and estimate if there is enough power/current budget available to do pending operations], [0039 - For example, the first power manager 113 can determine if the first memory component 112 has any queued commands or operations that correspond to a high, moderate, or low current state. The first power manager 113 additionally estimates a remaining “budget” for activity state values by, e.g., subtracting the sum of current activity state values from a maximum value for the sum of activity state values.]).
As per claim 12, the storage device of Parry as recited in claim 10 is incorporated, in addition, Parry discloses:
wherein the first nonvolatile memory device is configured to determine whether to queue the first command based on the first peak information, the second peak information, the third peak information, and a predetermined threshold(Parry, [0039 -- The first power manager 113 additionally estimates a remaining “budget” for activity state values by, e.g., subtracting the sum of current activity state values from a maximum value for the sum of activity state values. This maximum value represents a total amount of current or power demand that can be placed on the power network at a given time], [0041 -- the first power manager 113 uses the remaining budget to select an activity, the first power manager 113 can determine that none of its queued operations will fit within the remaining budget]).
As per claim 16, the storage device of Parry as recited in claim 1 is incorporated, in addition, Parry discloses:
wherein the first nonvolatile memory device is configured to complete execution of the first command without delay from a time point at which the first command is executed(Parry, [0041 -- the first power manager 113 uses the remaining budget to select an activity, the first power manager 113 can determine that none of its queued operations will fit within the remaining budget], [0043 -- the processing device executes one or more operations corresponding to the selected activity. The processing device can remain in this current state for a predetermined period]).
As per claim 20, Parry discloses:
A method performed by a first nonvolatile memory device(Parry, [0013 -- The memory components 112A to 112N can include any combination of the different types of non-volatile memory components and/or volatile memory components]), the method comprising:
receiving a first command from a storage controller(Parry, [0015 -- host system 120 and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory components], [0038 -- the first power manager 113 can cause the first memory component 112 to enter the inactive state until, e.g., the expiration of time or receipt of a command from the controller]);
based on receiving the first command, generating first peak information associated with the first command(Parry, [0034 -- different values ranging from 1-3, 1-4, 1-5, etc. may represent different current/power needs corresponding to an idle operation, a read operation, a write operation, no internal activity (e.g., beside transferring data out of the component), an erase operation]);
receiving second peak information associated with a second command from a second nonvolatile memory device(Parry, [0034 -- the activity state signals include a plurality of values indicating high, moderate, low, and inactive current states]);
queuing the first command in a first command queue based on the first peak information and the second peak information(Parry, [0039 -- he first power manager 113 can determine if the first memory component 112 has any queued commands or operations that correspond to a high, moderate, or low current state. The first power manager 113 additionally estimates a remaining “budget” for activity state values by, e.g., subtracting the sum of current activity state values from a maximum value for the sum of activity state values]);
and determining an execution time point of the first command based on the second peak information(Parry, [0043 -- At operation 340, the processing device executes one or more operations corresponding to the selected activity. ]).
Claim(s) 18-19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cho et al.(2020/0104062).
As per claim 18, Cho discloses:
A storage device(Cho, Figs 1-2 – memory system), comprising: a plurality of nonvolatile memory devices comprising a first nonvolatile memory device and a second nonvolatile memory device(Cho, [0008 -- In accordance with an embodiment, a memory system may include a plurality of memory devices storing data, a processor generating commands at a request of a host, and a flash interface layer transferring the commands to the plurality of memory devices based on power consumptions of the plurality of memory devices; i.e. flash chips]);
and a storage controller configured to control the plurality of nonvolatile memory devices,(Cho, [0035 -- The controller 1200 may control the storage device 1100 to program data, output the stored data to the controller 1200, or erase the stored data.]);
wherein the storage controller is configured to transmit a second command to the second nonvolatile memory device,(Cho, [Fig. 5; 0068 -- When the command CMD is queued, the command manager 55 may output a queued command CMD#]);
the second nonvolatile memory device is configured to generate, based on receiving the second command(Cho, [0047 -- The controller 1200 may selectively delay a period in which peak power occurs during an operation being performed by the selected memory device through the first to kth token output signals 1TKo to kTKo], [0078 -- When the first to kth memory devices MD1 to MDk perform operations according to first to third commands CMD1 to CMD3]), second peak information associated with the second command and transmit the second peak information to the storage controller,(Cho, [0047 -- The first to kth memory devices MD1 to MDk may inform the controller 1200 through the first to kth token input signals 1TKi to kTKi that a peak power period delayed by the first to kth token output signals 1TKo to kTKo has ended.]);
the storage controller is configured to queue a first command in a command queue based on a predetermined threshold and the second peak information,(Cho, [0067 -- the power manager 54 may calculate a period in which peak power is greater than a limit level based on the power consumption profile data PF_DATA and an input signal IN_SIG, and may output a calculation result C_RES to the token manager], [0068 -- The command manager 55 may receive a command CMD from the CPU 200 of FIG. 4 and change an execution order of the command CMD according to the adjusted power information MDP_IF], [0069 -- token manager 56 may receive the queued command CMD#, may check operating periods during which the peak power of the storage device 1100 is greater than the limit level in response to the calculation result C_RES output from the power manager 54 and the input signal IN_SIG output from the token counter 57, and may delay a corresponding operating period], [0120 -- When a period in which the total peak power of the memory devices is expected to exceed the limit level occurs after the period T2 to T3, the flash interface layer 250 may also delay the peak power operation of some memory devices during the corresponding period of the flash interface layer ]);
and determine a time point for executing the first command by the first nonvolatile memory device based on the second peak information,(Cho, [0057 -- In addition, the flash interface layer 250 may periodically, regularly or constantly monitor peak power of each of the memory devices which are performing operations, may predict a period in which the peak power is greater than a limit level… and may delay the corresponding period for a set or predetermined time to distribute the peak power], [0119 -- At a time T3 when the sum of the peak power operations performed at the same time is reduced to be less than the limit level, the token output signal TKo may be disabled, so that the first peak power operation 1P_OP of the second memory device MD2 coupled to the first channel CH1 may be performed]);
the storage controller is configured to transmit the first command to the first nonvolatile memory device at the time point for executing the first command,(Cho, [0056 -- In addition, the flash interface layer 250 may perform a queueing operation to change the order of commands generated by the CPU 200 according to a status of the storage device 1100, and may sequentially output the queued commands to the storage device], [0057 -- In other words, the flash interface layer 250 may predict a peak power period with respect to each of the commands and transfer commands by selecting memory devices which delay or do not delay the execution of the commands, among the first to kth memory devices MD1 to MDk… the commands may be queued according to the priority of the commands, and execution times of the commands may be controlled according to the peak power period.]);
and the first nonvolatile memory device is configured to generate, based on receiving the first command(Cho, [0074 -- For example, when the first token output signal 1TKo is enabled, the first memory device MD1 may delay a peak power operation while the first token output signal 1TKo remains enabled and may output the first token input signal 1TKi when the first token output signal 1TKo is disabled], [0078 -- The peak power period information PT# may include the start and end time PTs and PTe of the period in which the peak power occurs when a select memory device MD# executes a particular command (CMD1, CMD2, CMD3) related to peak power], [claim 7 -- wherein each of the plurality of memory devices executes the commands corresponding to the peak power operation by generating the internal clock when the token output signal is disabled.], [claim 8 -- wherein each of the plurality of memory devices outputs the token input signal when the commands corresponding to the peak power operation are executed.], [claim 9 -- wherein each of the plurality of memory devices disables the token input signal when execution of the commands corresponding to the peak power operation is completed.]), first peak information associated with the first command and transmit the first peak information to the storage controller(Cho, [0098 -- During the actual operation, the token counter 57 may receive the first to kth token input signals 1TKi to kTKi enabled only during peak power periods from the first to kth memory devices MD1 to MDk, and may output the input signal IN_SIG including information about start and end times of enablement of each of the first to kth token input signals 1TKi to kTK]).
As per claim 19, the storage device of Parry as recited in claim 18 is incorporated, in addition, Cho discloses:
wherein the storage controller(Cho, [0036 -- The controller 1200 may control the storage device 1100 in response to a request of the host]) is configured to determine whether a peak period associated with the second command has ended based on the second peak information(Cho, [0046 -- The token control lines 300 include lines for transferring first to kth token output signals 1TKo to kTKo for delaying some operations and lines for transferring first to kth token input signals 1TKi to kTKi. Each of the token input signals represents an end information signal of a delayed operation, and start and end period], [0098 -- During the actual operation, the token counter 57 may receive the first to kth token input signals 1TKi to kTKi enabled only during peak power periods from the first to kth memory devices MD1 to MDk, and may output the input signal IN_SIG including information about start and end times of enablement of each of the first to kth token input signals 1TKi to kTKi. For example, the token counter 57 may output the input signal IN_SIG with respect to an enabled token input signal]), and, based on determining that the peak period associated with the second command has ended(Cho, [0073 -- the input signal IN_SIG may be transferred to each of the power manager 54 and the token manager 56. In addition, the power manager 54 may calculate a period in which a peak power is greater than a limit level based on the power consumption profile data PF_DATA and the input signal IN_SIG]), control the first nonvolatile memory device to initiate the execution of the first command(Cho, [0046 -- In other words, some operations may be delayed by delaying the execution or transfer of commands to be transferred to the memory device], [0110 -- When the delay period DL ends at the time point P2, the token output signal TKo may be disabled, and the internal clock I_CLK may be re-generated to perform the peak power operation P_OP], [0119 -- At a time T3 when the sum of the peak power operations performed at the same time is reduced to be less than the limit level, the token output signal TKo may be disabled]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Parry et al.(20210011538), and further in view of Hsu et al.(20170139590).
As per claim 9, the storage device of Parry recited in claim 8 is incorporated, in addition, Parry does not explicitly disclose the following, however Hsu discloses:
wherein each of the first nonvolatile memory device, the second nonvolatile memory device, and the third nonvolatile memory device comprises a first data input/output pad(Hsu, [0054 -- in response to a broadcast status command (here, CMD=7D), each of the eight memory dies in the memory system 100 outputs its program status (here, 0 for not programming; 1 for programming) on different input-output pins on an 8-bit I-O bus]) for sharing the first peak information, a second data input/output pad for sharing the second peak information, and a third data input/output pad for sharing the third peak information(Hsu, [0058 -- In the above example, the memory system 100 has 8 memory dies, each providing its status on a single bit of an 8-bit bus]).
Therefore it would have been obvious to a POSITA at the time of filing to incorporate the multi-bit I/O arrangement of Hsu into the system of Parry for the benefit of dynamically reallocatting the available peak current based on which memory dies are active, which determines programming status for each die, then increases the current limit for active dies and reduces it for idle dies(Hsu, 0054, 0058).
Claim(s) 13-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Parry et al.(20210011538), and further in view of Mun et al.(20190138233).
As per claim 13, the storage device of Parry recited in claim 1 is incorporated, in addition, Parry does not explicitly disclose the following, however Li discloses:
wherein the first command and the second command comprise commands for multi-speed operation(Mun, [0106 -- the memory operation manager 224 may variably determine the data operation time, and may generate command signals CMDs different from each other, based on the determined operation time.]).
Therefore it would have been obvious to a POSITA at the time of filing to incorporate the method/controller for controlling memory devices of Mun into the system of Parry for the benefit of, by lengthening or shortening operation times based on how many dies are active, the method/controller can schedule more concurrent operations without violating the power cap (Mun, 0099).
As per claim 14, the storage device of Parry recited in claim 13 is incorporated, in addition, Parry does not explicitly disclose the following, however Mun discloses:
wherein the commands for multi-speed operation comprise read commands(Mun, [0092 -- the data operation request set REQ_SET may include a request to program the first nonvolatile memory die PGM (NVM_1), a request to program the second nonvolatile memory die PGM (NVM_2), and a request to program the third nonvolatile memory die PGM (NVM_3)]).
Therefore it would have been obvious to a POSITA at the time of filing to incorporate the method/controller for controlling memory devices of Mun into the system of Parry for the benefit of, by lengthening or shortening operation times based on how many dies are active, the method/controller can schedule more concurrent operations without violating the power cap (Mun, 0099).
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Parry et al.(20210011538), and further in view of Jeon(20190114099).
As per claim 15, the storage device of Parry recited in claim 1 is incorporated, in addition, Parry does not explicitly disclose the following, however Jeon discloses:
wherein the first nonvolatile memory device comprises a first bank and a second bank(Jeon, [0039 -- the control circuit 120 may include a monitoring logic 121 and a peak control logic 122. The monitoring logic 121 may monitor whether operations of the first to fourth memory planes PL1 to PL4]), and a first control logic and a second control logic configured to control operations of the first bank and the second bank, respectively(Jeon, [0081 -- The first to fourth control logics CL1 to CL4 may respectively correspond to first to fourth memory planes PL1 to PL4 and may respectively control operations of the first to fourth memory planes PL1 to PL4]), the first command comprises a first sub-command to be performed in the first bank and a second sub-command to be performed in the second bank(Jeon, [0109 -- In operation S240, the memory device 100 may monitor an operation of the first memory plane PL1. For example, the monitoring logic 121 of FIG. 1 or the first control logic CL1 of FIG. 9 may determine whether the operation of the first memory plane PL1 corresponds to the peak power interval and may generate a monitoring signal]), the first control logic is configured to generate peak information associated with the first sub-command based on the first sub-command(Jeon, [0084 -- The first control logic CL1 may monitor an operation of the first memory plane PL1 to generate a first monitoring signal MS1]), the second control logic is configured to generate peak information associated with the second sub-command based on the second sub-command and transmit the peak information associated with the second sub-command to the first control logic(Jeon, [0085 -- Likewise, the second control logic CL2 may monitor an operation of the second memory plane PL2 to generate a second monitoring signal MS2 and may provide the generated second monitoring signal MS2 to the first, third, and fourth control logics CL1, CL3, and CL4]), and the first control logic is configured to queue the first sub-command in a sub-command queue based on the peak information associated with the first sub-command and the peak information associated with the second sub-command(Jeon, [0086 -- The first control logic CL1 may determine whether the first memory plane PL1 enters the peak power interval, based on the first monitoring signal MS1]), and determine an execution time point of the first sub-command based on the peak information associated with the second sub-command(Jeon, [0094 -- the first control logic CL1 may suspend the bit line setup operation on the first memory plane PL1 until the bit line setup intervals BLSETUP of the second to fourth memory planes PL2 to PL4 end], [claim 10 -- delay the operation of the first memory plane when an operation of the second memory plane is in a corresponding peak power interval, and allow the operation of the first memory plane to be performed when the operation of the second memory plane is outside the corresponding peak power interval.]).
Therefore it would have been obvious to a POSITA at the time of filing to incorporate the peak controller of Jeon into the system of Parry for the benefit of a device that monitors each memory plane’s activity and detects when one or more planes enter a peak-power interval. If overlap is detected, the control circuit delays or suspends at least one plane so the high-power portions do not coincide. The result is a smoother aggregate power profile while preserving multi-plane operation(Jeon, 0084-0087)
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Parry et al.(20210011538), and further in view of Jung(20160179684).
As per claim 17, the storage device of Parry recited in claim 1 is incorporated, in addition, Parry does not explicitly disclose the following, however Jung discloses:
wherein the first nonvolatile memory device is configured to generate a ready/busy signal indicating a busy state of performing an internal operation or a ready state in which an internal operation is completed(Jung, [0009 -- The memory area 130 outputs a busy signal BUSY, which indicates that an operation is being performed therein, to the memory controller], [0069 -- The memory area 440 may include busy signal generation unit (not Illustrated) to generate the busy signal BUSY. The busy signal generation unit may identify the cache latch of the plurality of page buffers and generate the busy signal BUSY of a ‘high’ level when the cache latch is capable of storing the data DATA. The busy signal generation unit may out the busy signal BUSY to the operation control unit ]), and the first nonvolatile memory device is configured to determine the execution time point of the first command further based on the ready/busy signal(Jung, [0052 -- A memory controller 430 may control the cache operation of the memory area 440 in response to a busy signal BUSY of a ‘high’ level outputted from the memory area]).
Therefore it would have been obvious to a POSITA at the time of filing to incorporate the peak period tracking and command handling technique of Jung into the system of Parry for the benefit of identifies a peak-current window for a cache operation and prevents the next command from triggering a second overlapping spike in the same window, which either latches the next command until the peak window ends, temporarily stops the ongoing operation and services the next command, or changes the internal clock cycle to reduce the overlap(Jung, 0066-0067).
Notes
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kim et al.(20120221880) which involves a system that has an internal clock generator that generates an internal clock in synchronization with a processor clock received from a controller. A memory unit performs a peak current generation operation within a peak current generation period in synchronization with the internal clock. Multiple memory devices generate their respective internal clocks at different times(Kim, 0005-0007).
Ghlam et al.(20140293704) which involves determining whether subsequent memory operation is high-current memory operation by a die of a multi-die memory i.e. multi-die NAND flash memory (100). A suspended-operation mode is automatically entered by the die of the multi-die memory if the subsequent memory operation is the high current memory operation. Operation is resumed by the die of the multi-die memory in response to resume operation event. The high-current memory operation is performed. An indication is output to the multi-die memory of the subsequent high-current memory operation(Ghalam, abstract).
Conclusion
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Arvind Talukdar
Primary Examiner
Art Unit 2132
/ARVIND TALUKDAR/Primary Examiner, Art Unit 2132
