DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 – 8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitations "the capacity" and “the execution”. There is insufficient antecedent basis for these limitations in the claim. Claims 2 – 7 inherit and do not correct this deficiency.
Claim 2 recites the limitation “the other storage controller”. There is insufficient antecedent basis for this limitation in the claim.
Claim 8 recites the limitations "the capacity" and “the execution”. There is insufficient antecedent basis for these limitations in the claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 1, 3, 4, 7 and 8 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Atkisson et al. (US Patent Application 2012/0221774), hereinafter Atkisson ‘774.
Regarding claim 1, Atkisson ‘774 teaches a storage system comprising:
a non-volatile storage device for storing user data (Paragraph 0070, the backing store 118. Paragraph 0071 states the backing store may be non-volatile);
and a plurality of storage controllers for controlling reading from and writing to the storage device (Paragraphs 0072, 0075 and 0080, one or more solid-state storage controllers 104, direct cache module 116 and backing store controller 0120. All are in communication with the backing store),
wherein each of the plurality of storage controllers includes a processor and a memory (The solid-state storage controller is shown in Fig. 2 and paragraph 0122, the dynamic memory array 230, static memory array 232, and solid-state storage media 110a-n; Paragraph 0080, the backing store controller may be integrated/embodied in the same way as the solid-state storage controllers; Paragraph 0080, the direct cache module comprises the solid-state controllers and/or backing store controller),
wherein the storage controller includes a first memory protection scheme in which logs related to the writing and updating of data in the memory (Paragraph 0069, the cache on the storage controller/cache module stores or preserves data in a log; Paragraph 0094, logs are used to track reads and writes to the memory) are generated and stored in a queue (Paragraph 0069 and Paragraph 0373, the append-only writing structure of the cache) and in which logs are extracted from the queue and written to a non-volatile storage medium to protect the data in the memory (Paragraph 0066, data may be destaged from the cache to the backing store), and
wherein, when the data in the memory is to be protected using the first memory protection scheme, the storage controller controls, according to the capacity of the logs stored in the queue (Paragraph 0065 and 0066, the direct cache module manages the contents of the cache based on the finite storage capacity for caching the data for the store), the execution of a first process for storing the logs in the queue (Paragraph 0067, caching write data in the cache; Paragraph 0265, the dirty write pool module managing a dirty write pool) and a second process for extracting the logs from the queue and writing the logs to the storage medium (Paragraph 0066, destaging the data from the cache to the backing store; Paragraph 0266, a destage module managing destaging from the dirty write pool).
Regarding claim 3, Atkisson ‘774 teaches the storage system according to claim 1,
wherein, when the data in the memory is to be protected using the first memory protection scheme, the storage controller cancels the execution of a destage process for writing cache data cached in the memory to the storage device in the first process (The first process being caching write data in the cache) when the capacity of the logs stored in the queue is equal to or greater than a fourth threshold (Paragraph 0267, the direct cache module may guarantee to a user that the cache will store no more than a maximum dirty write pool size. Paragraph 0065, the cache has a finite physical storage. Paragraphs 0271 and 0272, when a write miss occurs, the actual size of the dirty write pool increases. Therefore, if the cache’s dirty write pool size is equal to the finite physical store or the maximum dirty write pool size, and a write miss occurs, the cache size cannot increase any further to accommodate the new write data, i.e. the write to the cache / the first process must be cancelled. The maximum dirty write pool size or maximum finite physical storage are considered the fourth threshold), and executes the destage process when the capacity of the logs stored in the queue is less than the fourth threshold (Paragraph 0271, when a write miss occurs, the data of the write miss is cached).
Regarding claim 4, Atkisson ‘774 teaches the storage system according to claim 3,
wherein, when the data in the memory is to be protected using the first memory protection scheme,
the storage controller executes the second process when the capacity of the logs stored in the queue is equal to or greater than a first threshold which is smaller than the fourth threshold (Paragraph 0293, a target write pool size is the first threshold. The dirty data module will destage dirty data if the target dirty write pool size is less than the actual dirty write pool size, i.e. if the capacity occupied by the actual dirty write pool is greater than the first threshold defined by the target side; Alternatively, paragraph 0275 teaches that the target pool size may be manipulated to remain within a predetermined range of the actual pool size. In this scenario, there exists two thresholds at the two points where the target pool size would leave this predetermined range), and
cancels the execution of the second process when the capacity of the logs stored in the queue is less than the first threshold (Paragraph 0293, if the target pool size is greater than the actual pool size, the dirty data may be retained/relocated instead of destaging it; In the alternative where the first threshold is such that the actual pool size cannot decrease further without leaving the predetermined range from the target pool size, dirty data will not be destaged in order to stay within the range of the target pool size).
Regarding claim 7, Atkisson ‘774 teaches the storage system according to claim 1, wherein the storage medium is the storage device (Paragraph 0066, the data is destaged from the cache to the backing store. The backing store is the storage device).
Regarding claim 8, Atkisson ‘774 teaches a data protection method executed by a storage
system that includes a non-volatile storage device for storing user data (Paragraph 0070, the backing store 118. Paragraph 0071 states the backing store may be non-volatile), and a plurality of storage controllers for controlling reading from and writing to the storage device (Paragraphs 0072, 0075 and 0080, one or more solid-state storage controllers 104, direct cache module 116 and backing store controller 0120. All are in communication with the backing store), each of the plurality of storage controllers including a processor and a memory (The solid-state storage controller is shown in Fig. 2 and paragraph 0122, the dynamic memory array 230, static memory array 232, and solid-state storage media 110a-n; Paragraph 0080, the backing store controller may be integrated/embodied in the same way as the solid-state storage controllers; Paragraph 0080, the direct cache module comprises the solid-state controllers and/or backing store controller), and the storage controller including a first memory protection scheme in which logs related to the writing and updating of data in the memory (Paragraph 0069, the cache on the storage controller/cache module stores or preserves data in a log; Paragraph 0094, logs are used to track reads and writes to the memory) are generated and stored in a queue (Paragraph 0069 and Paragraph 0373, the append-only writing structure of the cache) and in which logs are extracted from the queue and written to a non-volatile storage medium to protect the data in the memory (Paragraph 0066, data may be destaged from the cache to the backing store),
the data protection method including processing in which,
when the data in the memory is to be protected using the first memory protection scheme, the storage controller controls, according to the capacity of the logs stored in the queue (Paragraph 0065 and 0066, the direct cache module manages the contents of the cache based on the finite storage capacity for caching the data for the store), the execution of a first process for storing the logs in the queue (Paragraph 0067, caching write data in the cache; Paragraph 0265, the dirty write pool module managing a dirty write pool) and a second process for extracting the logs from the queue and writing the logs to the storage medium (Paragraph 0066, destaging the data from the cache to the backing store; Paragraph 0266, a destage module managing destaging from the dirty write pool).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Atkisson ‘774 in view of Sicola et al. (US Patent 7,111,189), hereinafter Sicola.
Regarding claim 2, Atkisson ‘774 teaches the storage system according to claim 1.
Atkisson ‘774 does not teach the storage system
wherein the storage controller further includes a second memory protection scheme in which the data in the memory is protected by copying the data in the memory to another memory of the other storage controller corresponding to the storage controller, and
wherein the storage controller switches between using either the first memory protection scheme or the second memory protection scheme according to an operating state of the other storage controller, and protects the data in the memory by using the switched first memory protection scheme or second memory protection scheme.
Sicola teaches a storage system
wherein the storage controller further includes a second memory protection scheme in which the data in the memory is protected by copying the data in the memory to another memory of the other storage controller corresponding to the storage controller (Column 15 lines 35 – 39 and 58 – 61, two controllers are linked with one another. Local cache 203 is backed up to remote cache 213), and
wherein the storage controller switches between using either the first memory protection scheme (Column 15 lines 44 – 48, when the link between caches is down, write operations are directed by the controller to the local array 203 and log unit 1000) or the second memory protection scheme according to an operating state of the other storage controller, and protects the data in the memory by using the switched first memory protection scheme or second memory protection scheme (Column 15 lines 39 – 44, whether the second memory protection scheme is used depends on whether the backup cache is accessible to the local cache).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to include backup caches similar to the ones taught by Sicola in the system of Atkisson ‘774. One would be motivated to do so as it provides desirable disaster tolerance to the memory controllers (Sicola Column 1 lines 17 - 31). There would be a reasonable expectation for success as Atkisson ‘774 already teaches that multiple controllers can be used (Paragraphs 0072, 0075 and 0080).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Atkisson ‘774.
Regarding claim 5, Atkisson ‘774 teaches the storage system according to claim 4,
wherein, when the data in the memory is to be protected using the first memory protection scheme, the storage controller
executes the destage process at a predetermined frequency when the capacity of the logs stored in the queue is less than a second threshold which is greater than the first threshold and less than the fourth threshold (Paragraph 0014, the target dirty write pool size can be increased. The new target dirty write pool size is therefore a new threshold that is greater than the first threshold / previous target write pool size; In the alternative where the first threshold is such that the actual pool size cannot decrease further than a set range from the target pool size, the second threshold will be the other end of the range described in paragraph 0275, where the actual pool size cannot increase further).
Atkisson ‘774 does not explicitly teach to execute the destage process at a frequency lower than the predetermined frequency when the capacity of the logs stored in the queue is equal to or greater than the second threshold (Paragraph 0269 merely states that “a difference between the target dirty write pool size and an actual dirty write pool size may drive the destage rate”. Paragraph 0266 states that the dirty write pool module 606 adjusts the size of the dirty write pool by adjusting the destage rate. Paragraph 0275 states that one of skill in the art will recognize other pool adjustment rules may be used to manage the size of the data pools but does not disclose this particular rule).
However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to decrease the destage rate when the capacity of the logs stored in the queue exceeds the second threshold. It would be clear that if the target pool size increased, the destage rate should be reduced to avoid destaging at an excessive rate, and avoid the pool becoming smaller than the now larger target pool size. One would be motivated to do so because reducing the destage rate allows for the cache to maintain possibly relevant data for longer periods of time without destaging them. Atkisson ‘774 teaches that this is beneficial as incorrectly evicting data can negatively affect performance (Paragraph 0005) and, in certain scenarios, a larger pool can benefit performance based on other factors (Paragraph 0273). Atkisson ‘774 establishes a clear expectation for success in paragraph 0275 by disclosing that one of skill in the art would recognize other pool adjustment rules.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Atkisson ‘774 in view of Atkisson et al. (US Patent Application Publication 2012/0124294), hereinafter Atkisson ‘294.
Regarding claim 6, Atkisson ‘774 teaches the storage system according to claim 4.
Atkisson ‘774 does not teach the storage system
wherein, when the data in the memory is to be protected using the first memory protection scheme, and
when the capacity of the logs stored in the queue is equal to or greater than a third threshold that is greater than the first threshold and less than the fourth threshold, the storage controller increases an execution interval at the time of executing, in the first process, a write process for the writing data related to a write request from a host to the storage device, and
when the capacity of the logs stored in the queue is less than the third threshold, the storage controller does not increase the execution interval at the time of executing the write process.
Atkisson ‘294 teaches a storage system
wherein, when the data in the memory is to be protected using the first memory protection scheme, and
when the capacity of the logs stored in the queue is equal to or greater than a third threshold that is greater than the first threshold and less than the fourth threshold (Paragraph 0059, a target cache write rate may be enforced based on an amount of dirty data in the cache failing to satisfy a dirty data threshold; Paragraph 0275, write requests are serviced at a target rate when an amount of dirty data in the cache exceeds or fails to satisfy a dirty data threshold), the storage controller increases an execution interval at the time of executing, in the first process, a write process for the writing data related to a write request from a host to the storage device (Paragraphs 0274 – 0277, the rate enforcement module quiesces, pauses, or throttles write operations in order to reduce the cache write rate), and
when the capacity of the logs stored in the queue is less than the third threshold, the storage controller does not increase the execution interval at the time of executing the write process (If the target rate is satisfied, there would be no need to perform further throttling).
It would have been obvious to one of ordinary skill in the art to apply the throttling of Atkisson ‘294 to the system of Atkisson ‘774. One would have been motivated to do so because it allows the system to beneficially balance the dirtied data rate and destage rate (Atkisson ‘294 paragraph 0374). The two references are clearly directed to the same cache system or family of cache systems, as they share the first named inventor. Furthermore Atkisson ‘774 indicates a clear expectation of success in paragraph 0275 by disclosing that one of skill in the art would recognize other pool adjustment rules.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
STOW: A Spatially and Temporally Optimized Write Caching Algorithm is a paper detailing a well-known destage algorithm using a four-threshold scheme to determine the destaging rate. US Patent Application Publication 2007/0250660 is a related patent document with the same first author.
Yang et al. (US Patent 6,243,795) teaches a system of backup caches for a storage system. It is not relied upon as a secondary reference regarding claim 2 as it does not elaborate on how state affects the protection scheme.
Other disclosures by Atkisson et al. considered include US Patent Application Publications 2011/0258391 and 2012/0198175.
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/B.P.H./Examiner, Art Unit 2114
/ASHISH THOMAS/Supervisory Patent Examiner, Art Unit 2114
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