DETAILED ACTION
This Office Action is based on application 19/312,298 filed 28 August 2025. Claims 1-20, as originally filed, are currently pending and have been fully considered below.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 28 August 2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
The following claims are objected to due to informalities:
Claim 1: Lack of antecedent basis of the term “the address {of the first page}”.
Claim 18: Lack of antecedent basis of the term “the address {of the first page}”.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 2, 5, 6, 9, 11, 12, 15, 16, 18, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over OTSUKA (US PGPub 2007/0208885) in further view of UNESAKI et al (US PGPub 2012/0072698).
With respect to Claim 1, OTSUKA discloses a data storage device comprising:
a storage medium (Fig 1, Main Memory 140) including a plurality of pages to which addresses are respectively allocated, the plurality of pages including a first page (Abstract);
a memory controller (Fig 9, I/O Access Control Apparatus 300) configured to manage information for each of the plurality of pages;
a first memory device (Fig 9, Partial Information Storage 310; ¶[0156] – “The partial information storage 310 may be constituted as a built-in cache capable of accessing faster than the address information storage 314”) configured to store, under control of the memory controller, a translation caching table including the information for pages, the addresses of which fall within a preset address range among the plurality of pages (¶[0021] – “A memory access control apparatus according to Item 3 or Item 4, further comprising a cache processing unit which loads beforehand a partial translation table which is a part corresponding to a predetermined logical address range in the address translation table, into a cache memory from the address translation table storage, prior to address translation by the address translation unit”); and
a second memory device (Fig 9, Address Information Storage 314; ¶[0156] – “The address information storage 314 may be constituted as part of the main memory 140”) configured to store, under control of the memory controller, a translation table including the information for each of the plurality of pages (¶[0015] – “an address translation table storage which stores an address translation table to translate a logical address into a physical address, wherein the address information is information indicative of the logical address which is a virtual address converted from an address of the memory into a predetermined format”), wherein the memory controller is configured to:
update the information for the first page in the translation caching table when the address of the first page, a status of which has changed, falls within the preset address range (¶[0173] – “Firstly, the address translation unit 306 determines whether or not it is possible to convert the address by a partial translation table refilled in the partial information storage 310, namely whether the address is hit or not (S30). If it is hit (Y of S30), the address translation unit 306 will identify a physical address by referring to said partial translation table (S34)”), and
determine whether to flush the translation caching table to the translation table when the address of the first page, the status of which has changed, does not fall within the preset address range (¶[0164] – “On the other hand, when the address translation could not be executed with the partial translation table stored in the partial information storage 310 by the look-ahead refill, namely at the time of a miss hit, the cache processing unit 308 loads a new partial translation table into the partial information storage 310. Then the address translation unit 306 identifies the physical address by referring to this newly refilled partial translation table. Such a refill of the partial translation table which is executed when a miss hit has occurred is called "look-behind refill"”; ¶[0166] – “The partial translation table which has been look-ahead refilled may be in a state where the partial translation table is locked in the partial information storage 310. The partial translation table being locked will not be removed from the partial information storage 310. Accordingly, it will not be overwritten by the newly refilled partial translation table. On the other hand, the partial translation table which is not locked may possibly be removed from the partial information storage 310 as a result of the new refilling”).
OTSUKA may not explicitly disclose wherein the translation table comprises a valid page table, the translation caching table comprises a valid page caching table, and the information includes valid information.
However, UNESAKI discloses wherein the translation table comprises a valid page table, the translation caching table comprises a valid page caching table, and the information includes valid information (¶[0051] – “The address translation table 13 manages, for each entry, a NAND logical address, a NAND physical address, valid/invalid information …”).
OTSUKA and UNESAKI are analogous art because they are from the same field of endeavor of memory space management. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of OTSUKA and UNESAKI before him or her, to modify the translation tables of OTSUKA to include validity information as taught by UNESAKI. A motivation for doing so would have been to enable to track whether an entry is valid (¶[0052]) which may enable efficient TLBs to change a status bit instead of flushing or rewriting an entire cache structure. Therefore, it would have been obvious to combine OTSUKA and UNESAKI to obtain the invention as specified in the instant claims.
With respect to Claim 11, OTSUKA discloses an operating method of a memory controller (Fig 9, I/O Access Control Apparatus 300) for controlling a storage medium (Fig 1, Main Memory 140) including a plurality of pages, to which addresses are respectively allocated, the plurality of pages including a first page (Abstract), the operating method comprising:
(Fig 9, Partial Information Storage 310; ¶[0156] – “The partial information storage 310 may be constituted as a built-in cache capable of accessing faster than the address information storage 314”), (¶[0173] – “Firstly, the address translation unit 306 determines whether or not it is possible to convert the address by a partial translation table refilled in the partial information storage 310, namely whether the address is hit or not (S30). If it is hit (Y of S30), the address translation unit 306 will identify a physical address by referring to said partial translation table (S34)”); and
(Fig 9, Address Information Storage 314; ¶[0156] – “The address information storage 314 may be constituted as part of the main memory 140”), (¶[0164] – “On the other hand, when the address translation could not be executed with the partial translation table stored in the partial information storage 310 by the look-ahead refill, namely at the time of a miss hit, the cache processing unit 308 loads a new partial translation table into the partial information storage 310. Then the address translation unit 306 identifies the physical address by referring to this newly refilled partial translation table. Such a refill of the partial translation table which is executed when a miss hit has occurred is called "look-behind refill"”; ¶[0166] – “The partial translation table which has been look-ahead refilled may be in a state where the partial translation table is locked in the partial information storage 310. The partial translation table being locked will not be removed from the partial information storage 310. Accordingly, it will not be overwritten by the newly refilled partial translation table. On the other hand, the partial translation table which is not locked may possibly be removed from the partial information storage 310 as a result of the new refilling”).
OTSUKA may not explicitly disclose wherein the translation table comprises a valid page table, the translation caching table comprises a valid page caching table, and the information includes valid information.
However, UNESAKI discloses wherein the translation table comprises a valid page table, the translation caching table comprises a valid page caching table, and the information includes valid information (¶[0051] – “The address translation table 13 manages, for each entry, a NAND logical address, a NAND physical address, valid/invalid information …”).
OTSUKA and UNESAKI are analogous art because they are from the same field of endeavor of memory space management. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of OTSUKA and UNESAKI before him or her, to modify the translation tables of OTSUKA to include validity information as taught by UNESAKI. A motivation for doing so would have been to enable to track whether an entry is valid (¶[0052]) which may enable efficient TLBs to change a status bit instead of flushing or rewriting an entire cache structure. Therefore, it would have been obvious to combine OTSUKA and UNESAKI to obtain the invention as specified in the instant claims.
(Specific to method Claim 11, the crossed out limitations are recited as contingent limitations and the contingencies are not required by the claim. For example, “updating information for the first page …” is contingent on “when an address of the first page, a status of which has changed, falls within a preset address range …”; the contingencies of (1) the address falls within the range, and (2) the status has changed are not required by the claim. Thus, the crossed out actions are not required to be performed by the claim under the broadest reasonable interpretation of the claim. See EXAMINER’S NOTE below)
With respect to Claim 18, OTSUKA discloses a memory controller (Fig 9, I/O Access Control Apparatus 300) for controlling a storage medium (Fig 1, Main Memory 140) including a plurality of pages to which addresses are respectively allocated, the plurality of pages including a first page (Abstract), wherein the memory controller is configured to:
store, in a first memory device (Fig 9, Partial Information Storage 310; ¶[0156] – “The partial information storage 310 may be constituted as a built-in cache capable of accessing faster than the address information storage 314”), a translation caching table including information for pages, the addresses of which fall within a preset address range among the plurality of pages (¶[0021] – “A memory access control apparatus according to Item 3 or Item 4, further comprising a cache processing unit which loads beforehand a partial translation table which is a part corresponding to a predetermined logical address range in the address translation table, into a cache memory from the address translation table storage, prior to address translation by the address translation unit”),
store, in a second memory device (Fig 9, Address Information Storage 314; ¶[0156] – “The address information storage 314 may be constituted as part of the main memory 140”), a translation table including the information for each of the plurality of pages (¶[0015] – “an address translation table storage which stores an address translation table to translate a logical address into a physical address, wherein the address information is information indicative of the logical address which is a virtual address converted from an address of the memory into a predetermined format”), and
based on the preset address range and the address of the first page, a status of which has changed, update status information of the first page, the status information being in the translation caching table (¶[0173] – “Firstly, the address translation unit 306 determines whether or not it is possible to convert the address by a partial translation table refilled in the partial information storage 310, namely whether the address is hit or not (S30). If it is hit (Y of S30), the address translation unit 306 will identify a physical address by referring to said partial translation table (S34)”), or flush the translation caching table to the second memory device (¶[0164] – “On the other hand, when the address translation could not be executed with the partial translation table stored in the partial information storage 310 by the look-ahead refill, namely at the time of a miss hit, the cache processing unit 308 loads a new partial translation table into the partial information storage 310. Then the address translation unit 306 identifies the physical address by referring to this newly refilled partial translation table. Such a refill of the partial translation table which is executed when a miss hit has occurred is called "look-behind refill"”; ¶[0166] – “The partial translation table which has been look-ahead refilled may be in a state where the partial translation table is locked in the partial information storage 310. The partial translation table being locked will not be removed from the partial information storage 310. Accordingly, it will not be overwritten by the newly refilled partial translation table. On the other hand, the partial translation table which is not locked may possibly be removed from the partial information storage 310 as a result of the new refilling”).
OTSUKA may not explicitly disclose wherein the translation table comprises a valid page table, the translation caching table comprises a valid page caching table, and the information includes valid information.
However, UNESAKI discloses wherein the translation table comprises a valid page table, the translation caching table comprises a valid page caching table, and the information includes valid information (¶[0051] – “The address translation table 13 manages, for each entry, a NAND logical address, a NAND physical address, valid/invalid information …”).
OTSUKA and UNESAKI are analogous art because they are from the same field of endeavor of memory space management. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of OTSUKA and UNESAKI before him or her, to modify the translation tables of OTSUKA to include validity information as taught by UNESAKI. A motivation for doing so would have been to enable to track whether an entry is valid (¶[0052]) which may enable efficient TLBs to change a status bit instead of flushing or rewriting an entire cache structure. Therefore, it would have been obvious to combine OTSUKA and UNESAKI to obtain the invention as specified in the instant claims.
With respect to Claims 2 and 12, the combination of OTSUKA and UNESAKI disclose the data storage device/method according to each respective parent claim.
OTSUKA further discloses wherein the memory controller is configured to assign the address of the first page as an index to the updated valid page caching table when no index is assigned to the updated valid page caching table (¶[0164] – “On the other hand, when the address translation could not be executed with the partial translation table stored in the partial information storage 310 by the look-ahead refill, namely at the time of a miss hit, the cache processing unit 308 loads a new partial translation table into the partial information storage 310. Then the address translation unit 306 identifies the physical address by referring to this newly refilled partial translation table. Such a refill of the partial translation table which is executed when a miss hit has occurred is called "look-behind refill").
(Specific to method Claim 12, the additional limitations (beyond the parent claim) of the claim are recited as contingent limitations and the contingencies are not required by the claim. For example, “assign the address of the first page …” is contingent on “when no index is assigned …”; the contingency of no index assignment is not required by the claim. Thus, the actions of the additional limitations are not required to be performed by the claim under the broadest reasonable interpretation of the claim. See EXAMINER’S NOTE below).
With respect to Claims 5 and 15, the combination of OTSUKA and UNESAKI disclose the data storage device/method according to each respective parent claim.
OTSUKA further discloses wherein the memory controller is configured to initialize the translation caching table when the address of the first page does not fall within the preset address range and no index is assigned to the translation caching table (¶[0164] – “On the other hand, when the address translation could not be executed with the partial translation table stored in the partial information storage 310 by the look-ahead refill, namely at the time of a miss hit, the cache processing unit 308 loads a new partial translation table into the partial information storage 310. Then the address translation unit 306 identifies the physical address by referring to this newly refilled partial translation table. Such a refill of the partial translation table which is executed when a miss hit has occurred is called "look-behind refill").
UNESAKI further discloses wherein the translation caching table comprises a valid page caching table (¶[0051] – “The address translation table 13 manages, for each entry, a NAND logical address, a NAND physical address, valid/invalid information …”)
(Specific to method Claim 15, the additional limitations (beyond the parent claim) of the claim are recited as contingent limitations and the contingencies are not required by the claim. For example, “initialize the valid page caching table …” is contingent on “when the address … does not fall within the preset range …”; the contingency of the address not falling within the preset address range is not required by the claim. Thus, the actions of the additional limitations are not required to be performed by the claim under the broadest reasonable interpretation of the claim. See EXAMINER’S NOTE below).
With respect to Claims 6 and 16, the combination of OTSUKA and UNESAKI disclose the data storage device/method according to each respective parent claim.
OTSUKA further discloses wherein the memory controller is configured to update, after initializing the translation caching table, the information for the first page in the translation caching table (¶[0164] – “On the other hand, when the address translation could not be executed with the partial translation table stored in the partial information storage 310 by the look-ahead refill, namely at the time of a miss hit, the cache processing unit 308 loads a new partial translation table into the partial information storage 310. Then the address translation unit 306 identifies the physical address by referring to this newly refilled partial translation table. Such a refill of the partial translation table which is executed when a miss hit has occurred is called "look-behind refill").
UNESAKI further discloses wherein the translation caching table comprises a valid page caching table, and the information includes valid information (¶[0051] – “The address translation table 13 manages, for each entry, a NAND logical address, a NAND physical address, valid/invalid information …”).
(Specific to method Claim 16, the additional limitations (beyond the parent claim) of the claim are recited as contingent limitations and the contingencies are not required by the claim. For example, “update … the valid information for the first page …” is contingent on “initialize the valid page caching table …” that is further contingent on “when the address … does not fall within the preset range …”; the contingency of the address not falling within the preset address range is not required by the claim. Thus, the actions of the additional limitations are not required to be performed by the claim under the broadest reasonable interpretation of the claim. See EXAMINER’S NOTE below).
With respect to Claim 9, the combination of OTSUKA and UNESAKI disclose the data storage device according to claim 1.
OTSUKA further discloses wherein the second memory device is provided inside or outside the memory controller (Fig 9 illustrates Address Information Storage 314 outside I/O Access Control Apparatus 300).
With respect to Claim 19, the combination of OTSUKA and UNESAKI disclose the memory controller according to claim 18.
OTSUKA further discloses wherein the translation caching table is at least a portion of the translation table (¶[0021] – “A memory access control apparatus according to Item 3 or Item 4, further comprising a cache processing unit which loads beforehand a partial translation table which is a part corresponding to a predetermined logical address range in the address translation table, into a cache memory from the address translation table storage, prior to address translation by the address translation unit”).
UNESAKI further discloses wherein the translation table comprises a valid page table, the translation caching table comprises a valid page caching table (¶[0051] – “The address translation table 13 manages, for each entry, a NAND logical address, a NAND physical address, valid/invalid information …”)
Claim(s) 3, 4, 8, 10, 13, 14, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over OTSUKA in further view of UNESAKI and SONG (US PGPub 2020/0341896).
With respect to Claims 3 and 13, the combination of OTSUKA and UNESAKI disclose the data storage device/method according to each respective parent claim.
OTSUKA and UNESAKI may not explicitly disclose wherein the memory controller is configured to: when the address of the first page does not fall within the preset address range and an index is assigned to the valid page caching table, flush the valid page caching table to the valid page table, and initialize the valid page caching table.
However, SONG discloses wherein the memory controller is configured to: when the address of the first page does not fall within the preset address range and an index is assigned to the valid page caching table, flush the valid page caching table to the valid page table, and initialize the valid page caching table (¶[0027-0028] – “After the open block is selected, when the specific stripe page is different from the first stripe page, the memory controller may perform a flush operation of updating the valid page table stored in the first memory based on new write information of at least two respective pages in the first stripe page included in the first cache entry. After performing the flush operation, the memory controller may perform a cache update operation of updating the first cache entry to allow the first cache entry to include new write information of at least two respective pages in the specific stripe page.”).
OTSUKA, UNESAKI, and SONG are analogous art because they are from the same field of endeavor of memory space management. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of OTSUKA, UNESAKI, and SONG before him or her, to modify the eviction procedure of the combination OTSUKA and UNESAKI to include flushing and initializing as taught by SONG. A motivation for doing so would have been to ensure any current validation data is not lost by performing the writeback procedure prior to evicting (or flushing) the cached copy of data. Therefore, it would have been obvious to combine OTSUKA, UNESAKI, and SONG to obtain the invention as specified in the instant claims.
With respect to Claims 4 and 14, the combination of OTSUKA, UNESAKI, and SONG disclose the data storage device/method according to each respective parent claim.
SONG further discloses wherein the memory controller is configured to update, after initializing the valid page caching table, the validity information for the first page in the valid page caching table (Fig 7, Update Cache S720).
With respect to Claims 8 and 20, the combination of OTSUKA, UNESAKI, and SONG disclose the data storage device/controller according to each respective parent claim.
OTSUKA and UNESAKI may not explicitly disclose wherein: the memory controller comprises a processor having a register, and the first memory device is at least a portion of the register.
However, SONG discloses wherein: the memory controller comprises a processor having a register, and the first memory device is at least a portion of the register (¶[0133] – “The read and write circuit 230 described above may include a page buffer circuit or a data register circuit”).
OTSUKA, UNESAKI, and SONG are analogous art because they are from the same field of endeavor of memory space management. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of OTSUKA, UNESAKI, and SONG before him or her, to modify the I/O Access Control Apparatus of the combination OTSUKA and UNESAKI to include a register as taught by SONG. A motivation for doing so would have been to enable the apparatus to perform a data processing or caching function (¶[0133]). Therefore, it would have been obvious to combine OTSUKA, UNESAKI, and SONG to obtain the invention as specified in the instant claims.
With respect to Claim 10, the combination of OTSUKA and UNESAKI disclose the data storage device according to claim 1.
OTSUKA and UNESAKI may not explicitly disclose wherein the second memory device comprises a static random access memory (SRAM) or a dynamic random access memory (DRAM).
However, SONG discloses wherein the second memory device comprises a static random access memory (SRAM) or a dynamic random access memory (DRAM) (¶[0018] – “For instance, the first memory may be a dynamic RAM (DRAM), and the second memory may be a static RAM (SRAM).”).
OTSUKA, UNESAKI, and SONG are analogous art because they are from the same field of endeavor of memory space management. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of OTSUKA, UNESAKI, and SONG before him or her, to modify the address information storage of the combination OTSUKA and UNESAKI to include SRAM or DRAM as taught by SONG. A motivation for doing so would have been an engineering decision to select a known type of storage that meets system performance requirements, especially since the known type has been taught in prior art for teaching storage of similar information. Therefore, it would have been obvious to combine OTSUKA, UNESAKI, and SONG to obtain the invention as specified in the instant claims.
Claim(s) 7 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over OTSUKA in further view of UNESAKI and YANG et al (US PGPub 2008/0183955).
With respect to Claims 7 and 17, the combination of OTSUKA and UNESAKI disclose the data storage device/method according to each respective parent claim.
OTSUKA further discloses wherein the memory controller is configured to: identify an offset within the translation caching table (¶[0131] – “The address in each page is designated by an offset. The address region 170 contains a segment region 174, a page region 176 and an offset region 178. The segment region 174 indicates a segment value that designates a segment, the page region 176 indicates a page value that designates a page, and the offset region 178 indicates an offset value within the page”), and update the validity information for the first page at a location of the translation caching table corresponding to the offset (¶[0138] – “An offset value indicated in the offset region 178 is added to the identified page and then a specific physical address is finally identified. Then the access is executed in accordance with the access attribute information indicated in the access condition column 194.”).
UNESAKI further discloses the translation caching table comprises a valid page caching table (¶[0051] – “The address translation table 13 manages, for each entry, a NAND logical address, a NAND physical address, valid/invalid information …”).
OTSUKA and UNESAKI may not explicitly disclose identify an offset … based on a remainder obtained by dividing the address of the first page by a size of the preset address range.
However, YANG discloses identify an offset … based on a remainder obtained by dividing the address of the first page by a size of the preset address range (Claim 5; ¶[0033] – “The block offset (BO) value can be represented by the following formula: (LBA) % N, which is the remainder by dividing "(LBA)" by "N", wherein "(LBA)" is the amount of logic block addresses and "N" is the amount of the pages in a block”).
OTSUKA, UNESAKI, and YANG are analogous art because they are from the same field of endeavor of memory space management. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of OTSUKA, UNESAKI, and YANG before him or her, to modify the determination of offsets of the combination OTSUKA and UNESAKI to include using the formula as taught by YANG. A motivation for doing so would have been to enable accessing data in a block at a sub-block level. Therefore, it would have been obvious to combine OTSUKA, UNESAKI, and YANG to obtain the invention as specified in the instant claims.
EXAMINER’S NOTE:
The Office further reminds the applicant of MPEP 2111.04(II) with respect to method claims:
The broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met. For example, assume a method claim requires step A if a first condition happens and step B if a second condition happens. If the claimed invention may be practiced without either the first or second condition happening, then neither step A or B is required by the broadest reasonable interpretation of the claim. If the claimed invention requires the first condition to occur, then the broadest reasonable interpretation of the claim requires step A. If the claimed invention requires both the first and second conditions to occur, then the broadest reasonable interpretation of the claim requires both steps A and B.
The broadest reasonable interpretation of a system (or apparatus or product) claim having structure that performs a function, which only needs to occur if a condition precedent is met, requires structure for performing the function should the condition occur. The system claim interpretation differs from a method claim interpretation because the claimed structure must be present in the system regardless of whether the condition is met and the function is actually performed.
See Ex parte Schulhauser, Appeal 2013-007847 (PTAB April 28, 2016) for an analysis of contingent claim limitations in the context of both method claims and system claims. In Schulhauser, both method claims and system claims recited the same contingent step. When analyzing the claimed method as a whole, the PTAB determined that giving the claim its broadest reasonable interpretation, "[i]f the condition for performing a contingent step is not satisfied, the performance recited by the step need not be carried out in order for the claimed method to be performed" (quotation omitted). Schulhauser at 10. When analyzing the claimed system as a whole, the PTAB determined that "[t]he broadest reasonable interpretation of a system claim having structure that performs a function, which only needs to occur if a condition precedent is met, still requires structure for performing the function should the condition occur." Schulhauser at 14. Therefore "[t]he Examiner did not need to present evidence of the obviousness of the [ ] method steps of claim 1 that are not required to be performed under a broadest reasonable interpretation of the claim (e.g., instances in which the electrocardiac signal data is not within the threshold electrocardiac criteria such that the condition precedent for the determining step and the remaining steps of claim 1 has not been met);" however to render the claimed system obvious, the prior art must teach the structure that performs the function of the contingent step along with the other recited claim limitations. Schulhauser at 9, 14.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure teach related validity information tracking in memory systems.
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/ERIC T LOONAN/Primary Examiner, Art Unit 2137
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