Prosecution Insights
Last updated: October 02, 2026
Application No. 19/312,885

CONTEXT-SENSITIVE DEBUG REQUESTS FOR MEMORY ACCESS

Non-Final OA §102§DP
Filed
Aug 28, 2025
Priority
Sep 20, 2017 — continuation of 10/599,555 +3 more
Examiner
DUNCAN, MARC M
Art Unit
Tech Center
Assignee
Texas Instruments Incorporated
OA Round
1 (Non-Final)
87%
Grant Probability
Favorable
1-2
OA Rounds
1y 3m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allowance Rate
757 granted / 868 resolved
+27.2% vs TC avg
Moderate +8% lift
Without
With
+7.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
13 currently pending
Career history
885
Total Applications
across all art units

Statute-Specific Performance

§101
15.9%
-24.1% vs TC avg
§103
29.7%
-10.3% vs TC avg
§102
24.5%
-15.5% vs TC avg
§112
15.6%
-24.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 868 resolved cases

Office Action

§102 §DP
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1, 2, 5, 6, 9-13, 15, 16, 18 and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Williams (7076767). Regarding claim 1: Williams teaches: A system comprising: processing circuitry configurable to execute instructions [Fig 4 – CPU]; a register configurable to store information related to activity of the processing circuitry [col. 6 lines 45-50, col. 10 line 57-col. 11 line 14, inter alia – CPUs operate by storing the current operating information in registers]; and a controller configurable to issue to the processing circuitry a service request that includes one or more fields, each specifying a respective conditional criterion for servicing the service request [col. 2 lines 58-61, col. 9 lines 23-25, 35-40, col. 10 line 57-col. 11 line 35, col. 11 lines 52-56, inter alia - history stack logic includes write mode selection module accessed via a control interface for selecting the write mode. History stack logic sets write mode registers for various modes that are executed when operating information matches required criteria]; wherein the processing circuitry is configurable to determine whether each criterion for servicing the service request is true, and to service the service request when it is determined that each conditional criterion specified in the service request is true [col. 10 line 57-col. 11 line 35, inter alia – when operating information matches the criteria, information is written to history for debugging purposes]. Regarding claim 2: Williams teaches: The system of claim 1, wherein the processing circuitry is configurable to compare each conditional criterion of the service request to the information stored in the register to determine whether each conditional criterion specified in the service request is true [col. 2 lines 58-61, col. 9 lines 23-25, 35-40, col. 10 line 57-col. 11 line 35, col. 11 lines 52-56, col. 12 line 61-col. 13 line 11, inter alia]. Regarding claim 5: Williams teaches: The system of claim 1, wherein the information stored in the register includes one or more of: an identification of an active thread being executed by the processing circuitry; an identification of a process currently being executed by the processing circuitry; an identification of a task currently being performed by the processing circuitry; an identification of a virtual machine currently running; and an identification of a processor mode in which the processing circuitry is currently operating [col. 10 line 57-col. 11 line 35 – function and address information indicates process and/or task being executed in the broadest reasonable interpretation of the terms]. Regarding claim 6: Williams teaches: The system of claim 5, wherein the processing circuitry is configured to update the information stored in the register in real-time [col. 18 lines 2-5 – making real time signals available, thus information is being updated in real time]. Regarding claim 9: Williams teaches: The system of claim 1, wherein the service request includes a debug request [col. 10 line 57-col. 11 line 35, inter alia – information is written to history for debugging purposes]. Regarding claim 10: Williams teaches: The system of claim 1, wherein, when the processing circuitry determines that not each criterion for servicing the service request is true, the processing circuitry is configurable to delay servicing the service request until it is determined that each conditional criterion specified in the service request is true [col. 9 lines 23-25, 37-40, col. 10 line 57-col. 11 line 35, col. 11 lines 52-56, inter alia – request is not serviced until there is a match]. Regarding claims 11-13, 16, 18, and 19: See the teachings above with respect to claims 1, 2, 6, 9, and 10. Williams further teaches a method [col. 2 lines 36-37, inter alia]. Regarding claim 15: Williams teaches: The method of claim 12, wherein the service request includes an address in a memory, and the servicing of the service request includes accessing the memory at the address specified by the service request [col. 9 lines 23-25, 37-40, col. 10 line 57-col. 11 line 35, inter alia]. Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claims 1-3, 5, 9 and 10 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 2, and 4 of U.S. Patent No. 12423215. Although the claims at issue are not identical, they are not patentably distinct from each other because the ‘215 claims contain all teachings of the instant claims and thus anticipate the instant claims. Instant claim 1: ‘215 claim 1: Explanation as needed: A system comprising: A device comprising: A device or a system are broad terms that impart no significant structural limitations. A device meets the BRI of a system processing circuitry configurable to execute instructions; a processor core including processing circuitry configured to execute code that includes a set of functions a register configurable to store information related to activity of the processing circuitry; a register configured to store an identifier of a first function of the set of functions in response to the processing circuitry executing the first function An identified of a function executed is information related to processing activity and a controller configurable to issue to the processing circuitry a service request that includes one or more fields, each specifying a respective conditional criterion for servicing the service request; a controller configured to issue to the processor core a debug request that includes a first field of one or more bits that specify the identifier of the first function and a second field of one or more bits that specify whether the first field is enabled; The identifier is a value to be matched to the register information in order to determine whether or not to service the request, thus it is a conditional criterion wherein the processing circuitry is configurable to determine whether each criterion for servicing the service request is true, and to service the service request when it is determined that each conditional criterion specified in the service request is true. wherein the processor core is configured to service the debug request based on the identifier being stored in the register and whether the first field is enabled. The request is serviced if the register stores the identifier, in which case the condition is true Claims 11-13, 15-17 and 19 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 2, 4, and 5 of U.S. Patent No. 12423215. Although the claims at issue are not identical, they are not patentably distinct from each other because the ‘215 claims contain all teachings of the instant claims except for teaching a method. The examiner takes official notice that methods of using devices were well-known and widely used in the art prior to the effective filing date. One of ordinary skill in the art prior to the effective filing date would have been motivated to combine a method of using a device with the device of the ‘215 patent because using the device for its intended purpose allows the benefits of said device to be realized. Claims 1-3, 5, 9-13, 15, 16, and 19 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 2, 5, 6, 10, 11, and 15 of U.S. Patent No. 11789848. Although the claims at issue are not identical, they are not patentably distinct from each other because the ‘848 claims contain all teachings of the instant claims and thus anticipate the instant claims. Instant claim 1: ‘848 claim 1: Explanation as needed: A system comprising: A device comprising A device is a system processing circuitry configurable to execute instructions; a processor core; the processor core is configured to: execute code a register configurable to store information related to activity of the processing circuitry; the processor core includes a debug context register; store the identifier of the first function in the debug context register Debug context register stores an identifier of a function being executed, which is activity information and a controller configurable to issue to the processing circuitry a service request that includes one or more fields, each specifying a respective conditional criterion for servicing the service request; a debug controller configured to provide a debug request that specifies an identifier of a first function; determine whether to delay or service the debug request based on whether the identifier of the first function is stored in the debug context register Debug controller provides a request identifying the first function and the first function is a criterion used to determine whether the request is serviced, so it is conditional wherein the processing circuitry is configurable to determine whether each criterion for servicing the service request is true, and to service the service request when it is determined that each conditional criterion specified in the service request is true. determine whether to delay or service the debug request based on whether the identifier of the first function is stored in the debug context register; and in response to the identifier of the first function being stored in the debug context register, service the debug request. The request is serviced based on the identifier matching the contents of the debug context register Claims 1, 2, 4, 5, 9, and 10 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 3, 5, 8, and 9 of U.S. Patent No. 11372745. Although the claims at issue are not identical, they are not patentably distinct from each other because the ‘745 claims contain all teachings of the instant claims and thus anticipate the instant claims. Instant claim 1: ‘745 claim 1: Explanation as needed: A system comprising: A processing device comprising A processing device is a system processing circuitry configurable to execute instructions; A processing device comprising; a processor core Processing devices execute instructions a register configurable to store information related to activity of the processing circuitry; store debug context information in the debug context register Debug context information is processing activity information and a controller configurable to issue to the processing circuitry a service request that includes one or more fields, each specifying a respective conditional criterion for servicing the service request; a debug controller operable to issue a debug request that includes a conditional criteria; compare the conditional criteria of the debug request to the subset of the debug context information by applying the debug context mask to the debug context information to identify the subset of the debug context information; and determine when to service the debug request based on the comparison of the conditional criteria of the debug request to the subset of the debug context information. wherein the processing circuitry is configurable to determine whether each criterion for servicing the service request is true, and to service the service request when it is determined that each conditional criterion specified in the service request is true. compare the conditional criteria of the debug request to the subset of the debug context information by applying the debug context mask to the debug context information to identify the subset of the debug context information; and determine when to service the debug request based on the comparison of the conditional criteria of the debug request to the subset of the debug context information. Request is serviced based on the conditional criteria being satisfied Claims 11-16 and 19 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 3, 5, 8, and 9 of U.S. Patent No. 11372745. Although the claims at issue are not identical, they are not patentably distinct from each other because the ‘745 claims contain all teachings of the instant claims except for teaching a method. The examiner takes official notice that methods of using devices were well-known and widely used in the art prior to the effective filing date. One of ordinary skill in the art prior to the effective filing date would have been motivated to combine a method of using a device with the device of the ‘745 patent because using the device for its intended purpose allows the benefits of said device to be realized. Claims 1, 2, 4, 5, 7, 9 and 10 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 4, 5, 7, and 8 of U.S. Patent No. 10599555. Although the claims at issue are not identical, they are not patentably distinct from each other because the ‘555 claims contain all teachings of the instant claims and thus anticipate the instant claims. Instant claim 1: ‘555 claim 5: Explanation as needed: A system comprising: A processing device comprising A processing device is a system processing circuitry configurable to execute instructions; processing core Processing cores contain circuitry that executes instructions a register configurable to store information related to activity of the processing circuitry; debug context register A register storing debug context stores processing activity information and a controller configurable to issue to the processing circuitry a service request that includes one or more fields, each specifying a respective conditional criterion for servicing the service request; a debug controller configured to issue a context-sensitive debug request including at least one conditional criteria wherein the processing circuitry is configurable to determine whether each criterion for servicing the service request is true, and to service the service request when it is determined that each conditional criterion specified in the service request is true. a processing core configured to determine whether all of the at least one conditional criteria are true, and service the context-sensitive debug request when all of the at least one conditional criteria are true, Claims 11, 12, 15, 16, and 19 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 5 and 7 of U.S. Patent No. 10599555. Although the claims at issue are not identical, they are not patentably distinct from each other because the ‘555 claims contain all teachings of the instant claims except for teaching a method. The examiner takes official notice that methods of using devices were well-known and widely used in the art prior to the effective filing date. One of ordinary skill in the art prior to the effective filing date would have been motivated to combine a method of using a device with the device of the ‘745 patent because using the device for its intended purpose allows the benefits of said device to be realized. Allowable Subject Matter Claim 8 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARC M DUNCAN whose telephone number is (571)272-3646. The examiner can normally be reached M-F: 730am-9am, 10am-4:30pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Bryce Bonzo can be reached at 571-272-3655. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MARC DUNCAN/Primary Examiner, Art Unit 2113
Read full office action

Prosecution Timeline

Aug 28, 2025
Application Filed
Sep 22, 2026
Non-Final Rejection mailed — §102, §DP (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
87%
Grant Probability
95%
With Interview (+7.6%)
2y 4m (~1y 3m remaining)
Median Time to Grant
Low
PTA Risk
Based on 868 resolved cases by this examiner. Grant probability derived from career allowance rate.

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