DETAILED ACTION
This FINAL action is in response to Application No. 19/313,168 originally filed 08/28/2025. The amendment presented on 08/07/2026 which provides amendments to claims 1, 3, 12, 14, 16 is hereby acknowledged.
Currently Claim(s) 1-17 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-17 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
In regard to the reference of Feng The Office respectfully disagrees. Feng in at least paragraphs [0215-0217] teaches that a POSITA is aware that N-Type and/or P-Type transistors can be utilized in the disclosed circuits. Accordingly, depending upon the chosen transistor, A POSITA in view of Feng (and as is well-known in the art) is aware that a corresponding gate line connected to the appropriate signal line for turning off and/or on the transistor is required. Therefore, because Feng teaches that either an N-Type and/or P-Type transistor can be selectively used within the disclosed circuits, Feng is considered to expressly teach the reset circuit transistor arrangement and connections as claimed. The rejection in view of Feng will be maintained.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Feng et al. U.S. Patent Application Publication No. 2024/0371328 A1 hereinafter Feng in view of Park et al. U.S. Patent Application Publication No. 2019/0347997 A1 hereinafter Park in view of Oh et al. U.S. Patent Application Publication No. 2024/0386838 A1 hereinafter Oh.
Consider Claim 1:
Feng discloses a display apparatus, comprising: (Feng, See Abstract.)
a display panel including a pixel; a light emitting diode and a plurality of transistors electrically connected to the light emitting diode, in the pixel; and a gate driving circuit including a stage configured to output a gate signal to one of the plurality of transistors, wherein the stage includes: (Feng, [0381], “In the embodiments of the present disclosure, the first driving output circuit 5 and the second driving output circuit 9 may be used to provide corresponding driving signals for two gate lines G2 and G1 configured for one row of pixel units in the display panel, respectively. Meanwhile, the third driving output circuit 25 and the fourth driving output circuit 29 may be used to provide corresponding driving signals for two gate lines G2 and G1 configured for another row of pixel units in the display panel, respectively. That is, the shift register unit provided by the embodiments may be used to drive four gate lines configured for two rows of pixel units (for example, two adjacent rows of pixel units). With such design, the number of stages of shift register units in a gate driving circuit can be effectively reduced, a region occupied by the gate driving circuit can be reduced, and the narrow frame design of the product can be facilitated.”)
a pull-up transistor and a pull-down transistor, a gate electrode of the pull-up transistor and a gate electrode of the pull-down transistor respectively connected to a Q node and a QB node; (Feng, [0273], “In some embodiments, the first global reset circuit 6 includes a seventh transistor M7, the first display input circuit 7 includes a ninth transistor M9, the first display reset circuit 8 includes a tenth transistor M10, the first pull-down control circuit 11 includes a twelfth transistor M12 and a thirteenth transistor M13, the first pull-up noise reduction circuit 12 includes a fourteenth transistor M14, the first driving output circuit 5 includes a fifth transistor M5 and a seventeenth transistor M17, the second driving output circuit 9 includes a fifteenth transistor M15 and an eighteenth transistor M18, and the first cascade output circuit 13 includes a sixteenth transistor M16 and a nineteenth transistor M19.”)
a reset circuit connected to one of the Q node or the Q2 node, (Feng, [0341], “FIG. 17A is a schematic diagram showing yet another circuit structure of the shift register unit according to the embodiments of the present disclosure, and FIG. 17B is a schematic diagram showing yet another circuit structure of the shift register unit according to the embodiments of the present disclosure. As shown in FIG. 17A and FIG. 17B, as another sensing reset solution, in some embodiments, the first sensing reset circuit 3 includes: a second switch circuit 303 and a third switch circuit 304 connected in series between the first pull-up node PU1 and the second power supply terminal, and the second switch circuit 303 is located between the third switch circuit 304 and the first pull-up node PU1.”)
wherein the reset circuit includes an N-type reset transistor configured to receive a gate high voltage at a drain electrode of the reset transistor, and a … auxiliary transistor connected between the N-type reset transistor and the one of the Q node or the Q2 node. (Feng, [0341], “ FIG. 17A is a schematic diagram showing yet another circuit structure of the shift register unit according to the embodiments of the present disclosure, and FIG. 17B is a schematic diagram showing yet another circuit structure of the shift register unit according to the embodiments of the present disclosure. As shown in FIG. 17A and FIG. 17B, as another sensing reset solution, in some embodiments, the first sensing reset circuit 3 includes: a second switch circuit 303 and a third switch circuit 304 connected in series between the first pull-up node PU1 and the second power supply terminal, and the second switch circuit 303 is located between the third switch circuit 304 and the first pull-up node PU1.” See also Fig. 16 item 301.)
Feng additionally teaches that wherein the reset circuit includes an N-type reset transistor configured to receive a gate high voltage at a drain electrode of the reset transistor (Feng, Fig. 16 Item 301 and H) and Feng also teaches “thin film transistors adopted in the embodiments of the present disclosure may be N-type transistors or P-type transistors.” [0215] and “For an N-type transistor, a high level signal is an active level signal, and a low level signal is an inactive level signal; and for a P-type transistor, a low level signal is an active level signal, and a high level signal is an inactive level signal.”. Therefore, Feng teaches wherein the reset circuit includes an N-type reset transistor configured to receive a gate high voltage, and a P-type auxiliary transistor connected between the N-type reset transistor and the one of the Q node or the Q2 node. (Feng, [0215-0217], [0341], [0217], “The case where the transistors are N-type transistors is taken as an example for illustration in the following description. In such case, the active level signal refers to a high level signal, and the inactive level signal refers to a low level signal. It should be envisaged that timing of control signals needs to be adjusted accordingly when the P-type transistors are adopted. Specific details are not described herein, but should also fall within the scope of the present disclosure.”))
Therefore, it would have been obvious to those having ordinary skill in the art to select either an n-type or p-type transistor as the general provisions were known to a person of skill in the art in view of Feng and provide an p-type transistor would have yielded the same and predictable results. Additionally, The Office notes that under 35 U.S.C. 103, “Combining two embodiments disclosed adjacent to each other in a prior art patent does not require a leap of inventiveness.” Boston Scientific Scimed, Inc. v. Cordis Corp., 554 F.3d 982, 991 (Fed. Cir. 2009).
Feng however does not specify to provide additionally a transfer transistor connected between the Q node and a Q2 node.
Park however teaches that it was a known technique to those of skill in the art before the effective filing date of the invention to provide a transfer transistor connected between the Q node and a Q2 node. (Park, [0070], “The second stress relieving transistor T11 may be connected between the first reset node NQB1 and the second reset node NQB2. In an exemplary embodiment of the inventive concept, the second stress relieving transistor T11 may include a gate receiving the gate on voltage VGL, a first terminal connected to the first reset node NQB1, and a second terminal connected to the second reset node NQB2. Further, in an exemplary embodiment of the inventive concept, the second stress relieving transistor T11 may be (e.g., always) turned on in response to the gate on voltage VGL (or the low gate voltage VGL) having the low level while the scan driver is powered on.”)
It therefore would have been obvious to those having ordinary skill in the art before the effective filing date of the invention to provide to provide a “transfer transistor” provide between a first and second node as this was a known technique in view of Park and would have been readily recognized to a person of skill in the art that such a transistor disposed in the line may allow an absolute value of a voltage of the first node to be lower than an absolute value of the voltage of the second node. (Park, [0070-0071])
Feng and Park however do not additionally discuss wherein the N-type reset transistor includes an oxide semiconductor layer, the P-type auxiliary transistor includes a polycrystalline silicon layer, and the oxide semiconductor layer and the polycrystalline silicon layer are on different levels from one another.
Oh however teaches that it was a known technique to those in the art to provide nmos and pmos on different layers and therefore teaches wherein the N-type reset transistor includes an oxide semiconductor layer, the P-type auxiliary transistor includes a polycrystalline silicon layer, and the oxide semiconductor layer and the polycrystalline silicon layer are on different levels from one another. (Oh, [0084], “A third source/drain region SD3, the second active region ACT2 and a fourth source/drain region SD4 of the NMOS transistor NT may be formed on the first inter-insulating layer ILD1. The second active region ACT2 of the NMOS transistor NT may include or consist of a material different from the material of the first active region ACT1 of the PMOS transistor PT. In an embodiment, the second active region ACT2 of the NMOS transistor NT may include or consist of an oxide semiconductor, an organic semiconductor, amorphous silicon, etc., for example. That is, in some embodiments, the first active region ACT1 of the PMOS transistor PT may include polycrystalline silicon, and the second active region ACT2 of the NMOS transistor NT may include an oxide semiconductor. In other embodiments, the first active region ACT1 of the PMOS transistor PT may include polycrystalline silicon, and the second active region ACT2 of the NMOS transistor NT may include an organic semiconductor. In still other embodiments, the first active region ACT1 of the PMOS transistor PT may include polycrystalline silicon, and the second active region ACT2 of the NMOS transistor NT may include amorphous silicon. Further, in some embodiments, as illustrated in FIG. 4, the first active region ACT1 of the PMOS transistor PT and the second active region ACT2 of the NMOS transistor NT may be formed in different layers, respectively, disposed at different heights, respectively, from the substrate SUB of the display panel. The third and fourth source/drain regions SD3 and SD4 may be n+ doped regions, and may serve as a source and a drain of the NMOS transistor NT, respectively. A third gate insulating layer GI3 may be formed on the third source/drain region SD3, the second active region ACT2 and the fourth source/drain region SD4. In an embodiment, the third gate insulating layer GI3 may include or consist of silicon nitride, but is not limited thereto. Further, the top gate GAT2 of the NMOS transistor NT may be formed on the third gate insulating layer (or film) GI3, for example. In an embodiment, the top gate GAT2 of the NMOS transistor NT may include or consist of a metal material such as molybdenum or titanium, for example, but is not limited thereto. A second inter-insulating layer ILD2 may be formed on the top gate GAT2 of the NMOS transistor NT. In an embodiment, the second inter-insulating layer (or film) ILD2 may include or consist of silicon oxide or silicon nitride, for example, but is not limited thereto.”)
It therefore would have been obvious to those having ordinary skill in the art before the effective filing date of the invention to provide NMOS and PMOS transistors on different layers using different materials as this was a known technique in view of Oh and would have been utilized for the art recognized purpose of power consumption of the driver and a display device including the driver may be reduced. (Oh, [0086])
Consider Claim 2:
Feng in view of Park in view of Oh disclose the display apparatus of claim 1, wherein the reset transistor includes an oxide semiconductor, and a gate electrode of the reset transistor is configured to receive a reset signal. (Oh, [0084], Feng, [0215-0217], [0341], [0321], “The first sensing reset circuit 3 is connected to a sensing reset signal input terminal S-RST, the sensing control node H, the first pull-up node PU1, and the second power supply terminal, and is configured to write an inactive level signal provided by the second power supply terminal to the first pull-up node in response to control of a signal provided by the sensing reset signal input terminal S-RST and an active level signal at the sensing control node H.”)
Therefore, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of design choice. that a mere reversal of the working parts of the essential working parts of a device involves only routine skill in the art. In re Leshin, 125 USPQ 146.
Consider Claim 3:
Feng in view of Park in view of Oh disclose the display apparatus of claim 1, wherein the auxiliary transistor includes polycrystalline silicon. (Oh, [0084], Feng, [0215-0217], [0341], [0321], “The first sensing reset circuit 3 is connected to a sensing reset signal input terminal S-RST, the sensing control node H, the first pull-up node PU1, and the second power supply terminal, and is configured to write an inactive level signal provided by the second power supply terminal to the first pull-up node in response to control of a signal provided by the sensing reset signal input terminal S-RST and an active level signal at the sensing control node H.”)
Therefore, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of design choice. that a mere reversal of the working parts of the essential working parts of a device involves only routine skill in the art. In re Leshin, 125 USPQ 146. Additionally, it would have been obvious to those having ordinary skill in the art to select either an n-type or p-type transistor as the general provisions were known to a person of skill in the art in view of Feng and provide an p-type transistor would have yielded the same and predictable results.
Consider Claim 4:
Feng in view of Park in view of Oh disclose the display apparatus of claim 1, wherein the stage further includes a first control transistor that is connected to the Q2 node, configured to receive a carry signal and has a gate electrode configured to receive a gate clock. (Feng, Fig. 19 see items, 1, 2, input2, clka.)
Consider Claim 5:
Feng in view of Park in view of Oh disclose the display apparatus of claim 4, wherein the Q2 node is electrically coupled to the gate clock. (Feng, Fig. 19 see items, 1, 2, input2, clka.)
Consider Claim 6:
Feng in view of Park in view of Oh disclose the display apparatus of claim 1, wherein the stage further includes a P-type second reset transistor that is connected to the QB node and is configured to receive a gate low voltage. (Feng, [0357], “FIG. 19 is a schematic diagram showing yet another circuit structure of the shift register unit according to the embodiments of the present disclosure. As shown in FIG. 19, in some embodiments, in the case where the shift register unit includes the first global reset circuit 6, the first display reset circuit 8, and the first pull-up noise reduction circuit 12, an anti-leakage design may be made for at least one of the first global reset circuit 6, the first display reset circuit 8, and the first pull-up noise reduction circuit 12.” See also Figure 16-17.)
Consider Claim 7:
Feng in view of Park in view of Oh disclose the display apparatus of claim 6, wherein a first reset signal is to be applied to the reset transistor and a second reset signal is to be applied to the second reset transistor are opposite in phase. (Feng, [0313], “FIG. 12 is another timing diagram of the shift register unit shown in FIG. 10. As shown in FIG. 12, in addition to the global reset phase to, the display input phase t1, the display output phase t2, the display reset phase t3, and the sensing output phase t4 shown in FIG. 11, an operating process shown in FIG. 12 further includes a sensing reset phase t5 (corresponding to the phase p3 in FIG. 5) after the sensing output phase t4 and before the global reset phase to of the next frame. Only the sensing reset phase t5 is described in detail below.”)
Consider Claim 8:
Feng in view of Park in view of Oh disclose the display apparatus of claim 1, wherein the pull-up transistor, the pull-down transistor and the transfer transistor are P-type transistors including polycrystalline silicon. (Feng, [0215-0217], [0341], [0217], “The case where the transistors are N-type transistors is taken as an example for illustration in the following description. In such case, the active level signal refers to a high level signal, and the inactive level signal refers to a low level signal. It should be envisaged that timing of control signals needs to be adjusted accordingly when the P-type transistors are adopted. Specific details are not described herein, but should also fall within the scope of the present disclosure.”))
Therefore, it would have been obvious to those having ordinary skill in the art to select either an n-type or p-type transistor as the general provisions were known to a person of skill in the art in view of Feng and provide an p-type transistor would have yielded the same and predictable results.
Consider Claim 9:
Feng in view of Park in view of Oh disclose the display apparatus of claim 4, wherein the stage further includes: a P-type second control transistor having a gate electrode connected to the Q2 node, a source electrode configured to receive a gate high voltage, and a drain electrode connected to the QB node; and a N-type third control transistor having a gate electrode connected to the Q node, a source electrode configured to receive a gate low voltage, and a drain electrode connected to the QB node. (Feng, [0341], “ FIG. 17A is a schematic diagram showing yet another circuit structure of the shift register unit according to the embodiments of the present disclosure, and FIG. 17B is a schematic diagram showing yet another circuit structure of the shift register unit according to the embodiments of the present disclosure. As shown in FIG. 17A and FIG. 17B, as another sensing reset solution, in some embodiments, the first sensing reset circuit 3 includes: a second switch circuit 303 and a third switch circuit 304 connected in series between the first pull-up node PU1 and the second power supply terminal, and the second switch circuit 303 is located between the third switch circuit 304 and the first pull-up node PU1.”)
Therefore, it would have been obvious to those having ordinary skill in the art to select either an n-type or p-type transistor as the general provisions were known to a person of skill in the art in view of Feng and provide an p-type transistor would have yielded the same and predictable results.
Consider Claim 10:
Feng in view of Park in view of Oh disclose the display apparatus of claim 1, wherein the stage further includes a Q capacitor connected between the Q node and a source electrode of the pull-up transistor. (Feng, [0286], “In some embodiments, a second capacitor C2 and a third capacitor C3 are disposed at the first driving signal output terminal OUT2 and the second driving signal output terminal OUT1, respectively.”)
Consider Claim 11:
Feng in view of Park in view of Oh disclose the display apparatus of claim 1, wherein the stage further includes a QB capacitor connected between the QB node and a source electrode of the pull-down transistor. (Feng, [0286], “In some embodiments, a second capacitor C2 and a third capacitor C3 are disposed at the first driving signal output terminal OUT2 and the second driving signal output terminal OUT1, respectively.”)
Claim Rejections - 35 USC § 103
Claim(s) 12-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Feng et al. U.S. Patent Application Publication No. 2024/0371328 A1 in view of Oh et al. U.S. Patent Application Publication No. 2024/0386838 A1.
Consider Claim 12:
Feng discloses a driving circuit, comprising: (Feng, See Abstract.)
a transistor having a source electrode or a drain electrode connected to a node; and (Feng, [0273], “In some embodiments, the first global reset circuit 6 includes a seventh transistor M7, the first display input circuit 7 includes a ninth transistor M9, the first display reset circuit 8 includes a tenth transistor M10, the first pull-down control circuit 11 includes a twelfth transistor M12 and a thirteenth transistor M13, the first pull-up noise reduction circuit 12 includes a fourteenth transistor M14, the first driving output circuit 5 includes a fifth transistor M5 and a seventeenth transistor M17, the second driving output circuit 9 includes a fifteenth transistor M15 and an eighteenth transistor M18, and the first cascade output circuit 13 includes a sixteenth transistor M16 and a nineteenth transistor M19.”)
a reset circuit connected to the node, (Feng, [0341], “FIG. 17A is a schematic diagram showing yet another circuit structure of the shift register unit according to the embodiments of the present disclosure, and FIG. 17B is a schematic diagram showing yet another circuit structure of the shift register unit according to the embodiments of the present disclosure. As shown in FIG. 17A and FIG. 17B, as another sensing reset solution, in some embodiments, the first sensing reset circuit 3 includes: a second switch circuit 303 and a third switch circuit 304 connected in series between the first pull-up node PU1 and the second power supply terminal, and the second switch circuit 303 is located between the third switch circuit 304 and the first pull-up node PU1.”)
wherein the reset circuit includes: an N-type reset transistor configured to receive a gate high voltage; and a … auxiliary transistor connected between the N-type reset transistor and the node. (Feng, [0341], “ FIG. 17A is a schematic diagram showing yet another circuit structure of the shift register unit according to the embodiments of the present disclosure, and FIG. 17B is a schematic diagram showing yet another circuit structure of the shift register unit according to the embodiments of the present disclosure. As shown in FIG. 17A and FIG. 17B, as another sensing reset solution, in some embodiments, the first sensing reset circuit 3 includes: a second switch circuit 303 and a third switch circuit 304 connected in series between the first pull-up node PU1 and the second power supply terminal, and the second switch circuit 303 is located between the third switch circuit 304 and the first pull-up node PU1.” See also Figure 16 item 301)
Feng additionally teaches that “thin film transistors adopted in the embodiments of the present disclosure may be N-type transistors or P-type transistors.” [0215] and “For an N-type transistor, a high level signal is an active level signal, and a low level signal is an inactive level signal; and for a P-type transistor, a low level signal is an active level signal, and a high level signal is an inactive level signal.”. Therefore, Feng teaches wherein the reset circuit includes: an N-type reset transistor configured to receive a gate high voltage at a drain electrode of the reset transistor; and a P-type auxiliary transistor connected between the N-type reset transistor and the node, a gate of the P-type auxiliary transistor configured to receive a continuously applied gate low voltage. (Feng, [0215-0217], [0341], [0217], “The case where the transistors are N-type transistors is taken as an example for illustration in the following description. In such case, the active level signal refers to a high level signal, and the inactive level signal refers to a low level signal. It should be envisaged that timing of control signals needs to be adjusted accordingly when the P-type transistors are adopted. Specific details are not described herein, but should also fall within the scope of the present disclosure.”))
Therefore, it would have been obvious to those having ordinary skill in the art to select either an n-type or p-type transistor as the general provisions were known to a person of skill in the art in view of Feng and provide an p-type transistor would have yielded the same and predictable results. Additionally, The Office notes that under 35 U.S.C. 103, “Combining two embodiments disclosed adjacent to each other in a prior art patent does not require a leap of inventiveness.” Boston Scientific Scimed, Inc. v. Cordis Corp., 554 F.3d 982, 991 (Fed. Cir. 2009).
Feng however does not specifically recite wherein the N-type reset transistor includes an oxide semiconductor layer, the P-type auxiliary transistor includes a polycrystalline silicon layer, and the oxide semiconductor layer and the polycrystalline silicon layer are on different levels from one another.
Oh however teaches that it was a known technique to those in the art to provide nmos and pmos on different layers and therefore teaches wherein the N-type reset transistor includes an oxide semiconductor layer, the P-type auxiliary transistor includes a polycrystalline silicon layer, and the oxide semiconductor layer and the polycrystalline silicon layer are on different levels from one another. (Oh, [0084], “A third source/drain region SD3, the second active region ACT2 and a fourth source/drain region SD4 of the NMOS transistor NT may be formed on the first inter-insulating layer ILD1. The second active region ACT2 of the NMOS transistor NT may include or consist of a material different from the material of the first active region ACT1 of the PMOS transistor PT. In an embodiment, the second active region ACT2 of the NMOS transistor NT may include or consist of an oxide semiconductor, an organic semiconductor, amorphous silicon, etc., for example. That is, in some embodiments, the first active region ACT1 of the PMOS transistor PT may include polycrystalline silicon, and the second active region ACT2 of the NMOS transistor NT may include an oxide semiconductor. In other embodiments, the first active region ACT1 of the PMOS transistor PT may include polycrystalline silicon, and the second active region ACT2 of the NMOS transistor NT may include an organic semiconductor. In still other embodiments, the first active region ACT1 of the PMOS transistor PT may include polycrystalline silicon, and the second active region ACT2 of the NMOS transistor NT may include amorphous silicon. Further, in some embodiments, as illustrated in FIG. 4, the first active region ACT1 of the PMOS transistor PT and the second active region ACT2 of the NMOS transistor NT may be formed in different layers, respectively, disposed at different heights, respectively, from the substrate SUB of the display panel. The third and fourth source/drain regions SD3 and SD4 may be n+ doped regions, and may serve as a source and a drain of the NMOS transistor NT, respectively. A third gate insulating layer GI3 may be formed on the third source/drain region SD3, the second active region ACT2 and the fourth source/drain region SD4. In an embodiment, the third gate insulating layer GI3 may include or consist of silicon nitride, but is not limited thereto. Further, the top gate GAT2 of the NMOS transistor NT may be formed on the third gate insulating layer (or film) GI3, for example. In an embodiment, the top gate GAT2 of the NMOS transistor NT may include or consist of a metal material such as molybdenum or titanium, for example, but is not limited thereto. A second inter-insulating layer ILD2 may be formed on the top gate GAT2 of the NMOS transistor NT. In an embodiment, the second inter-insulating layer (or film) ILD2 may include or consist of silicon oxide or silicon nitride, for example, but is not limited thereto.”)
It therefore would have been obvious to those having ordinary skill in the art before the effective filing date of the invention to provide NMOS and PMOS transistors on different layers using different materials as this was a known technique in view of Oh and would have been utilized for the art recognized purpose of power consumption of the driver and a display device including the driver may be reduced. (Oh, [0086])
Consider Claim 13:
Feng in view of Oh discloses the driving circuit of claim 12, wherein the reset transistor includes an oxide semiconductor, and a gate electrode of the reset transistor is configured to receive a reset signal. (Feng, [0215-0217], [0341], [0321], “The first sensing reset circuit 3 is connected to a sensing reset signal input terminal S-RST, the sensing control node H, the first pull-up node PU1, and the second power supply terminal, and is configured to write an inactive level signal provided by the second power supply terminal to the first pull-up node in response to control of a signal provided by the sensing reset signal input terminal S-RST and an active level signal at the sensing control node H.”)
Therefore, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of design choice. that a mere reversal of the working parts of the essential working parts of a device involves only routine skill in the art. In re Leshin, 125 USPQ 146.
Consider Claim 14:
Feng in view of Oh discloses the driving circuit of claim 12, wherein the auxiliary transistor includes polycrystalline silicon. (Feng, [0215-0217], [0341], [0321], “The first sensing reset circuit 3 is connected to a sensing reset signal input terminal S-RST, the sensing control node H, the first pull-up node PU1, and the second power supply terminal, and is configured to write an inactive level signal provided by the second power supply terminal to the first pull-up node in response to control of a signal provided by the sensing reset signal input terminal S-RST and an active level signal at the sensing control node H.”)
Therefore, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of design choice. that a mere reversal of the working parts of the essential working parts of a device involves only routine skill in the art. In re Leshin, 125 USPQ 146.
Consider Claim 15:
Feng in view of Oh discloses the driving circuit of claim 12, further comprising a control transistor that is connected to the node and has a gate electrode configured to receive a clock signal. (Feng, Fig. 19 see items, 1, 2, input2, clka.)
Consider Claim 16:
Feng discloses a driving circuit, comprising: (Feng, See Abstract.)
an output portion; and a control portion configured to control output operation of the output portion, (Feng, [0341], “FIG. 17A is a schematic diagram showing yet another circuit structure of the shift register unit according to the embodiments of the present disclosure, and FIG. 17B is a schematic diagram showing yet another circuit structure of the shift register unit according to the embodiments of the present disclosure. As shown in FIG. 17A and FIG. 17B, as another sensing reset solution, in some embodiments, the first sensing reset circuit 3 includes: a second switch circuit 303 and a third switch circuit 304 connected in series between the first pull-up node PU1 and the second power supply terminal, and the second switch circuit 303 is located between the third switch circuit 304 and the first pull-up node PU1.”)
wherein the output portion includes a pull-up transistor and a pull-down transistor, a gate electrode of the pull-up transistor and a gate electrode of the pull-down transistor respectively connected to a Q node and a QB node, and
(Feng, [0376], “FIG. 20 is a schematic diagram showing yet another circuit structure of the shift register unit according to the embodiments of the present disclosure. As shown in FIG. 20, in addition to the first display input circuit 7, the second driving output circuit 9, and the first cascade output circuit 13 in the above embodiments, the shift register unit shown in FIG. 20 further includes: a second sensing input circuit 23, a second display input circuit 27, a third driving output circuit 25, and a fourth driving output circuit 29.”)
wherein the control portion includes a reset circuit including an N-type reset transistor configured to receive a gate high voltage, and a … auxiliary transistor connected between the N- type reset transistor and the Q node or a Q2 node, a gate of the P-type auxiliary transistor configured to receive a continuously applied gate low voltage,. (Feng, [0341], “ FIG. 17A is a schematic diagram showing yet another circuit structure of the shift register unit according to the embodiments of the present disclosure, and FIG. 17B is a schematic diagram showing yet another circuit structure of the shift register unit according to the embodiments of the present disclosure. As shown in FIG. 17A and FIG. 17B, as another sensing reset solution, in some embodiments, the first sensing reset circuit 3 includes: a second switch circuit 303 and a third switch circuit 304 connected in series between the first pull-up node PU1 and the second power supply terminal, and the second switch circuit 303 is located between the third switch circuit 304 and the first pull-up node PU1.” See also Figure 16 item 301.)
Feng additionally teaches that “thin film transistors adopted in the embodiments of the present disclosure may be N-type transistors or P-type transistors.” [0215] and “For an N-type transistor, a high level signal is an active level signal, and a low level signal is an inactive level signal; and for a P-type transistor, a low level signal is an active level signal, and a high level signal is an inactive level signal.”. Therefore, Feng teaches wherein the control portion includes a reset circuit including an N-type reset transistor configured to receive a gate high voltage, and a P-type auxiliary transistor connected between the N- type reset transistor and the Q node or a Q2 node. (Feng, [0215-0217], [0341], [0217], “The case where the transistors are N-type transistors is taken as an example for illustration in the following description. In such case, the active level signal refers to a high level signal, and the inactive level signal refers to a low level signal. It should be envisaged that timing of control signals needs to be adjusted accordingly when the P-type transistors are adopted. Specific details are not described herein, but should also fall within the scope of the present disclosure.”))
Therefore, it would have been obvious to those having ordinary skill in the art to select either an n-type or p-type transistor as the general provisions were known to a person of skill in the art in view of Feng and provide an p-type transistor would have yielded the same and predictable results.
Claim Rejections - 35 USC § 103
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Feng et al. U.S. Patent Application Publication No. 2024/0371328 A1 in view of Park et al. U.S. Patent Application Publication No. 2019/0347997 A1 in view of Oh et al. U.S. Patent Application Publication No. 2024/0386838 A1.
Consider Claim 17:
Feng discloses the driving circuit of claim 16, Park however teaches wherein the control portion further includes a transfer transistor connected between the Q node and the Q2 node. (Park, [0070], “The second stress relieving transistor T11 may be connected between the first reset node NQB1 and the second reset node NQB2. In an exemplary embodiment of the inventive concept, the second stress relieving transistor T11 may include a gate receiving the gate on voltage VGL, a first terminal connected to the first reset node NQB1, and a second terminal connected to the second reset node NQB2. Further, in an exemplary embodiment of the inventive concept, the second stress relieving transistor T11 may be (e.g., always) turned on in response to the gate on voltage VGL (or the low gate voltage VGL) having the low level while the scan driver is powered on.”)
It therefore would have been obvious to those having ordinary skill in the art before the effective filing date of the invention to provide to provide a “transfer transistor” provide between a first and second node as this was a known technique in view of Park and would have been readily recognized to a person of skill in the art that such a transistor disposed in the line may allow an absolute value of a voltage of the first node to be lower than an absolute value of the voltage of the second node. (Park, [0070-0071])
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Prior art made of record and not relied upon which is still considered pertinent to applicant's disclosure is cited in a current or previous PTO-892. The prior art cited in a current or previous PTO-892 reads upon the applicants claims in part, in whole and/or gives a general reference to the knowledge and skill of persons having ordinary skill in the art before the effective filing date of the invention. Applicant, when responding to this Office action, should consider not only the cited references applied in the rejection but also any additional references made of record.
In the response to this office action, the Examiner respectfully requests support be shown for any new or amended claims. More precisely, indicate support for any newly added language or amendments by specifying page, line numbers, and/or figure(s). This will assist The Office in compact prosecution of this application. The Office has cited particular columns, paragraphs, and/or line numbers in the applied rejection of the claims above for the convenience of the applicant. Citations are representative of the teachings in the art and are applied to the specific limitations within each claim, however other passages and figures may apply. Applicant, in preparing a response, should fully consider the cited reference(s) in its entirety and not only the cited portions as other sections of the reference may expand on the teachings of the cited portion(s).
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/Michael J Jansen II/ Primary Examiner, Art Unit 2626
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