DETAILED ACTION
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1. Application number (checked for accuracy, including series code and serial no.).
2. Group art unit number (copied from most recent Office communication).
3. Filing date.
4. Name of the examiner who prepared the most recent Office action.
5. Title of invention.
6. Confirmation number (See MPEP § 503).
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 – 7, 18 and 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Youn et al. (US 2022/0181431).
As to claim 1, Youn discloses a display device comprising:
a substrate (SUB of fig. 9);
a first signal line (gate electrode line GE of fig. 9 correspondent to gate line GL of figs. 2 and 3) on the substrate (SUB of fig. 9) and extending in a first direction (horizontal direction of figs. 2 and 3);
an overcoat layer (planarization layer PAC of fig. 9) on the first signal line (gate electrode line GE of fig. 9 correspondent to gate line GL of figs. 2 and 3);
a pixel electrode (PXL of fig. 9) on the overcoat layer (planarization layer PAC of fig. 9), the pixel electrode (PXL of fig. 9) comprising a first electrode material (metal layer M1 [0177]);
a light-emitting layer (EL of fig. 9) on the pixel electrode (PXL of fig. 9);
a common electrode (COM of fig. 9) on the light-emitting layer (EL of fig. 9);
and a plurality of second signal lines (CL of fig. 9, wherein there are plurality of the clock signal lines [0093]) on the overcoat layer (planarization layer PAC of fig. 9), comprising the first electrode material (metal layer M1 [0177]), and extending in a second direction (vertical direction of fig. 3) different from the first direction (horizontal direction of figs. 2 and 3).
As to claim 2 (dependent on 1), Youn discloses the display device, further comprising:
a first lower pattern (capacitor electrode CE of fig. 9) on the substrate (SUB of fig. 9);
and a buffer layer (BUF of fig. 9) on the first lower pattern (capacitor electrode CE of fig. 9), wherein
the first signal line (gate electrode line GE of fig. 9 correspondent to gate line GL of figs. 2 and 3) is on the buffer layer (BUF of fig. 9) and vertically overlaps the first lower pattern (capacitor electrode CE of fig. 9).
As to claim 3 (dependent on 2), Youn discloses the display device, wherein
the first lower pattern (capacitor electrode CE of fig. 9) is in an electrically floating state (as show in figs. 2 and 7, node N2 which corresponds to the capacitor electrode CE of fig. 9 is in floating state when transistors are OFF).
As to claim 4 (dependent on 2), Youn discloses the display device, further comprising:
a first active layer (active layer ACTs of fig. 9) on the buffer layer (BUF of fig. 9) and overlapping the first signal line (gate electrode line GE of fig. 9 correspondent to gate line GL of figs. 2 and 3);
and a first insulating layer (gate insulating layer GI of fig. 9) on the first active layer (active layer ACTs of fig. 9), wherein
the first signal line (gate electrode line GE of fig. 9 correspondent to gate line GL of figs. 2 and 3) is on the first insulating layer (gate insulating layer GI of fig. 9).
As to claim 5 (dependent on 4), Youn discloses the display device, wherein
the first lower pattern (capacitor electrode CE of fig. 9) overlaps the first active layer (active layer ACTs of fig. 9) and transmits a signal that is the same as or different from the signal transmitted through the first signal line (gate electrode line GE of fig. 9 correspondent to gate line GL of figs. 2 and 3).
As to claim 6 (dependent on 1), Youn discloses the display device, wherein
the first signal line (gate electrode line GE of fig. 9 correspondent to gate line GL of figs. 2 and 3) is a single-layer line (fig. 9), and each of the plurality of second signal lines (CL of fig. 9, wherein there are plurality of the clock signal lines [0093]) is a multi-layer line (including a first metal layer M1 and the second metal layer M2 [0161 - 0165]).
As to claim 7 (dependent on 1), Youn discloses the display device, wherein
each of the plurality of second signal lines (CL of fig. 9, wherein there are plurality of the clock signal lines [0093]) comprises:
a lower line including the first electrode material (metal layer M1 [0177]);
and an upper line including a second electrode material (second metal layer M2 [0177]) different from the first electrode material (metal layer M1 [0177]) and electrically connected to the lower line (fig. 9).
As to claim 18, Youn discloses a display device comprising:
a substrate (SUB of fig. 9);
a first signal line (gate electrode line GE of fig. 9 correspondent to gate line GL of figs. 2 and 3) on the substrate (SUB of fig. 9) and extending in a first direction (horizontal direction of figs. 2 and 3);
an overcoat layer (planarization layer PAC of fig. 9) on the first signal line (gate electrode line GE of fig. 9 correspondent to gate line GL of figs. 2 and 3);
a pixel electrode (PXL of fig. 9) of a light-emitting device on the overcoat layer (planarization layer PAC of fig. 9);
and a plurality of second signal lines (CL of fig. 9, wherein there are plurality of the clock signal lines [0093]) on the overcoat layer (planarization layer PAC of fig. 9) and extending in a second direction (vertical direction of fig. 3) different from the first direction (horizontal direction of figs. 2 and 3), wherein
the first signal line (gate electrode line GE of fig. 9 correspondent to gate line GL of figs. 2 and 3) is a single-layer line (fig. 9), and each of the plurality of second signal lines (CL of fig. 9, wherein there are plurality of the clock signal lines [0093]) is a multi-layer line (including a first metal layer M1 and the second metal layer M2 [0161 - 0165]).
As to claim 19, Youn discloses a display device comprising:
a substrate (SUB of fig. 9);
a first signal line (gate electrode line GE of fig. 9 correspondent to gate line GL of figs. 2 and 3) on the substrate (SUB of fig. 9);
an overcoat layer (planarization layer PAC of fig. 9) on the first signal line (gate electrode line GE of fig. 9 correspondent to gate line GL of figs. 2 and 3);
a pixel electrode (PXL of fig. 9) of a light-emitting device on the overcoat layer (planarization layer PAC of fig. 9);
and a second signal line (CL of fig. 9) on the overcoat layer (planarization layer PAC of fig. 9), wherein
the pixel electrode (PXL of fig. 9) and the second signal line (CL of fig. 9) are on a same layer as each other (fig. 9).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 8 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Youn.
As to claim 8 (dependent on 7), Youn discloses the display device but fails to disclose the display device, wherein the upper line includes a low-reflectance material.
However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to try materials with various reflectance for the upper line, with motivation to provide a simple design choice alternative which would have simply required a routine skill.
As to claim 9 (dependent on 1), Youn discloses the display device but fails to disclose the display device, wherein the first electrode material comprises a transparent electrode material.
However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to try materials with various transmittances for the first electrode material, with motivation to provide a simple design choice alternative which would have simply required a routine skill.
Allowable Subject Matter
Claims 10 – 17 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
As to claim 10, Youn alone or in combination with other art of record fails to disclose the display device of claim 1, further comprising a color filter disposed between the substrate and the overcoat layer, and wherein the color filter overlaps the pixel electrode and at least one of the plurality of second signal lines. (Emphasis Added.)
As to claim 11 (dependent on 1), Youn discloses the display device, further comprising:
a driving transistor (DRT of fig. 2) including a first node (N1 of fig. 2), a second node (N2 of fig. 2), and a third node (N3 of fig. 2), wherein the third node (N3 of fig. 2) is electrically connected to a high-potential voltage line (EVDD of fig. 2),
a scan transistor (SWT of fig. 2) that is turned on or off by a first signal transmitted through the first signal line (gate electrode line GE of fig. 9 correspondent to gate line GL of figs. 2 and 3) and controls the electrical connection between a data line (Vdata of fig. 2) and the first node (N1 of fig. 3);
and a sensing transistor (SENT of fig. 2) that is turned on or off by the first signal transmitted from the first signal line (gate electrode line GE of fig. 9 correspondent to gate line GL of figs. 2 and 3) and controls the electrical connection between a reference voltage line (Vref of fig. 2) and the second node (N2 of fig. 2), but fails to disclose alone or in combination with other art of record that
the high-potential voltage line is among the plurality of second signal lines;
the data line is among the plurality of second signal lines;
and the reference voltage line is among the plurality of second signal lines. (Emphasis Added.)
As to claim 17 (dependent on 1), Youn discloses the display device, further comprising:
at least one of a driving transistor (DRT of fig. 2) and a sensing transistor (SENT of fig. 2) including an active layer (ACTs of fig. 9), but fails to disclose alone or in combination with other art of record that
the active layer includes a transparent material that electrically connects to one of the plurality of second signal lines as a branch line. (Emphasis Added.)
As to claim 10, Youn alone or in combination with other art of record fails to disclose the display device of claim 19, further comprising a black bank layer between the substrate and the overcoat layer, wherein the black bank layer at least partially overlaps the first signal line. (Emphasis Added.)
Conclusion
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/DMITRIY BOLOTIN/Primary Examiner, Art Unit 2623
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