Prosecution Insights
Last updated: October 02, 2026
Application No. 19/315,067

HOST ACCELERATED OPERATIONS IN MANAGED NAND DEVICES

Non-Final OA §DP
Filed
Aug 29, 2025
Priority
May 18, 2018 — provisional 62/673,587 +4 more
Examiner
MATIN, TASNIMA
Art Unit
2135
Tech Center
2100 — Computer Architecture & Software
Assignee
Lodestar Licensing Group LLC
OA Round
1 (Non-Final)
90%
Grant Probability
Favorable
1-2
OA Rounds
1y 1m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 90% — above average
90%
Career Allowance Rate
396 granted / 440 resolved
+35.0% vs TC avg
Moderate +8% lift
Without
With
+8.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
6 currently pending
Career history
449
Total Applications
across all art units

Statute-Specific Performance

§101
5.8%
-34.2% vs TC avg
§103
55.6%
+15.6% vs TC avg
§102
12.4%
-27.6% vs TC avg
§112
17.1%
-22.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 440 resolved cases

Office Action

§DP
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claims 1-20 are pending. Information Disclosure Statement The references cited in the information disclosure statement (IDS) submitted on 8/29/25 have been considered by the examiner. Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim1-20 of U.S. Patent No. 12436881. Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1-20 of U.S. Patent No. 12436881 contains every element of claims 1-20 of the instant application and as such anticipates claim 1-20 of the instant application. Instant App U.S. Patent No. 12436881 1. A memory device comprising: a memory array; and a controller coupled to the memory array and configured to couple to a host, wherein the controller is configured to: receive a memory access request comprising a host logical-to-physical (L2P) entry of a host L2P table stored in the host; determine that the host L2P entry is invalid based on a comparison of a token included in the memory access request with a verification component stored in the memory array, wherein the verification component corresponds to a physical address included in the host L2P entry; and notify the host to refresh the host L2P table in response to a number of invalid host L2P entries exceeding a threshold. 1. A memory device comprising: a memory array comprising a memory logical-to-physical (L2P) table stored therein; and a controller coupled to the memory array and configured to couple to a host, wherein the controller is configured to: receive a memory access request comprising a first host L2P entry of a host L2P table stored in the host; tabulate the first host L2P entry based on a first indication of the first host L2P entry not corresponding to a second indication of a first memory L2P entry of the memory L2P table, wherein the first host L2P entry corresponds to the first memory L2P entry; and notify the host to refresh the host L2P table in response to a number of tabulations exceeding a threshold, and wherein the first indication comprises a first hash of the first host L2P entry, and the second indication comprises a second hash of the first memory L2P entry. Please note that MPEP § 804 states: “A complete response to a nonstatutory double patenting (NSDP) rejection is either a reply by applicant showing that the claims subject to the rejection are patentably distinct from the reference claims or the filing of a terminal disclaimer in accordance with 37 CFR 1.321 in the pending application(s) with a reply to the Office action (see MPEP § 1490 for a discussion of terminal disclaimers). Such a response is required even when the nonstatutory double patenting rejection is provisional. As filing a terminal disclaimer, or filing a showing that the claims subject to the rejection are patentably distinct from the reference application’s claims, is necessary for further consideration of the rejection of the claims, such a filing should not be held in abeyance. Only objections or requirements as to form not necessary for further consideration of the claims may be held in abeyance until allowable subject matter is indicated. Replies with an omission should be treated as provided in MPEP § 714.03. “ Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to TASNIMA MATIN whose telephone number is (571)272-8785. The examiner can normally be reached on Monday-Friday 9-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jared Rutz can be reached on 571-272-5535. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see https://ppair-my.uspto.gov/pair/PrivatePair. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. TASNIMA . MATIN Primary Examiner Art Unit 2135 /TASNIMA MATIN/Primary Examiner, Art Unit 2135
Read full office action

Prosecution Timeline

Aug 29, 2025
Application Filed
Sep 18, 2026
Non-Final Rejection mailed — §DP (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12743226
MEMORY PHASE MONITORING AND SCHEDULING SYSTEM
1y 9m to grant Granted Sep 22, 2026
Patent 12724704
METHODS OF OPERATING MEMORY SYSTEM, MEMORY SYSTEMS, HOSTS, AND MEMORY CONTROLLERS
2y 2m to grant Granted Sep 01, 2026
Patent 12717482
STORAGE SYSTEM USING COMPUTE EXPRESS LINK (CXL) INTERFACE
1y 9m to grant Granted Aug 25, 2026
Patent 12711059
In-NAND LLR Generation
2y 3m to grant Granted Aug 18, 2026
Patent 12710875
HOT DATA DETECTION FOR DISAGGREGATED MEMORY USING BLOOM FILTERS
1y 8m to grant Granted Aug 18, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
90%
Grant Probability
98%
With Interview (+8.3%)
2y 2m (~1y 1m remaining)
Median Time to Grant
Low
PTA Risk
Based on 440 resolved cases by this examiner. Grant probability derived from career allowance rate.

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