DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on July 28, 2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claims 4 and 9 are objected to because of the following informalities: The phrase “the second control signal shifting the voltage” should be corrected to “the second control signal by shifting the voltage” to match the phrase regarding the first control signal.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 2 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 recites the limitation "the issue". There is insufficient antecedent basis for this limitation in the claim. Although independent claim 1 recites “a second program associated with fixing issues”, there is no antecedent basis for which issue the claim term “the issue” refers to.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 – 3 and 6 – 8 are rejected under 35 U.S.C. 103 under by Park et al. (US Patent Application Publication 2025/0053471), hereinafter Park, in view of Kumar et al. (US Patent Application Publication 2025/0165345), hereinafter Kumar.
Regarding claim 1, Park teaches a solid-state disk (SSD) (Paragraphs 0002 and 0086, the storage systems taught include an SSD) comprising:
a power supply unit (Fig. 7, paragraphs 0081 and 0092, the power supplying device 1470);
a storage unit (Paragraph 0019, the storage device 200 containing storage controller 210 and non-volatile memory 220; Likewise, paragraph 0085, the storage devices 1300, their storage controllers 1310, and non-volatile memories 1320) that stores a first program that is associated with implementing basic operations (Paragraphs 0033 – 0035, the flash translation layer/FTL which can perform operations of programming, accessing the NVM data, and other functions; Paragraph 0042, the normal operating state/”normal mode”) and a second program that is associated with fixing issues that occur within the SSD therein (Paragraph 0043, the “recovery mode”);
a control unit connected to the storage unit (The storage controllers 210/1310); and
a monitoring unit (Fig. 1, the host 100; Fig. 7, the main processor 1100) connected to the power supply unit and the control unit (Fig. 7, the storage controllers, the host, and the power supplying device are all connected via the bus), and outputs a first control signal indicating a normal state to the control unit (Paragraph 0055, the host may transmit commands to the storage device, and the storage device may perform operations according to the commands),
the control unit, in response to receipt of the first control signal, loads and executes the first program, and outputs a pulse signal periodically (The heartbeat responses from the storage controller. Paragraph 0041, the storage controller 210 may periodically update a heartbeat to the host 100. A heartbeat is an information exchange signal that allows data to be shared at a certain period and may perform the function of notifying the normal operation of a system from one system to another; Paragraph 0055, Such commands and responses corresponding to the commands may continuously occur while performing operations between the host 100 and the storage device 200. The responses from the control unit occur regularly while the controller is in normal operation),
the monitoring unit, in response to determination that no pulse signal is received from the control unit (Paragraph 0043, the storage system 10 enters a recovery mode in response to determining that the heartbeat update failed to respond in time), deactivates the control unit and then reactivates the control unit (Paragraphs 0045/0046, the storage system may reset the connection between the host and the storage device, paragraph 0049, the storage recovery operation made in response to the failure may include a reset or reboot of the storage device), and outputs a second control signal indicating an abnormal state to the control unit (Paragraph 0047, the recovery signal which causes the storage device to perform an internal recovery method); and
the control unit, in response to receipt of the second control signal, loads and executes the second program to implement a self-recovery operation (Paragraphs 0047 – 0049).
Park does not expressly teach that the monitoring unit, in response to determination that no pulse signal is received from the control unit, controls the power supply unit to deactivate the control unit and then to reactivate the control unit (Although it is taught that the storage device may be rebooted, it is not expressly stated that this is done by means of the power supply unit).
Kumar teaches a monitoring unit (Fig. 2, failure detector module 112) that controls the power supply unit to deactivate the control unit and then to reactivate the control unit (Paragraph 0023, a recovery routine triggered by the failure detector module may perform a controller reset that is a power cycle).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention that the deactivating and reactivating of the control unit in Park would be performed through control of the power supply unit as taught by Kumar. It would have been obvious because a simple substitution of one known element (a general reset of a connection via a storage device as taught by Park Fig. 3 and paragraph 0045) for another (The power cycle event of Kumar paragraph 0023) can be performed to obtain predictable results. A power cycle is a known means to reestablish a connection during a recovery process; Kumar indicates that the ordinary meaning of a controller reset includes a power cycle of the controller in paragraph 0023. It would be clear to one of ordinary skill in the art that this would include the controller reset of Park.
Regarding claim 2, Park in view of Kumar teaches the SSD as claimed in Claim 1, wherein:
the control unit, in determining that the self-recovery operation has fixed the issue, further transmits a confirmation signal (Park paragraph 0050, after the storage recovery operation is performed, the storage controller may transmit a signal to notify the host that recovery has been completed); and
the monitoring unit, in response to receipt of the confirmation signal, outputs the first control signal indicating the normal state to the control unit (Park paragraph 0050, the storage system exists recovery mode and returns to normal mode).
Park in view of Kumar as applied to Claim 1 does not teach that the monitoring unit, in response to receipt of the confirmation signal, further controls the power supply unit to deactivate the control unit and controls the power supply unit to reactivate the control unit (Park does not teach details on what occurs when the device transitions out of the recovery mode back to the normal mode).
Kumar teaches that the monitoring unit, in response to receipt of the confirmation signal, further controls the power supply unit to deactivate the control unit and controls the power supply unit to reactivate the control unit (Paragraph 0033, after a firmware upgrade as part of a recovery operation is finished, the storage device may reboot into the normal mode; Paragraph 0023, booting into a different mode occurs on the next power cycle of the device; Paragraph 0041, switching back to normal initialization occurs after confirming a failure is expected).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention that the transition by the device of Park from recovery mode to normal mode would include controlling the power supply unit to deactivate and reactivate the control unit, as taught by Kumar. It would be obvious because it resets the state of the storage device, reducing the possibility of the failure reoccurring (Kumar paragraph 0033).
Regarding claim 3, Park in view of Kumar teaches the SSD as claimed in Claim 1, wherein:
the control unit includes a communication interface that is connected to the monitoring unit and that supports a communication protocol (Park paragraphs 0024/0025, the host and the storage device communicate according to a standard protocol including PCIe or NVMe);
the monitoring unit, after controlling the power supply unit to activate the control unit (Park paragraph 0041, the heartbeat responses are sent during normal operation of the system. Therefore the control unit has been activated previously), outputs the first control signal using the communication protocol (Park paragraphs 0041 – 0044 demonstrate that the heartbeat responses mapped to the first control signal are indicative of the state of the connection between the host and storage device, therefore they are transmitted across the PCIe or NVMe); and
the monitoring unit, after controlling the power supply unit to reactivate the control unit (Park paragraphs 0045 – 0047, the recovery signal is transmitted after resetting the connection), outputs the second control signal using the communication protocol through the communication interface (Park paragraph 0047, the recovery signal is transmitted from the host to the storage controller using a PCIe channel or NVMe channel).
Regarding claim 6, Park teaches a method for identifying and fixing an issue in a solid-state disk (SSD) (Paragraphs 0002 and 0086, the storage systems taught include an SSD), the SSD including a power supply unit (Fig. 7, paragraphs 0081 and 0092, the power supplying device 1470), a storage unit (Paragraph 0019, the storage device 200 containing storage controller 210 and non-volatile memory 220; Likewise, paragraph 0085, the storage devices 1300, their storage controllers 1310, and non-volatile memories 1320), a control unit connected to the storage unit (The storage controllers 210/1310), and a monitoring unit (Fig. 1, the host 100; Fig. 7, the main processor 1100) connected to the power supply unit and the control unit (Fig. 7, the storage controllers, the host, and the power supplying device are all connected via the bus), the storage unit storing a first program that is associated with implementing basic operations (Paragraphs 0033 – 0035, the flash translation layer/FTL which can perform operations of programming, accessing the NVM data, and other functions; Paragraph 0042, the normal operating state/”normal mode”) and a second program that is associated with fixing issues that occur within the SSD therein (Paragraph 0043, the “recovery mode”),
the method comprising the steps of:
(A) the monitoring unit outputting a first control signal indicating a normal state to the control unit (Paragraph 0055, the host may transmit commands to the storage device, and the storage device may perform operations according to the commands),
(B) the control unit, in response to receipt of the first control signal, loading and executing the first program, and outputting a pulse signal periodically (The heartbeat responses from the storage controller. Paragraph 0041, the storage controller 210 may periodically update a heartbeat to the host 100. A heartbeat is an information exchange signal that allows data to be shared at a certain period and may perform the function of notifying the normal operation of a system from one system to another; Paragraph 0055, Such commands and responses corresponding to the commands may continuously occur while performing operations between the host 100 and the storage device 200. The responses from the control unit occur regularly while the controller is in normal operation),
(C) the monitoring unit, in response to determination that no pulse signal is received from the control unit (Paragraph 0043, the storage system 10 enters a recovery mode in response to determining that the heartbeat update failed to respond in time), deactivating the control unit and then reactivating the control unit (Paragraphs 0045/0046, the storage system may reset the connection between the host and the storage device, paragraph 0049, the storage recovery operation made in response to the failure may include a reset or reboot of the storage device), and outputting a second control signal indicating an abnormal state to the control unit (Paragraph 0047, the recovery signal which causes the storage device to perform an internal recovery method); and
(D) the control unit, in response to receipt of the second control signal, loading and executing the second program to implement a self-recovery operation (Paragraphs 0047 – 0049).
Park does not expressly teach:
the monitoring unit controlling the power supply unit to activate the control unit
(C) the monitoring unit, in response to determination that no pulse signal is received from the control unit, controlling the power supply unit to deactivate the control unit and then to reactivate the control unit (Although it is taught that the storage device may be rebooted, it is not expressly stated that this is done by means of the power supply unit).
Kumar teaches
(A) a monitoring unit (Fig. 2, the failure detector module 112) controlling the power supply unit to activate the control unit (Paragraph 0023, a recovery routine triggered by the failure detector module may perform a controller reset that is a power cycle).
(C) the monitoring unit controlling the power supply unit to deactivate the control unit and then to reactivate the control unit (Paragraph 0023, a recovery routine triggered by the failure detector module may perform a controller reset that is a power cycle).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention that the deactivating and reactivating of the control unit in Park would be performed through control of the power supply unit as taught by Kumar. It would have been obvious because a simple substitution of one known element (a general reset of a connection via a storage device as taught by Park Fig. 3 and paragraph 0045) for another (The power cycle event of Kumar paragraph 0023) can be performed to obtain predictable results. A power cycle is a known means to reestablish a connection during a recovery process; Kumar indicates that the ordinary meaning of a controller reset includes a power cycle of the controller in paragraph 0023. Therefore it would be clear to one of ordinary skill in the art that the reset of Park can be substituted for this power cycle.
Regarding claim 7, Park in view of Kumar as applied to Claim 6 teaches the method as claimed in Claim 6, further comprising, after step (D), the steps of:
(E) the control unit, in determining that the self-recovery operation has fixed the issue, transmitting a confirmation signal (Park paragraph 0050, after the storage recovery operation is performed, the storage controller may transmit a signal to notify the host that recovery has been completed); and
the monitoring unit, in response to receipt of the confirmation signal, repeating step (A) (Park paragraph 0050, the storage system exists recovery mode and returns to normal mode).
Park in view of Kumar as applied to Claim 6 does not teach that
(F) the monitoring unit, in response to receipt of the confirmation signal, further controls the power supply unit to deactivate the control unit (Park does not teach details on what occurs when the device transitions out of the recovery mode back to the normal mode).
Kumar teaches that the monitoring unit, in response to receipt of the confirmation signal, further controls the power supply unit to deactivate the control unit (Paragraph 0033, after a firmware upgrade as part of a recovery operation is finished, the storage device may reboot into the normal mode; Paragraph 0023, booting into a different mode occurs on the next power cycle of the device; Paragraph 0041, switching back to normal initialization occurs after confirming a power cycle was expected).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention that the transition by the device of Park from recovery mode to normal mode would include controlling the power supply unit to deactivate the control unit, as taught by Kumar. It would be obvious because it resets the state of the storage device, reducing the possibility of the failure reoccurring (Kumar paragraph 0033).
Regarding claim 8, Park in view of Kumar teaches the method as claimed in claim 6, the control unit including a communication interface connected to the monitoring unit and that supports a communication protocol (Park paragraphs 0024/0025, the host and the storage device communicate according to a standard protocol including PCIe or NVMe), wherein:
step (A) includes the monitoring unit outputting the first control signal using the communication protocol (Park paragraphs 0041 – 0044 demonstrate that the heartbeat responses mapped to the first control signal are indicative of the state of the connection between the host and storage device. Paragraph 0025 states that the recovery signals using the channels is described with reference to Figs. 3 – 5, which includes the heartbeats) after controlling the power supply unit to activate the control unit (Park paragraph 0041, the heartbeat responses are sent during normal operation of the system. Therefore the control unit has been activated previously); and
step (C) includes the monitoring unit outputting the second control signal using the communication protocol through the communication interface (Park paragraph 0047, the recovery signal is transmitted from the host to the storage controller using a PCIe channel or NVMe channel) after controlling the power supply unit to reactivate the control unit (Park paragraphs 0045 – 0047, the recovery signal is transmitted after resetting the connection).
Claims 4, 5, 9 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Kumar as applied to claims 1 and 6 above, and further in view of Chen et al. (US Patent Application Publication 2020/0151056), hereinafter Chen.
Regarding claim 4, Park in view of Kumar teaches the SSD as claimed in Claim 1.
Park in view of Kumar does not teach the SSD as claimed in Claim 1, wherein:
the control unit includes a communication pin connected to the monitoring unit;
the monitoring unit, before controlling the power supply unit to activate the control unit, outputs the first control signal by shifting a voltage to the communication pin to a first logic level; and
the monitoring unit, before controlling the power supply unit to reactivate the control unit, outputs the second control signal by shifting the voltage to the communication pin to a second logic level different from the first logic level (The claim language is directed to a low-level hardware implementation of communication logic. Neither Park nor Kumar explicitly describes the communication as being used with pins and voltage levels).
Park in view of Kumar does, however, teach that
the monitoring unit, before controlling the power supply unit to activate the control unit, outputs the first control signal (Park paragraphs 0047 – 0049, the actual reset of the device in step S370 occurs after the signal to recover it is sent by the host in step S360; Kumar paragraph 0023, Failure detector module 112 may trigger an interrupt signal to controller 108 for controller 108 to execute recovery routine 214. Recovery routine 214 may perform a controller reset, i.e. a power cycle initiated by storage device 104. The interrupt signal is transmitted to execute the recovery routine before the recovery routine is actually controlled to perform the power cycle); and
the monitoring unit, before controlling the power supply unit to reactivate the control unit, outputs the second control signal (Park paragraphs 0047 – 0049, the actual reset of the device in step S370 occurs after the signal to recover it is sent by the host in step S360; Kumar paragraph 0023, Failure detector module 112 may trigger an interrupt signal to controller 108 for controller 108 to execute recovery routine 214. Recovery routine 214 may perform a controller reset, i.e. a power cycle initiated by storage device 104. The interrupt signal is transmitted to execute the recovery routine before the recovery routine is actually controlled to perform the power cycle).
That is, Park in view of Kumar does not teach that the control signals are transmitted by shifting a voltage / logic level of a communication pin.
Chen teaches:
a control unit (Fig. 1, the memory controller 100) includes a communication pin (Paragraph 0025, the error status pin 0025) connected to a monitoring unit (Paragraph 0026, the error analyzer/error manager which reads the error status pin);
the monitoring unit outputs a first control signal by shifting a voltage to the communication pin to a first logic level (Paragraph 0025, when an error occurs on a connected memory, the error status pin is enabled by adjusting a voltage level from a first voltage to a second voltage to indicate an error has been detected. Paragraph 0026, when the error status pin is disabled, the error status pin is at a lower voltage); and
the monitoring unit outputs a second control signal by shifting the voltage to the communication pin to a second logic level different from the first logic level (Paragraph 0025, when an error occurs on a connected memory, the error status pin is enabled by adjusting a voltage level from a first voltage to a second voltage to indicate an error has been detected.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention that the PCIe interface of Park in view of Kumar would be implemented by shifting voltages of pins as taught by Chen. It would have been obvious because a simple substitution of one known element (The interconnects of Park paragraph 0024/0025 and Kumar paragraph 0045) for another (The status pins of Chen) can be performed to obtain predictable results. The results would be predictable because there are similar signals within Park (Paragraphs 0075 – 0077 and 0107) transmit information in a similar manner, and because the error signals of Park, Kumar, and Chen are all simple binary indications that a particular error has occurred.
Regarding claim 5, Park in view of Kumar and Chen teaches the SSD as claimed in Claim 4, wherein:
the control unit further includes a communication interface that is connected to the monitoring unit and that supports a communication protocol (Park paragraphs 0024/0025, the host and the storage device communicate according to a standard protocol including PCIe or NVMe); and
the control unit periodically outputs the pulse signal (Park paragraph 0041, the heartbeat) through the communication interface using the communication protocol (Park paragraph 0025, communication between the host and storage device is done via the protocol. This is stated to include the communications in reference to Figs. 3 – 5, which includes the heartbeats).
Regarding claim 9, Park in view of Kumar teaches the method as claimed in Claim 6.
Park in view of Kumar does not teach the method as claimed in Claim 6, the control unit including a communication pin connected to the monitoring unit, wherein:
step (A) includes the monitoring unit outputting the first control signal by shifting a voltage to the communication pin to a first logic level before controlling the power supply unit to activate the control unit; and
step (C) includes the monitoring unit outputting the second control signal by shifting the voltage to the communication pin to a second logic level different from the first logic level before controlling the power supply unit to reactivate the control unit (The claim language is directed to a low-level hardware implementation of communication logic. Neither Park nor Kumar explicitly describes the communication as being used with pins and voltage levels).
Park in view of Kumar does, however, teach that
step (A) includes the monitoring unit outputting the first control signal before controlling the power supply unit to activate the control unit (Park paragraphs 0047 – 0049, the actual reset of the device in step S370 occurs after the signal to recover it is sent by the host in step S360; Alternatively, Kumar paragraph 0028, the host may power cycle the storage device. Kumar paragraph 0023, Failure detector module 112 may trigger an interrupt signal to controller 108 for controller 108 to execute recovery routine 214. Recovery routine 214 may perform a controller reset, i.e. a power cycle initiated by storage device 104. The interrupt signal is transmitted to execute the recovery routine before the recovery routine is actually controlled to perform the power cycle); and
step (C) includes the monitoring unit outputting the second control signal before controlling the power supply unit to reactivate the control unit (Park paragraphs 0047 – 0049, the actual reset of the device in step S370 occurs after the signal to recover it is sent by the host in step S360; Alternatively, Kumar paragraph 0028, the host may power cycle the storage device. Kumar paragraph 0023, Failure detector module 112 may trigger an interrupt signal to controller 108 for controller 108 to execute recovery routine 214. Recovery routine 214 may perform a controller reset, i.e. a power cycle initiated by storage device 104. The interrupt signal is transmitted to execute the recovery routine before the recovery routine is actually controlled to perform the power cycle).
That is, Park in view of Kumar does not teach that the control signals are transmitted by shifting a voltage / logic level of a communication pin.
Chen teaches a method with:
a control unit (Fig. 1, the memory controller 100) including a communication pin (Paragraph 0025, the error status pin 0025) connected to a monitoring unit (Paragraph 0026, the error analyzer/error manager which reads the error status pin);
(A) the monitoring unit outputting a first control signal by shifting a voltage to the communication pin to a first logic level (Paragraph 0025, when an error occurs on a connected memory, the error status pin is enabled by adjusting a voltage level from a first voltage to a second voltage to indicate an error has been detected. Paragraph 0026, when the error status pin is disabled, the error status pin is at a lower voltage); and
(C) the monitoring unit outputting a second control signal by shifting the voltage to the communication pin to a second logic level different from the first logic level (Paragraph 0025, when an error occurs on a connected memory, the error status pin is enabled by adjusting a voltage level from a first voltage to a second voltage to indicate an error has been detected.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention that the PCIe interface of Park in view of Kumar would be implemented by shifting voltages of pins as taught by Chen. It would have been obvious because a simple substitution of one known element (The interconnects of Park paragraph 0024/0025 and Kumar paragraph 0045) for another (The status pins of Chen) can be performed to obtain predictable results. The results would be predictable because there are similar signals within Park (Paragraphs 0075 – 0077 and 0107) transmit information in a similar manner, and because the error signals of Park, Kumar, and Chen are all simple binary indications that a particular error has occurred.
Regarding claim 10, Park in view of Kumar and Chen teaches the method as claimed in claim 9, the control unit further including a communication interface that is connected to the monitoring unit and that supports a communication protocol (Park paragraphs 0024/0025, the host and the storage device communicate according to a standard protocol including PCIe or NVMe); wherein step (B) includes the control unit periodically outputting the pulse signal (Park paragraph 0041, the heartbeat) through the communication interface using the communication protocol (Park paragraph 0025, communication between the host and storage device is done via the protocol. This is stated to include the communications in reference to Figs. 3 – 5, which includes the heartbeats).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Horning (US Patent 5,414,861), Shin et al. (US Patent Application Publication 2015/0363258) and Koike (US Patent Application Publication 2023/0333839) teach recovery modes for devices including SSDs.
Matsubayashi et al. (US Patent Application Publication 2016/0321199) and Idapalapati et al. (US Patent Application Publication 2017/0269984) teach heartbeat signals to detect failures.
They are not relied upon as particular implementation details are dissimilar to the claims, but are noted to demonstrate that high-level structure of the claims are common in the art.
With regards to claims 4 and 9, Zitlaw (US Patent 9,921,763) teaches a set of status pins that output the failure status of a set of memories. It is not relied upon as it does not explicitly teach that these status pins use voltage and logic levels to output their signals. Wig et al. (US Patent Application Publication 2014/0141654) teaches that changing the voltage of pins is a typical implementation of PCIe communication.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRYAN PAI SONG HUANG whose telephone number is (571)272-0510. The examiner can normally be reached Monday - Friday 11:30 AM - 8:30 PM.
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/B.P.H./Examiner, Art Unit 2114
/JOSEPH R KUDIRKA/Primary Patent Examiner, Art Unit 2114
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