Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim 1 is pending.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 of U.S. Patent No. 12,411,765.
Claim(s) 1 of patent # 12,411,765 contain(s) every element of claim(s) 1 of the instant application and as such anticipate(s) claim(s) 1 of the instant application.
“A later patent claim is not patentably distinct from an earlier patent claim if the later claim is obvious over, or anticipated by, the earlier claim. In re Longi, 759 F.2d at 896, 225 USPQ at 651 (affirming a holding of obviousness-type double patenting because the claims at issue were obvious over claims in four prior art patents); In re Berg, 140 F.3d at 1437, 46 USPQ2d at 1233 (Fed. Cir. 1998) (affirming a holding of obviousness-type double patenting where a patent application claim to a genus is anticipated by a patent claim to a species within that genus). “ ELI LILLY AND COMPANY v BARR LABORATORIES, INC., United States Court of Appeals for the Federal Circuit, ON PETITION FOR REHEARING EN BANC (DECIDED: May 30, 2001).
Below is the claim mapping between the claim of the instant application and patent:
Current Application
1.A node in a network including a plurality of nodes, comprising:
a processing unit and a memory unit, the memory unit including a first interface to interface with the processing unit and a second interface to interface with one or more memory units in one or more other nodes of the plurality of nodes; and
wherein the memory unit includes a node control device configurable to:
receive a memory access request from the processing unit via the first interface;
in response to the memory access request including a first address in a local unified memory access (UMA) address space accessible by applications running on the processing unit, translate the first address to a second address in a global UMA address space, the global UMA address space being mapped to a physical UMA address space including physical address spaces associated with memory units in the plurality of nodes; and
transmit a first request packet via the second interface, the first request packet including the second address or a first target address for a first target node among the plurality of nodes; and
wherein the network further includes memory access paths, each of the memory access paths is between the second interface of one memory unit in one node and the second interface of another memory unit in another node, and none of the memory access paths go through any of the processing unit in any of the plurality of nodes.
Patent 12,411,765
1.A node in a network including a plurality of nodes, comprising:
a processing unit and a memory unit, the memory unit including a first interface configured to interface with the processing unit and a second interface configured to interface with one or more memory units in one or more other nodes of the plurality of nodes without going through any processing unit in any of the one or more other nodes; and wherein the memory unit includes a node control device configurable to:
receive a memory access request from the processing unit via the first interface; in response to the memory access request including a first address in a local unified memory access (UMA) address space accessible by applications running on the processing unit, translate the first address to a second address in a global UMA address space, the global UMA address space being mapped to a physical UMA address space including physical address spaces associated with memory units in the plurality of nodes; and
transmit a first request packet via the second interface, the first request packet including the second address or a first target address for a first target node among the plurality of nodes; and
wherein the network further includes memory access paths, each of the memory access paths is between the second interface of one memory unit in one node and the second interface of another memory unit in another node, and none of the memory access paths go through any of the processing unit in any of the plurality of nodes.
Claim(s) 1 of patent # 12,411,765 contain(s) every element of claim(s) 1 of the instant application and as such anticipate(s) claim(s) 1 of the instant application.
Claims 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 of U.S. Patent No. 11,768,769.
Claim(s) 1 of patent #11,768,769 contain(s) every element of claim(s) 1 of the instant application and as such anticipate(s) claim(s) 1 of the instant application.
“A later patent claim is not patentably distinct from an earlier patent claim if the later claim is obvious over, or anticipated by, the earlier claim. In re Longi, 759 F.2d at 896, 225 USPQ at 651 (affirming a holding of obviousness-type double patenting because the claims at issue were obvious over claims in four prior art patents); In re Berg, 140 F.3d at 1437, 46 USPQ2d at 1233 (Fed. Cir. 1998) (affirming a holding of obviousness-type double patenting where a patent application claim to a genus is anticipated by a patent claim to a species within that genus). “ ELI LILLY AND COMPANY v BARR LABORATORIES, INC., United States Court of Appeals for the Federal Circuit, ON PETITION FOR REHEARING EN BANC (DECIDED: May 30, 2001).
Below is an example claim mapping:
Current Application
1. A node in a network including a plurality of nodes, comprising:
a processing unit and a memory unit, the memory unit including a first interface to interface with the processing unit and a second interface to interface with one or more memory units in one or more other nodes of the plurality of nodes; and
wherein the memory unit includes a node control device configurable to:
receive a memory access request from the processing unit via the first interface;
in response to the memory access request including a first address in a local unified memory access (UMA) address space accessible by applications running on the processing unit,
translate the first address to a second address in a global UMA address space, the global UMA address space being mapped to a physical UMA address space including physical address spaces associated with memory units in the plurality of nodes; and
transmit a first request packet via the second interface, the first request packet including the second address or a first target address for a first target node among the plurality of nodes; and
wherein the network further includes memory access paths, each of the memory access paths is between the second interface of one memory unit in one node and the second interface of another memory unit in another node, and none of the memory access paths go through any of the processing unit in any of the plurality of nodes.
Patent 11,768,769
1. A system, comprising:
a plurality of nodes,
each respective node of the plurality of nodes including a respective
processing unit and a respective memory unit, the respective memory unit including a respective first interface to interface with the respective processing unit and a respective second interface to interface with one or more memory units in one or more other nodes of the plurality of nodes;
and wherein the respective memory unit in the respective node of the plurality of nodes includes a node control device configurable to: receive a memory access request from the respective processing unit via the respective first interface;
in response to the memory access request including a first address in a local unified memory access (UMA) address space accessible by applications running on the respective processing unit,
translate the first address to a second address in a global UMA address space, the global UMA address space being mapped to a physical UMA address space including physical address spaces associated with memory units in the plurality of nodes; and
transmit a first request packet via the second interface, the first request packet including the second address or a first target address for a first target node among the plurality of nodes.
and memory access paths, wherein each of the memory access paths is between the second interface of one memory unit in one node and the second interface of another memory unit in another node, wherein none of the memory access paths go through any of the processing unit in any of the plurality of nodes;
As can be seen from above, claim 1 of the patent include all of the limitations of claim 1 of the instant application, and more, anticipating claim 1 of the instant application.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 9,262,225 discloses a server apparatus having remote memory access function in a cluster of data processing nodes. Each node have memory resources and are interconnected through a node interconnect fabric and can allocate memory resources to other nodes.
US 8,185,683 discloses an information processing system in which a plurality of processor units are connected to each other by a switch, a global address space is introduced into which effective addresses of the processor units are mapped and which is shared by the plurality of processor units. The nodes share a global address space, each processor effective address space is mapped into its node.
US 10,073,809 discloses a remote memory access method to nodes over a network. A receiver computing node receives a message from a sender node and extracts a segment identifier from the message. The receiver computing node determines, based on the segment identifier, a segment start address associated with a partitioned global address space (PGAS) segment of its local memory. The receiver computing node may index a segment table stored in the local memory or in a host fabric interface. The receiver computing node determines a local destination address within the PGAS segment based on the segment start address and an offset included in the message. The receiver computing node performs a remote memory access operation at the local destination address. The receiver computing node may perform those operations in hardware by the host fabric interface of the receiver computing node.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THAN NGUYEN whose telephone number is (571)272-4198. The examiner can normally be reached M-F 7:00am -4:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tim Vo can be reached on (571)272-3642. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/THAN NGUYEN/Primary Examiner, Art Unit 2138
