DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-28 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
6. Claim(s) 1 and 20-22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shin et al (2023/0217767) (herein “Shin”) in view of LIM et al (2016/0093247) (herein “LIM”) and further in view of JUNG et al (2014/0055503) (herein “JUNG”). In regards to claims 1 and 21, Shin teaches a display panel comprising: a first pixel including a first plurality of sub-pixels (See; Fig. 3 for PX1 comprising a plurality of sub pixels); a second pixel including a second plurality of sub-pixels, the second pixel adjacent to the first pixel in a first direction (See; Fig. 3 for PX2 comprising a plurality of sub pixels, adjacent to PX1); a first high potential voltage line on a first side of the first pixel in the first direction (See; Fig. 3 for left most high potential voltage line VDDL adjacent to PX1); a second high potential voltage line on a second side of the second pixel in the first direction (See; Fig. 3 for right most high potential voltage line VDDL adjacent PX2); a third high potential voltage line between the first pixel and the second pixel such that the third high potential voltage line is on a second side of the first pixel and a first side of the second pixel (See; Fig. 3 the middle high potential voltage line VDDL between PX1 and PX2). Shin fails to explicitly teach wherein the third high potential voltage line is electrically connected to a first set of the first plurality of sub-pixels but not electrically connected to a second set of the first plurality of sub-pixels other than the first set of the first plurality of sub-pixels, and wherein the third high potential voltage line is electrically connected to a first set of the second plurality of sub-pixels but not electrically connected to a second set of the second plurality of sub-pixels other than the first set of the second plurality of sub-pixels. However the Examiner contends that Shin would implicitly teach this statement as the central VDDL line (third high potential voltage line) would be connected in a similar manner to that of the DL1 and DL3 lines, where the central VDDL would be connected to the sub pixels adjacent to it (i.e. the left sub pub pixels in PX1 (GC, WC) and the right most sub pixels in PX2 (WC)). There would be no reasons to have three VDDL lines if each VDDL line was used to control a whole pixel, there would be an unused VDDL line. However, for the sake of compact prosecution, LIM teaches wherein the third high potential voltage line is electrically connected to a first set of the first plurality of sub-pixels but not electrically connected to a second set of the first plurality of sub-pixels other than the first set of the first plurality of sub-pixels, and wherein the third high potential voltage line is electrically connected to a first set of the second plurality of sub-pixels but not electrically connected to a second set of the second plurality of sub-pixels other than the first set of the second plurality of sub-pixels (See; Fig. 5 where VDD2 is connected to electrode 503 of the first pixel region 101a and electrode 501 of the second pixel region 101b. Where VDD2 is not connected to all of the sub pixels in each pixel region). Therefore it would have been obvious to one of ordinary skill in the art at the time of filing to connect the sub pixels to the closest VDDL line in Shin so as to reduce circuit complexity. The combination fails to explicitly teach a plurality of driving circuits configured to drive the first plurality of sub-pixels of the first pixel, wherein a first set of the plurality of driving circuits is on a third side of the first pixel, wherein a second set of the plurality of driving circuits is on a fourth side of the first pixel, wherein the first set of the plurality of driving circuits and the second set of the plurality of driving circuits are not electrically connected to the same sub-pixels. However, JUNG teaches a plurality of driving circuits configured to drive the first plurality of sub-pixels of the first pixel, wherein a first set of the plurality of driving circuits is on a third side of the first pixel, wherein a second set of the plurality of driving circuits is on a fourth side of the first pixel, wherein the first set of the plurality of driving circuits and the second set of the plurality of driving circuits are not electrically connected to the same sub-pixels (See; Fig. 1 and p[0010] for a first and second data driver 150 and 160 located on a third and fourth side of the pixels. See; Fig. 2 and p[0065]-p[0068] where a first sub pixel SPX1 is connected to the first data driver through DLj_1 and the second sub pixel SPX2 is connected to the second data driver through DLj_2). Therefore it would have been obvious to one of ordinary skill in the art at the time of filing to modify the sub pixels to be connected to different data drivers at different positions on the display so as to supply different data voltages to each sub pixel so as to reduce a brightness difference in the display and improve side visibility of the display (See; p[0008]-p[0009]). In regards to claim 20, Shin teaches a display device comprising: the display panel of claim 1; a data driver configured to supply a data voltage to the display panel via a plurality of data lines (See; Figs. 1-3 for a data driver supplying data voltages DATA along data lines DL); and a gate driver configured to supply a gate signal to the display panel via a plurality of gate lines (See; Figs. 1-3 for a gate driver supplying gate signals GATE along data lines GL).
In regards to claim 22, Shin teaches further comprising: a first gate line that supplies a first gate signal to at least one of the first plurality of sub- pixels of the first pixel and at least one of the second plurality of sub-pixels of the second pixel, the first gate line on the third side of the first pixel (See; Fig. 3 for GATE1 connected to RC and GC of PX1 as well as WC and BC of PX2 on the top side of the pixel); and a second gate line that supplies a second gate signal to at least another one of the first plurality of sub-pixels of the first pixel and at least another one of the second plurality of sub-pixels of the second pixel, the second gate line on the fourth side of the first pixel (See; Fig. 3 for GATE2 connected to WC and BC of PX1 as well as GC and RC of PX2 on the bottom side of the pixel).
Claim(s) 16-19, 27 and 28 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shin et al (2023/0217767) (herein “Shin”) in view of LIM et al (2016/0093247) (herein “LIM”) in view of JUNG et al (2014/0055503) (herein “JUNG”) and further in view of Fletcher et al (2018/0233077) (herein “Fletcher”). In regards to claim 16, Shin teaches wherein the first pixel includes a first sub-pixel having a first side and a second side that is opposite the first side in a second direction that is different from the first direction, a second sub-pixel having a first side and a second side that is opposite the first side in the second direction, and a third sub-pixel having a first side and a second side that is opposite the first side in the second direction (See; Fig. 3 for PX1 having sub pixels GC, RC and WC), wherein the display panel further comprises a first driving circuit that is configured to drive the first sub-pixel, a second driving circuit that is configured to drive the second sub-pixel, and a third driving circuit that is configured to drive the third sub-pixel (See; Figs. 2, 3 and p[0038] where the data driver may consist of a plurality of source drive ICS to supply data to a first node N1 and to drive transistor DT of each sub pixel). Shin fails to explicitly teach the first sub-pixel, the second sub- pixel, and the third sub-pixel are sequentially arranged in the first direction, wherein the first driving circuit is disposed on the first side of the first sub-pixel in the second direction, the second driving circuit is disposed on the second side of the second sub-pixel in the second direction, and the third driving circuit is disposed on the first side the third sub-pixel in the second direction (Shin teaches all driving circuits are on the same side of the sub pixels (See; Fig. 1)). However, Fletcher teaches the first sub-pixel, the second sub- pixel, and the third sub-pixel are sequentially arranged in the first direction (See; Fig. 3 where the sub pixels are sequentially arranged in the first direction), wherein the first driving circuit is disposed on the first side of the first sub-pixel in the second direction, the second driving circuit is disposed on the second side of the second sub-pixel in the second direction, and the third driving circuit is disposed on the first side the third sub-pixel in the second direction (See; Figs. 3, 5A and p[0036] where each sub pixel is driven by two drivers as driver pairs, each being on opposite sides of each sub pixel in a second direction). When JUNG is modified with the sequentially arranged sub pixels in the first direction of Fletcher, the claim is realized. In other words, since Jung supplies every other sub pixel with a different voltage from a different driver on opposite sides, if Jung’s pixels were arranged such as in Fletcher, every other sub pixels would be symmetrically supplied by a driver on any given side. Therefore it would have been obvious to one of ordinary skill in the art at the time of filing to modify JUNG to have sequentially arranged sub pixels in the first direction such as in of Fletcher as a mere design choice based on the pixel layout of the given display.
In regards to claim 17, Fletcher teaches wherein the second pixel includes a fourth sub-pixel having a first side and a second side that is opposite the first side in the second direction, a fifth sub-pixel having a first side and a second side that is opposite the first side in the second direction, and a sixth sub-pixel having a first side and a second side that is opposite the first side in the second direction, and the fourth sub-pixel, the fifth sub-pixel, and the sixth sub-pixel are sequentially arranged in the first direction, wherein the display panel further comprises a fourth driving circuit that is configured to drive the fourth sub-pixel, a fifth driving circuit that is configured to drive the fifth sub-pixel, and a sixth driving circuit that is configured to drive the sixth sub-pixel, wherein the fourth driving circuit is disposed on the second side of the fourth sub-pixel in the second direction, the fifth driving circuit is disposed on the first side of the fifth sub-pixel in the second direction, and the sixth driving circuit is disposed on the second side of the sixth sub-pixel in the second direction (See; Figs. 3, 5A and p[0036] where each sub pixel is driven by two drivers as driver pairs, each being on opposite sides of each sub pixel in a second direction. When the claims are read in the broadest reasonable sense, one could selectively name either driver of the pair as needed to be read on for each subpixel in each claimed arrangement. Same could be shown for an adjacent second pixel not shown in Fig. 3 but implied where they would inherently have a fourth, fifth and sixth driver for the second adjacent pixels three sub pixels). When JUNG is modified with the sequentially arranged sub pixels in the first direction of Fletcher, the claim is realized. In other words, since Jung supplies every other sub pixel with a different voltage from a different driver on opposite sides, if Jung’s pixels were arranged such as in Fletcher, every other sub pixels would be symmetrically supplied by a driver on any given side. In regards to claim 18, Shin teaches wherein the display panel further comprises: a plurality of gate lines that supply a gate signal to the first pixel and the second pixel (See; Fig. 3 for GATE1, GATE2 where some GATE lines connect to some sub pixels and some connect to different sub pixels in the same pixel). Shin fails to explicitly teach the plurality of gate lines including a first gate line between the first sub-pixel and the first driving circuit, between the third sub-pixel and the third driving circuit, and between the fifth sub-pixel and the fifth driving circuit.
However, when Shin is combined with the paired drivers of Fletcher (See; Fig. 3 of Fletcher where each sub pixel is connected to a top and bottom driver), Shin teaches the plurality of gate lines including a first gate line between the first sub-pixel and the first driving circuit (See; Fig. 3 where GATE1 is between GC of PX1 and a bottom driver), between the third sub-pixel and the third driving circuit (See; Fig. 3 for GATE1 between GC of PX2 and a bottom driver), and between the fifth sub-pixel and the fifth driving circuit (See; Fig. 3 where GATE1 is between WC of PX2 and a top driver). When JUNG is modified with the sequentially arranged sub pixels in the first direction of Fletcher, the claim is realized. In other words, since Jung supplies every other sub pixel with a different voltage from a different driver on opposite sides, if Jung’s pixels were arranged such as in Fletcher, every other sub pixels would be symmetrically supplied by a driver on any given side. Therefore it would have been obvious to one of ordinary skill in the art at the time of filing to modify JUNG to have sequentially arranged sub pixels in the first direction such as in of Fletcher as a mere design choice based on the pixel layout of the given display. In regards to claim 19, Shin teaches (when combined with Fletcher’s paired drivers) wherein the first high potential voltage line applies a first high potential voltage to the first driving circuit, the second high potential voltage line applies a second high potential voltage to the fifth driving circuit and the sixth driving circuit, and the third high potential voltage line applies a third high potential voltage to the second driving circuit, the third driving circuit, and the fourth driving circuit (See; Fig. 3). In regards to claim 27, Shin teaches wherein the first pixel includes a first sub-pixel having a first side and a second side that is opposite the first side in a second direction that is different from the first direction, a second sub-pixel having a first side and a second side that is opposite the first side in the second direction, and a third sub-pixel having a first side and a second side that is opposite the first side in the second direction (See; Fig. 3 for PX1 having sub pixels GC, RC, BC and WC), wherein the second pixel includes a fourth sub-pixel having a first side and a second side that is opposite the first side in the second direction, a fifth sub-pixel having a first side and a second side that is opposite the first side in the second direction, and a sixth sub-pixel having a first side and a second side that is opposite the first side in the second direction (See; Fig. 3 for PX2 having sub pixels GC, RC, BC and WC), wherein the display panel further comprises a first driving circuit that is configured to drive the first sub-pixel, a second driving circuit that is configured to drive the second sub-pixel, a third driving circuit that is configured to drive the third sub-pixel, a fourth driving circuit that is configured to drive the fourth sub-pixel, a fifth driving circuit that is configured to drive the fifth sub-pixel, and a sixth driving circuit that is configured to drive the sixth sub-pixel (See; Figs. 2, 3 and p[0038] where the data driver may consist of a plurality of source drive ICS to supply data to a first node N1 and to drive transistor DT of each sub pixel). Shen fails to explicitly teach wherein the first driving circuit is disposed on the first side of the first sub-pixel in the second direction, the second driving circuit is disposed on the second side of the second sub-pixel in the second direction, and the third driving circuit is disposed on the first side the third sub-pixel in the second direction, wherein the fourth driving circuit is disposed on the second side of the fourth sub-pixel in the second direction, the fifth driving circuit is disposed on the first side of the fifth sub-pixel in the second direction, and the sixth driving circuit is disposed on the second of the sixth sub-pixel in the second direction (Shin teaches all driving circuits are on the same side of the sub pixels (See; Fig. 1)). However, Fletcher teaches the first sub-pixel, the second sub- pixel, and the third sub-pixel are sequentially arranged in the first direction (See; Fig. 3 where the sub pixels are sequentially arranged in the first direction), and the fourth, fifth and sixth sub pixel are sequentially arranged in the first direction (See; Fig. 3 where it is implied that additional subpixels for additional pixels would be sequentially arranged the same as the shown pixel); wherein the first driving circuit is disposed on the first side of the first sub-pixel in the second direction, the second driving circuit is disposed on the second side of the second sub-pixel in the second direction, and the third driving circuit is disposed on the first side the third sub-pixel in the second direction, wherein the fourth driving circuit is disposed on the second side of the fourth sub-pixel in the second direction, the fifth driving circuit is disposed on the first side of the fifth sub-pixel in the second direction, and the sixth driving circuit is disposed on the second side of the sixth sub-pixel in the second direction (See; Figs. 3, 5A and p[0036] where each sub pixel is driven by two drivers as driver pairs, each being on opposite sides of each sub pixel in a second direction). When JUNG is modified with the sequentially arranged sub pixels in the first direction of Fletcher, the claim is realized. In other words, since Jung supplies every other sub pixel with a different voltage from a different driver on opposite sides, if Jung’s pixels were arranged such as in Fletcher, every other sub pixels would be symmetrically supplied by a driver on any given side. Therefore it would have been obvious to one of ordinary skill in the art at the time of filing to modify JUNG to have sequentially arranged sub pixels in the first direction such as in of Fletcher as a mere design choice based on the pixel layout of the given display. In regards to claim 28, Shin fails to explicitly teach wherein the first gate line is disposed between the first sub-pixel and the first driving circuit, between the third sub-pixel and the third driving circuit, and between the fifth sub-pixel and the fifth driving circuit, and wherein the second gate line is disposed between the second sub-pixel and the second driving circuit, between the fourth sub-pixel and the fourth driving circuit, and between the sixth sub-pixel and the sixth driving circuit.
However, when Shin is combined with the paired drivers of Fletcher (See; Fig. 3 of Fletcher where each sub pixel is connected to a top and bottom driver), Shin teaches wherein the first gate line is between the first sub-pixel and the first driving circuit (See; Fig. 3 where GATE1 is between GC of PX1 and a bottom driver), between the third sub-pixel and the third driving circuit (See; Fig. 3 for GATE1 between GC of PX2 and a bottom driver), and between the fifth sub-pixel and the fifth driving circuit (See; Fig. 3 where GATE1 is between BC of PX2 and a bottom driver) and wherein the second gate line is between, the second sub-pixel and the second driving circuit (See; Fig. 3 for GATE2 between BC of PX1 and a top driver), between the fourth sub-pixel and the fourth driving circuit (See; Fig. 3 for GATE2 between GC of PX2 and a top driver) and the sixth sub-pixel and the sixth driving circuit (See; Fig. 3 for GATE2 between RC of PX2 and a bottom driver). When JUNG is modified with the sequentially arranged sub pixels in the first direction of Fletcher, the claim is realized. In other words, since Jung supplies every other sub pixel with a different voltage from a different driver on opposite sides, if Jung’s pixels were arranged such as in Fletcher, every other sub pixels would be symmetrically supplied by a driver on any given side. Therefore it would have been obvious to one of ordinary skill in the art at the time of filing to modify JUNG to have sequentially arranged sub pixels in the first direction such as in of Fletcher as a mere design choice based on the pixel layout of the given display.
Allowable Subject Matter
Claims 2-15 and 23-26 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Claims 2, 3, 11, 23 and 25 each recite that the driving circuits are asymmetrical in their placements on either side of the pixels.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONATHAN A BOYD whose telephone number is (571)270-7503. The examiner can normally be reached Mon - Fri 8:00 - 5:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ke Xiao can be reached at (571) 272-7776. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JONATHAN A BOYD/Primary Examiner, Art Unit 2627
Prosecution Insights