DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 4, 10, and 19 are objected to because of the following informalities:
At Line 10 of Claim 4: the recitation “inverting” requires a change to - - non-inverting - - to correct an essentially typographical error.
At Line 10 of Claim 10: the recitation “inverting” requires a change to - - non-inverting - - to correct an essentially typographical error.
At Line 11 of Claim 19: the recitation “inverting” requires a change to - - non-inverting - - to correct an essentially typographical error.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 – 4, 6, 14, 18 – 19, and 21 - 23 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Yin.
Regarding Claim 1, Lee discloses “A display compensation circuit, comprising: a generation circuit configured to output a first reference gamma voltage and a second reference gamma voltage” (Figure 5, Items Vref1, Vref2, and 520 (Notice that a circuit entity generates a first reference gamma voltage Vref1 and a second reference gamma voltage Vref2 that is applied to calculation circuit 520)), “and a calculation circuit electrically connected to the generation circuit and configured to: receive a power supply voltage signal, the first reference gamma voltage, and the second reference gamma voltage; and output a first gamma voltage signal and a second gamma voltage signal” (Figure 5, Item 520 ‘second voltage generating circuit’ (Notice that a calculation circuit 520 is electrically connected to the circuit entity and receives a power supply voltage ELVDD, the first reference gamma voltage Vref1, the second reference gamma voltage Vref2, and outputs a first gamma voltage signal Vgref21 and second gamma voltage signal Vgref22.)), “wherein the first gamma voltage signal is a voltage sum of the power supply voltage signal and the first reference gamma voltage” (Figure 6, Item 521 ‘first voltage correcting circuit’, and Column 9, Lines 27 - 29 (Notice that the first gamma voltage signal Vgref21 is a voltage sum of the power supply voltage ELVDD and the first reference gamma voltage Vref1.)), “and wherein the second gamma voltage signal is a voltage difference between the power supply voltage signal and the second reference gamma voltage” (Figure 7, Item 522 ‘second voltage correcting circuit’, and Column 9, Lines 55 – 57 (Notice that the second gamma voltage signal Vgref22 is a difference between the power supply voltage ELVDD and the second reference gamma voltage Vref2.)). However, Lee fails to explicitly disclose “wherein the generation circuit comprises: a signal generation sub-circuit, configured to output a reference voltage signal; and a voltage divider sub-circuit, electrically connected to the signal generation sub-circuit, and configured to perform voltage division on the reference voltage signal, to obtain the first reference gamma voltage and the second reference gamma voltage”.
In a similar field of endeavor, Yin teaches a generation circuit 110 (Figure 6) with signal generation sub-circuit 111 (signal generator) to output a refence voltage signal that is electrically connected to a voltage divider sub-circuit 112 (adjust sub-circuit) to perform voltage division on the output reference signal to create first and second reference gamma voltages among plural voltages ∆VG1 – ∆VG5.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide “wherein the generation circuit comprises: a signal generation sub-circuit, configured to output a reference voltage signal; and a voltage divider sub-circuit, electrically connected to the signal generation sub-circuit, and configured to perform voltage division on the reference voltage signal, to obtain the first reference gamma voltage and the second reference gamma voltage” because one having ordinary skill in the art would want to provide voltages for a calculation circuit (Paragraph [0047], Lines 8 – 17).
Regarding Claim 2, Lee and Yin, the combination of hereinafter referenced as LY, disclose/ teach everything claimed as applied above (See Claim 1). In addition, Lee discloses “wherein the calculation circuit comprises; an adder, electrically connected to the generation circuit, and configured to calculate the voltage sum” (Figure 6 (Notice that the first voltage correcting circuit 521 forms a non-inverting adding circuit connected to the generation circuit entity and configured to calculate the voltage sum between Vref1 and ELVDD.)), “and a subtractor, electrically connected to the generation circuit, and configured to calculate the voltage difference” (Figure 7 (Notice that the second voltage correcting circuit 522 forms a differential amplifying circuit connected to the generation circuit entity and configured to calculate the voltage different between Vref2 and ELVDD.)).
Regarding Claim 3, LY disclose/ teach everything claimed as applied above (See Claim 2). In addition, Lee discloses “wherein the adder comprises: a first resistor” (Figure 6, Item Ra2 ‘second resistance’), “a first operational amplifier comprising: an inverting input terminal; and output terminal; and a non-inverting input terminal electrically connected to the first resistor and configured to receive the power supply voltage signal through the first resistor” (Figure 6, Items OP1 ‘first amplifier’ (Notice a first operational amplifier OP1 comprising an inverting input terminal Na2, an output terminal Nao, and non-inverting input terminal Na1 configured to received power supply voltage ELVDD through the first resistor Ra2.)), “a second resistor connected between the generation circuit and the non-inverting input terminal” (Figure 6, Item Ra1 ‘first resistance’ (Notice that a second resistor Ra1 is connected between the generation circuit entity and the non-inverting terminal Na1.)), “a third resistor connected between a first voltage terminal and the inverting input terminal” (Figure 6, Item Ra4 ‘forth resistance’ (Notice that third resistor Ra4 is connected between a first ground voltage terminal and the inverting input Na2.)), “and a fourth resistor connected between the inverting input terminal and the output terminal” (Figure 6, Item Ra3 ‘third resistance’ (Notice that a fourth resistor Ra3 is connected between inverting input terminal Na2 and the output terminal Nao.)).
Regarding Claim 4, LY disclose/ teach everything claimed as applied above (See Claim 2). In addition, Lee discloses “wherein the subtractor comprises: a fifth resistor” (Figure 7, Item Rb4), “a sixth resistor” (Figure 7, Item Rb2), “a second operational amplifier comprising: an output terminal; an inverting input terminal; and a non-inverting input terminal electrically connected to the fifth resistor” (Figure 7, Items OP2 (Notice a second operational amplifier OP2 comprising an inverting input terminal Nb1, an output terminal Nbo, and non-inverting input terminal Nbt electrically connected to the fifth resistor Rb4.)), “wherein the fifth resistor is connected between a first voltage terminal and the non-inverting input terminal” (Figure 7 (Notice that fifth resistor Rb4 is between a first voltage terminal and non-inverting input terminal Nb2.)), “and, wherein the [non]inverting input terminal is electrically connected to the sixth resistor and configured to receive the power supply voltage signal through the sixth resistor” (Figure 7 (Notice that non-inverting input terminal Nb2 is electrically connected to the sixth resistor Rb2 and configured to receive power supply voltage ELVDD through resistor Rb2.)), “a seventh resistor connected between the generation circuit and the inverting input terminal” (Figure 7, Item Rb1 (Notice that seventh resistor Rb1 is connected between the generation circuit entity and the inverting input terminal Nb1.)), “an eighth resistor connected between the inverting input terminal and the output terminal” (Figure 7, Item Rb3 (Notice that eight resistor Rb3 is connected between the inverting input terminal Nb1 and output terminal Nbo.)).
Regarding Claim 6, LY disclose/ teach everything claimed as applied above (See Claim 1). In addition, Lee fails to explicitly disclose “wherein the voltage divider sub-circuit comprises: a first voltage divider resistor, a second voltage divider resistor disposed in series with the first voltage divider resistor, wherein the first voltage divider resistor and the second voltage divider resistor are connected between the signal generation sub-circuit and a second voltage terminal; a first output terminal connected between the first voltage divider resistor and the second voltage divider resistor and configured to output the first reference gamma voltage; and a second output terminal connected between the second voltage divider resistor and the second voltage terminal, and configured to output the second reference gamma voltage”. However, Yin teaches “wherein the voltage divider sub-circuit comprises: a first voltage divider resistor” (Figure 6, Item R1n (Notice that R1n provides a first divider resistor.)), “a second voltage divider resistor disposed in series with the first voltage divider resistor” (Figure 6, Item R11 (Notice that R11 provides a second divider resistor that is in series with first divider resistor R1n.)), “wherein the first voltage divider resistor and the second voltage divider resistor are connected between the signal generation sub-circuit and a second voltage terminal” (Figure 6 (Notice that first voltage divider resistor R1n and the second voltage divider resistor R11 are connected between the signal generation sub-circuit 111 and a second voltage terminal Vd1.)), “a first output terminal connected between the first voltage divider resistor and the second voltage divider resistor and configured to output the first reference gamma voltage;” (Figure 6 (Notice that a first output terminal outputting a first reference gamma voltage ∆VG5 is provided between the first voltage divider resistor R1n and the second voltage divider resistor R11.)), and a second output terminal connected between the second voltage divider resistor and the second voltage terminal, and configured to output the second reference gamma voltage” (Figure 6 (Notice that a second output terminal outputting a second reference gamma voltage ∆VG1 is provided between the second voltage divider resistor R11 and the second voltage terminal Vd1.)).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide “wherein the voltage divider sub-circuit comprises: a first voltage divider resistor, a second voltage divider resistor disposed in series with the first voltage divider resistor, wherein the first voltage divider resistor and the second voltage divider resistor are connected between the signal generation sub-circuit and a second voltage terminal; a first output terminal connected between the first voltage divider resistor and the second voltage divider resistor and configured to output the first reference gamma voltage; and a second output terminal connected between the second voltage divider resistor and the second voltage terminal, and configured to output the second reference gamma voltage because one having ordinary skill in the art would want to provide voltages for a calculation circuit (Paragraph [0047], Lines 8 – 17).
Regarding Claim 14, Lee discloses “A display module comprising: a display compensation circuit comprising: a generation circuit configured to output a first reference gamma voltage and a second reference gamma voltage” (Figures 1 and 5, Items Vref1, Vref2, and 520 (Notice that a display module is shown with compensation circuitry having circuit entity that generates a first reference gamma voltage Vref1 and a second reference gamma voltage Vref2 that is applied to calculation circuit 520)), “and a calculation circuit electrically connected to the generation circuit and least one source driver, wherein the calculation circuit is configured to: receive a power supply voltage signal, the first reference gamma voltage, and the second reference gamma voltage; and output a first gamma voltage signal and a second gamma voltage signal; and output a first gamma voltage signal and second gamma voltage signal to the at least one source driver” (Figure 5, Item 520 ‘second voltage generating circuit’ (Notice that a calculation circuit 520 is electrically connected to the circuit entity and receives a power supply voltage ELVDD, the first reference gamma voltage Vref1, the second reference gamma voltage Vref2, and outputs a first gamma voltage signal Vgref21 and second gamma voltage signal Vgref22. Also, notice that a first gamma voltage signal Vgref21 and second gamma voltage signal Vgref22 is output to at least on source driver as downstream outputs Vgn through Vg1 through circuits 530 and 540.)), “wherein the first gamma voltage signal is a voltage sum of the power supply voltage signal and the first reference gamma voltage” (Figure 6, Item 521 ‘first voltage correcting circuit’, and Column 9, Lines 27 - 29 (Notice that the first gamma voltage signal Vgref21 is a voltage sum of the power supply voltage ELVDD and the first reference gamma voltage Vref1.)), “and wherein the second gamma voltage signal is a voltage difference between the power supply voltage signal and the second reference gamma voltage” (Figure 7, Item 522 ‘second voltage correcting circuit’, and Column 9, Lines 55 – 57 (Notice that the second gamma voltage signal Vgref22 is a difference between the power supply voltage ELVDD and the second reference gamma voltage Vref2.)), “a display panel comprising data lines” (Figure 1, Item 110 ‘panel’ (Notice that one data line DL is shown of the plurality needed for multiple pixels.)), “and at least one source driver electrically connected to the display compensation circuit and the data lines and configured to: receive the first gamma voltage signal and the second gamma voltage signal from the display compensation circuit; and drive the data lines based on the first gamma voltage signal and the second gamma voltage signal” (Figures 1, 5, and Column 6, Lines 22 - 24 (Notice that a source driver downstream of the display compensation circuitry of Figure 5 applies Vgn through Vg1 as data voltage to data lines DL, where Vgn through Vg1 are based on first gamma reference signal Vgref21 and second gamma reference signal Vgref22 fed through gamma voltage generating device 500.)). In addition, Lee fails to explicitly disclose “wherein the generation circuit comprises: a signal generation sub-circuit, configured to output a reference voltage signal; and a voltage divider sub-circuit, electrically connected to the signal generation sub-circuit, and configured to perform voltage division on the reference voltage signal to obtain the first reference gamma voltage and the second reference gamma voltage”. However, Yin teaches a generation circuit 110 (Figure 6) with signal generation sub-circuit 111 (signal generator) to output a refence voltage signal that is electrically connected to a voltage divider sub-circuit 112 (adjust sub-circuit) to perform voltage division on the output reference signal to create first and second reference gamma voltages among plural voltages ∆VG1 – ∆VG5.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide “wherein the generation circuit comprises: a signal generation sub-circuit, configured to output a reference voltage signal; and a voltage divider sub-circuit, electrically connected to the signal generation sub-circuit, and configured to perform voltage division on the reference voltage signal, to obtain the first reference gamma voltage and the second reference gamma voltage” because one having ordinary skill in the art would want to provide voltages for a calculation circuit (Paragraph [0047], Lines 8 – 17).
Regarding Claim 18, LY disclose/teach everything claimed as applied above (See Claim 14). In addition, Lee discloses “wherein the calculation circuit comprises; an adder, electrically connected to the generation circuit, and configured to calculate the voltage sum” (Figure 6 (Notice that the first voltage correcting circuit 521 forms a non-inverting adding circuit connected to the generation circuit entity and configured to calculate the voltage sum between Vref1 and ELVDD.)), “wherein the adder comprises: a first resistor” (Figure 6, Item Ra2 ‘second resistance’), “a first operational amplifier comprising: an inverting input terminal; and output terminal; and a non-inverting input terminal electrically connected to the first resistor and configured to receive the power supply voltage signal through the first resistor” (Figure 6, Items OP1 ‘first amplifier’ (Notice a first operational amplifier OP1 comprising an inverting input terminal Na2, an output terminal Nao, and non-inverting input terminal Na1 configured to received power supply voltage ELVDD through the first resistor Ra2.)), “a second resistor connected between the generation circuit and the non-inverting input terminal” (Figure 6, Item Ra1 ‘first resistance’ (Notice that a second resistor Ra1 is connected between the generation circuit entity and the non-inverting terminal Na1.)), “a third resistor connected between a first voltage terminal and the inverting input terminal” (Figure 6, Item Ra4 ‘forth resistance’ (Notice that third resistor Ra4 is connected between a first ground voltage terminal and the inverting input Na2.)), “and a fourth resistor connected between the inverting input terminal and the output terminal” (Figure 6, Item Ra3 ‘third resistance’ (Notice that a fourth resistor Ra3 is connected between inverting input terminal Na2 and the output terminal Nao.)).
Regarding Claim 19, LY disclose/ teach everything claimed as applied above (See Claim 14). In addition, Lee discloses “wherein the subtractor comprises: a fifth resistor” (Figure 7, Item Rb4), “a sixth resistor” (Figure 7, Item Rb2), “a second operational amplifier comprising: an output terminal; an inverting input terminal; and a non-inverting input terminal electrically connected to the fifth resistor” (Figure 7, Items OP2 (Notice a second operational amplifier OP2 comprising an inverting input terminal Nb1, an output terminal Nbo, and non-inverting input terminal Nbt electrically connected to the fifth resistor Rb4.)), “wherein the fifth resistor is connected between a first voltage terminal and the non-inverting input terminal” (Figure 7 (Notice that fifth resistor Rb4 is between a first voltage terminal and non-inverting input terminal Nb2.)), “and, wherein the [non]inverting input terminal is electrically connected to the sixth resistor and configured to receive the power supply voltage signal through the sixth resistor” (Figure 7 (Notice that non-inverting input terminal Nb2 is electrically connected to the sixth resistor Rb2 and configured to receive power supply voltage ELVDD through resistor Rb2.)), “a seventh resistor connected between the generation circuit and the inverting input terminal” (Figure 7, Item Rb1 (Notice that seventh resistor Rb1 is connected between the generation circuit entity and the inverting input terminal Nb1.)), “an eighth resistor connected between the inverting input terminal and the output terminal” (Figure 7, Item Rb3 (Notice that eight resistor Rb3 is connected between the inverting input terminal Nb1 and output terminal Nbo.)).
Regarding Claim 21, LY disclose/ teach everything claimed as applied above (See Claim 14). In addition, Lee fails to explicitly disclose “wherein the voltage divider sub-circuit comprises: a first voltage divider resistor, a second voltage divider resistor disposed in series with the first voltage divider resistor, wherein the first voltage divider resistor and the second voltage divider resistor are connected between the signal generation sub-circuit and a second voltage terminal; a first output terminal connected between the first voltage divider resistor and the second voltage divider resistor and configured to output the first reference gamma voltage; and a second output terminal connected between the second voltage divider resistor and the second voltage terminal, and configured to output the second reference gamma voltage”. However, Yin teaches “wherein the voltage divider sub-circuit comprises: a first voltage divider resistor” (Figure 6, Item R1n (Notice that R1n provides a first divider resistor.)), “a second voltage divider resistor disposed in series with the first voltage divider resistor” (Figure 6, Item R11 (Notice that R11 provides a second divider resistor that is in series with first divider resistor R1n.)), “wherein the first voltage divider resistor and the second voltage divider resistor are connected between the signal generation sub-circuit and a second voltage terminal” (Figure 6 (Notice that first voltage divider resistor R1n and the second voltage divider resistor R11 are connected between the signal generation sub-circuit 111 and a second voltage terminal Vd1.)), “a first output terminal connected between the first voltage divider resistor and the second voltage divider resistor and configured to output the first reference gamma voltage;” (Figure 6 (Notice that a first output terminal outputting a first reference gamma voltage ∆VG5 is provided between the first voltage divider resistor R1n and the second voltage divider resistor R11.)), and a second output terminal connected between the second voltage divider resistor and the second voltage terminal, and configured to output the second reference gamma voltage” (Figure 6 (Notice that a second output terminal outputting a second reference gamma voltage ∆VG1 is provided between the second voltage divider resistor R11 and the second voltage terminal Vd1.)).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide “wherein the voltage divider sub-circuit comprises: a first voltage divider resistor, a second voltage divider resistor disposed in series with the first voltage divider resistor, wherein the first voltage divider resistor and the second voltage divider resistor are connected between the signal generation sub-circuit and a second voltage terminal; a first output terminal connected between the first voltage divider resistor and the second voltage divider resistor and configured to output the first reference gamma voltage; and a second output terminal connected between the second voltage divider resistor and the second voltage terminal, and configured to output the second reference gamma voltage because one having ordinary skill in the art would want to provide voltages for a calculation circuit (Paragraph [0047], Lines 8 – 17).
Regarding Claim 22, LY disclose/ teach everything claimed as applied above (See Claim 14). In addition, Lee discloses “wherein the at least one source driver is further configured to: generate a data voltage signal based on the first gamma voltage signal and the second gamma voltage signal; and transmit the data voltage signal to a pixel drive circuit of the display panel” (Figures 1, 5, and Column 6, Lines 22 - 24 (Notice that a source driver downstream of the display compensation circuitry of Figure 5 applies Vgn through Vg1 as data voltage to data lines DL (where the data voltage is transmitted to pixel drive circuits shown in Figure 2), where Vgn through Vg1 are based on first gamma reference signal Vgref21 and second gamma reference signal Vgref22 fed through gamma voltage generating device 500.)).
Regarding Claim 23, LY disclose/ teach everything claimed as applied above (See Claim 22). In addition, Lee discloses “wherein the data voltage signal compensates for a voltage drop of the power supply voltage signal received by the pixel drive circuit” (Column 4, Line 57 through Column 5, Line 5 (Notice the corrected data voltage (corrected via gamma correction) compensates for decreased ELVDD received by a driven pixel.)).
Claims 7 – 10, 12 – 13, 15 – 17 are rejected under 35 U.S.C. 103 as being unpatentable over Lee, in view of Yin, and further in view of Nam.
Regarding Claim 7, Lee discloses “A source circuit [ ], comprising: a generation circuit configured to output a first reference gamma voltage and a second reference gamma voltage” (Figure 5, Items Vref1, Vref2, and 520 (Notice that a circuit entity generates a first reference gamma voltage Vref1 and a second reference gamma voltage Vref2 that is applied to calculation circuit 520)), “and a calculation circuit electrically connected to the generation circuit and configured to: receive a power supply voltage signal, the first reference gamma voltage, and the second reference gamma voltage; and output a first gamma voltage signal and a second gamma voltage signal” (Figure 5, Item 520 ‘second voltage generating circuit’ (Notice that a calculation circuit 520 is electrically connected to the circuit entity and receives a power supply voltage ELVDD, the first reference gamma voltage Vref1, the second reference gamma voltage Vref2, and output a first gamma voltage signal Vgrer21 and second gamma voltage signal Vgref22.)), “wherein the first gamma voltage signal is a voltage sum of the power supply voltage signal and the first reference gamma voltage” (Figure 6, Item 521 ‘first voltage correcting circuit’, and Column 9, Lines 27 - 29 (Notice that the first gamma voltage signal Vgref21 is a voltage sum of the power supply voltage ELVDD and the first reference gamma voltage Vref1.)), “and wherein the second gamma voltage signal is a voltage difference between the power supply voltage signal and the second reference gamma voltage” (Figure 7, Item 522 ‘second voltage correcting circuit’, and Column 9, Lines 55 – 57 (Notice that the second gamma voltage signal Vgref22 is a difference between the power supply voltage ELVDD and the second reference gamma voltage Vref2.)) However, Lee fails to disclose “wherein the generation circuit comprises: a signal generation sub-circuit, configured to output a reference voltage signal; and a voltage divider sub-circuit, electrically connected to the signal generation sub-circuit, and configured to perform voltage division on the reference voltage signal to obtain the first reference gamma voltage and the second reference gamma voltage” and where the source circuit is mounted or is provided on a “board”.
In a similar field of endeavor, Yin teaches a generation circuit 110 (Figure 6) with signal generation sub-circuit 111 (signal generator) to output a refence voltage signal that is electrically connected to a voltage divider sub-circuit 112 (adjust sub-circuit) to perform voltage division on the output reference signal to create first and second reference gamma voltages among plural voltages ∆VG1 – ∆VG5.
Also, in a similar field of endeavor, Nam teaches providing a source board 171 for a display device and control board 172 by which circuity for power delivery AVDD and gamma voltage VGMA are generated/delivered (Figures 1, 2, and Paragraphs [0056], [0058], and [0059]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide “wherein the generation circuit comprises: a signal generation sub-circuit, configured to output a reference voltage signal; and a voltage divider sub-circuit, electrically connected to the signal generation sub-circuit, and configured to perform voltage division on the reference voltage signal, to obtain the first reference gamma voltage and the second reference gamma voltage” because one having ordinary skill in the art would want to provide voltages for a calculation circuit (Paragraph [0047], Lines 8 – 17). Furthermore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide where the source circuit is on a “board” because one having ordinary skill in the art would want to provide physical stability for the operation of a circuit.
Regarding Claim 8, Lee, Yin, and Nam, the combination of hereinafter referenced as LYN, disclose/ teach everything claimed as applied above (See Claim 7). In addition, Lee discloses “wherein the calculation circuit comprises; an adder, electrically connected to the generation circuit, and configured to calculate the voltage sum” (Figure 6 (Notice that the first voltage correcting circuit 521 forms a non-inverting adding circuit connected to the generation circuit entity and configured to calculate the voltage sum between Vref1 and ELVDD.)), “and a subtractor, electrically connected to the generation circuit, and configured to calculate the voltage difference” (Figure 7 (Notice that the second voltage correcting circuit 522 forms a differential amplifying circuit connected to the generation circuit entity and configured to calculate the voltage different between Vref2 and ELVDD.)).
Regarding Claim 9, LYN disclose/ teach everything claimed as applied above (See Claim 8). In addition, Lee discloses “wherein the adder comprises: a first resistor” (Figure 6, Item Ra2 ‘second resistance’), “a first operational amplifier comprising: an inverting input terminal; and output terminal; and a non-inverting input terminal electrically connected to the first resistor and configured to receive the power supply voltage signal through the first resistor” (Figure 6, Items OP1 ‘first amplifier’ (Notice a first operational amplifier OP1 comprising an inverting input terminal Na2, an output terminal Nao, and non-inverting input terminal Na1 configured to received power supply voltage ELVDD through the first resistor Ra2.)), “a second resistor connected between the generation circuit and the non-inverting input terminal” (Figure 6, Item Ra1 ‘first resistance’ (Notice that a second resistor Ra1 is connected between the generation circuit entity and the non-inverting terminal Na1.)), “a third resistor connected between a first voltage terminal and the inverting input terminal” (Figure 6, Item Ra4 ‘forth resistance’ (Notice that third resistor Ra4 is connected between a first ground voltage terminal and the inverting input Na2.)), “and a fourth resistor connected between the inverting input terminal and the output terminal” (Figure 6, Item Ra3 ‘third resistance’ (Notice that a fourth resistor Ra3 is connected between inverting input terminal Na2 and the output terminal Nao.)).
Regarding Claim 10, LYN disclose/ teach everything claimed as applied above (See Claim 8). In addition, Lee discloses “wherein the subtractor comprises: a fifth resistor” (Figure 7, Item Rb4), “a sixth resistor” (Figure 7, Item Rb2), “a second operational amplifier comprising: an output terminal; an inverting input terminal; and a non-inverting input terminal electrically connected to the fifth resistor” (Figure 7, Items OP2 (Notice a second operational amplifier OP2 comprising an inverting input terminal Nb1, an output terminal Nbo, and non-inverting input terminal Nbt electrically connected to the fifth resistor Rb4.)), “wherein the fifth resistor is connected between a first voltage terminal and the non-inverting input terminal” (Figure 7 (Notice that fifth resistor Rb4 is between a first voltage terminal and non-inverting input terminal Nb2.)), “and, wherein the [non]inverting input terminal is electrically connected to the sixth resistor and configured to receive the power supply voltage signal through the sixth resistor” (Figure 7 (Notice that non-inverting input terminal Nb2 is electrically connected to the sixth resistor Rb2 and configured to receive power supply voltage ELVDD through resistor Rb2.)), “a seventh resistor connected between the generation circuit and the inverting input terminal” (Figure 7, Item Rb1 (Notice that seventh resistor Rb1 is connected between the generation circuit entity and the inverting input terminal Nb1.)), “an eighth resistor connected between the inverting input terminal and the output terminal” (Figure 7, Item Rb3 (Notice that eight resistor Rb3 is connected between the inverting input terminal Nb1 and output terminal Nbo.)).
Regarding Claim 12, LYN disclose/ teach everything claimed as applied above (See Claim 5). In addition, Lee and Nam fail to explicitly disclose “wherein the voltage divider sub-circuit comprises: a first voltage divider resistor, a second voltage divider resistor disposed in series with the first voltage divider resistor, wherein the first voltage divider resistor and the second voltage divider resistor are connected between the signal generation sub-circuit and a second voltage terminal; a first output terminal connected between the first voltage divider resistor and the second voltage divider resistor and configured to output the first reference gamma voltage; and a second output terminal connected between the second voltage divider resistor and the second voltage terminal, and configured to output the second reference gamma voltage”. However, Yin teaches “wherein the voltage divider sub-circuit comprises: a first voltage divider resistor” (Figure 6, Item R1n (Notice that R1n provides a first divider resistor.)), “a second voltage divider resistor disposed in series with the first voltage divider resistor” (Figure 6, Item R11 (Notice that R11 provides a second divider resistor that is in series with first divider resistor R1n.)), “wherein the first voltage divider resistor and the second voltage divider resistor are connected between the signal generation sub-circuit and a second voltage terminal” (Figure 6 (Notice that first voltage divider resistor R1n and the second voltage divider resistor R11 are connected between the signal generation sub-circuit 111 and a second voltage terminal Vd1.)), “a first output terminal connected between the first voltage divider resistor and the second voltage divider resistor and configured to output the first reference gamma voltage;” (Figure 6 (Notice that a first output terminal outputting a first reference gamma voltage ∆VG5 is provided between the first voltage divider resistor R1n and the second voltage divider resistor R11.)), and a second output terminal connected between the second voltage divider resistor and the second voltage terminal, and configured to output the second reference gamma voltage” (Figure 6 (Notice that a second output terminal outputting a second reference gamma voltage ∆VG1 is provided between the second voltage divider resistor R11 and the second voltage terminal Vd1.)).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide “wherein the voltage divider sub-circuit comprises: a first voltage divider resistor, a second voltage divider resistor disposed in series with the first voltage divider resistor, wherein the first voltage divider resistor and the second voltage divider resistor are connected between the signal generation sub-circuit and a second voltage terminal; a first output terminal connected between the first voltage divider resistor and the second voltage divider resistor and configured to output the first reference gamma voltage; and a second output terminal connected between the second voltage divider resistor and the second voltage terminal, and configured to output the second reference gamma voltage because one having ordinary skill in the art would want to provide voltages for a calculation circuit (Paragraph [0047], Lines 8 – 17)
Regarding Claim 13, LYN disclose/ teach everything claimed as applied above (See Claim 7). In addition, Lee discloses “comprising a time sequence controller” (Figure 1, Item 140, and Column 4, Lines 44 – 45), but fails to explicitly disclose where the time sequence controller is “electrically connected to the signal generation sub-circuit, and configured to control the signal generation sub-circuit to output the reference voltage control signal”. However, Lee teaches where control signals are sent to a data driving device 120 (Figure 1) to provide display control, where gamma voltage generating device 500 is part of data driving display device (Column 6, Lines 47 – 49).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide where the time sequence controller is “electrically connected to the signal generation sub-circuit, and configured to control the signal generation sub-circuit to output the reference voltage control signal” because one having ordinary skill in the art would want to provide reference voltages with timing to enable display operation.
Regarding Claim 15, LYN disclose/ teach everything claimed as applied above (See Claim 14). In addition, Lee discloses “a source circuit [ ], wherein the source circuit [ ] comprises the display compensation circuit” (Figures 1 and 5 (Notice the source circuity is within data driving device 120 where gamma voltage generating circuit (compensation circuit) is also part of the data display driving device (Column 6, Lines 47 – 49).)). However, Lee fails to disclose where the source circuit is mounted or is provided on a “board”. However, Nam teaches providing a source board 171 for a display device and control board 172 by which circuity for power delivery AVDD and gamma voltage VGMA are generated/delivered (Figures 1, 2, and Paragraphs [0056], [0058], and [0059]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide where the source circuit is on a “board” because one having ordinary skill in the art would want to provide physical stability for the operation of a circuit.
Regarding Claim 16, LYN disclose/ teach everything claimed as applied above (See Claim 15). In addition, LN fail to explicitly disclose “wherein the generation circuit comprises: a signal generation sub-circuit and a voltage divider sub-circuit”. However, Yin teaches a generation circuit 110 (Figure 6) with signal generation sub-circuit 111 (signal generator) to output a refence voltage signal that is electrically connected to a voltage divider sub-circuit 112 (adjust sub-circuit) to perform voltage division on the output reference signal to create first and second reference gamma voltages among plural voltages ∆VG1 – ∆VG5.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide “wherein the generation circuit comprises: a signal generation sub-circuit and a voltage divider sub-circuit” because one having ordinary skill in the art would want to provide voltages for a calculation circuit (Paragraph [0047], Lines 8 – 17).
Regarding Claim 17, LYN disclose/ teach everything claimed as applied above (See Claim 16). In addition, Lee discloses “wherein the source circuit [ ] further comprises a time sequence controller” (Figure 1, Item 140, and Column 4, Lines 44 – 45), but fails to explicitly disclose where the time sequence controller is “electrically connected to the signal generation sub-circuit, and configured to control the signal generation sub-circuit to output the reference voltage control signal”. However, Lee teaches where control signals are sent to a data driving device 120 (Figure 1) to provide display control, where gamma voltage generating device 500 is part of data driving display device (Column 6, Lines 47 – 49).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide where the time sequence controller is “electrically connected to the signal generation sub-circuit, and configured to control the signal generation sub-circuit to output the reference voltage control signal” because one having ordinary skill in the art would want to provide reference voltages with timing to enable display operation.
Response to Applicants Amendments and Arguments
Applicants amendments and arguments filed September 08, 2026 have been fully considered.
First, the amendments to each of Claims 4, 10, and 19 have overcome the rejections of Claims 4, 10, and 19 under 35 U.S.C. 112(b) as set forth and made record in the Office Action mailed July 13, 2026.
Second, the amendments to each of Claims 1, 7, and 14 have overcome the rejections of Claims 1 – 3, 14, and 18 under 35 U.S.C. 102(a)(1) as set forth and made of record in the Office Action mailed July 13, 2026.
Third, the Examiner disagrees that - - Yin does not disclose that the adjustment sub-circuit 112 performs voltage division on a reference voltage signal to obtain a first reference gamma voltage and second reference gamma voltage - - (REMARKS, Page 15, last three lines of page). The Examiner disagrees because the sub-circuit 112 performs voltage division to obtain first and second gamma compensation voltages among ∆VG1 – ∆VG5 (i.e. ∆(change or difference) V (voltage) G (gamma)).
Finally, the Examiner disagrees that - - there would be no apparent reason to combine Yin’s voltage-divider circuit with Lee - - (REMARKS, Page 17, Lines 3 – 4) and disagrees that the proposed combination - - does not bridge the gap because Yin’s paragraph 47 itself distinguishes the voltage compensation amounts output by the generation circuit from the reference gamma voltages received by the calculation circuit - - (REMARKS, Page 17, Lines 19 – 21). The Examiner disagrees because an apparent reason for combination was provided in the obviousness rejections of previous claims 5, 11, and 20 (amended claims 1, 7, and 14) and the proposed combinations meet the claim limitations (i.e. bridges the gap) because gamma compensation voltages ∆VG1 – ∆VG5 are not excluded by the terminology “reference gamma voltage” of claims 5, 11, and 20 (amended claims 1, 7, and 14).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIAN M BUTCHER whose telephone number is (571)270-5575. The examiner can normally be reached on Monday – Friday from 6:30 AM to 3:00 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Ke Xiao, can be reached at (571) 272 - 7776. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BRIAN M BUTCHER/Primary Examiner, Art Unit 2627 September 29, 2026
