DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5, 7 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 2020/0185481 A1) in view of Li et al. (US 2019/0392768 A1).
As to claim 1, Park et al. teaches a display panel ([0002]: display), comprising a plurality of subpixels ([0010]: pixels), a subpixel comprising a light emitting element ([0076]: light emitting diode), and a pixel driving circuit ([0076]: transistors , capacitors); wherein the display panel comprises: a plurality of light emitting elements ([0076]: light emitting diode (OLED), Fig. 1); and an interconnected first voltage supply network configured to provide a first voltage signal (ELVSS in Fig. 1) to cathodes of the plurality of light emitting elements ([0076];[0084]: driving low voltage lines 156 and 196 apply the driving low voltage ELVSS, driving low voltage ELVSS is applied to the cathode electrode of the OLED); wherein the interconnected first voltage supply network comprises signal lines in a display area of the display panel ([0076];[0084]: driving low voltage lines 156 and 196), the signal lines comprise a plurality of first low voltage signal lines in a first signal line layer and a plurality of second low voltage signal lines in a second signal line layer ([0084]: driving low voltage lines 156 and 196 include wiring extending in a horizontal direction and wiring extending in a longitudinal direction, the layers of the wiring extending in the horizontal direction and the wiring extending in the longitudinal direction are different from each other, Figs. 3-4); the plurality of first low voltage signal lines respectively cross over the plurality of second low voltage signal lines ([0084]: driving low voltage lines 156 and 196 include wiring extending in a horizontal direction and wiring extending in a longitudinal direction, Fig. 3); the display panel further comprises a planarization layer (14 in Fig. 4) between the plurality of first low voltage signal lines (156 in Fig. 4) and the plurality of second low voltage signal lines (196 in Fig. 4;[0076];[0133];[0139]); the plurality of first low voltage signal lines (156 in Figs. 1, 3-4) are electrically connected to the plurality of second low voltage signal lines (196 in Figs. 1, 3-4; [0076]; [0084]: driving low voltage lines 156 and 196 apply the driving low voltage ELVSS, Fig. 1;[0121];[0129]: connection between driving low voltage line 196 and driving low voltage line 156); and an orthographic projection of an anode of at least a light emitting element (201 in Fig. 4) of the plurality of light emitting elements on a base substrate ([0076];[0112]: substrate) at least partially overlaps with an orthographic projection of a second low voltage signal line ([0084]: driving low voltage line 196) of the plurality of second low voltage signal lines on the base substrate ([0112];[0146]: anode 201 overlaps the second driving low voltage line 196, Figs. 3-4), but does not explicitly disclose the display area being at least partially surrounded by a peripheral area, wherein the display panel further comprises a second peripheral low voltage signal line and a third peripheral low voltage signal line in the peripheral area; at least one of the plurality of second low voltage signal lines is electrically connected to the second peripheral low voltage signal line; the second peripheral low voltage signal line is electrically connected to the third peripheral low voltage signal line; and the third peripheral low voltage signal line is electrically connected to an integrated circuit.
However, Li et al. teaches the display area being at least partially surrounded by a peripheral area ([0084]: peripheral area; Figs. 4-5 show the display area (pixel regions 41) being at least partially surrounded by a peripheral area in which lines 431 and 432 are coupled to controller 42),
wherein the display panel further comprises a second peripheral low voltage signal line and a third peripheral low voltage signal line in the peripheral area ([0044]: plurality of second power signal lines 432. One interpretation is a power signal line 432 is a second peripheral low voltage signal line and another power signal line 432 is a third peripheral low voltage signal line; [0084]: the lines are coupled to the controller in the peripheral area, Fig. 5; note that a second alternative interpretation is the slanted line portion of line 432 is a second peripheral low voltage line and the vertical portion of line 432 is a third peripheral low voltage signal line as shown in Fig. 5 below);
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at least one of the plurality of second low voltage signal lines ([0057];[0065]: as illustrated in FIG. 5, ELVSS1 represents that the cathodes 412 in that pixel region 41 are each coupled to a same second power signal line ELVSS1, ELVSS2 represents that the cathodes 412 in that pixel region 41 are each coupled to a same second power signal line ELVSS2, and so on) is electrically connected to the second peripheral low voltage signal line (Figs. 5-6;[0057]: the cathodes 412 in the display panel 410 are each coupled to second power signal line 432 , the second power signal line is coupled to the controller 42, and a low voltage level signal is input to the second power signal line ELVSS),
the second peripheral low voltage signal line is electrically connected to the third peripheral low voltage signal line ([0044]: power signal lines 432, note the claim does not recite “directly” connected; Fig. 5 shows one power signal line 432 is connected to another power signal line 432 through controller 42. A second alternative interpretation is the slanted line portion of line 432 (i.e. the second peripheral low voltage line) and the vertical portion of line 432 (i.e. third peripheral low voltage signal line) are connected to each other as shown in Fig. 5;[0093]: controller 42 is coupled with the plurality of power signal lines); and
the third peripheral low voltage signal line is electrically connected to an integrated circuit ([0047]; controller 42 is a driver IC; [0093]: controller 42 is coupled with the plurality of power signal lines, Fig. 5 shows the vertical portion of line 432 is connected to controller 42 which is a driver IC).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Park et al. such that the display area being at least partially surrounded by a peripheral area , wherein the display panel further comprises a second peripheral low voltage signal line and a third peripheral low voltage signal line in the peripheral area, at least one of the plurality of second low voltage signal lines is electrically connected to the second peripheral low voltage signal line, the second peripheral low voltage signal line is electrically connected to the third peripheral low voltage signal line, and the third peripheral low voltage signal line is electrically connected to an integrated circuit as taught by Li et al. in order to alleviate trail phenomenon.
As to claim 2, Park et al. in view of Li et al. teaches the display panel of claim 1, further comprising an interconnected second voltage supply network configured to provide a second voltage signal to a plurality of pixel driving circuits (Park et al., Fig. 1;[0084]: driving voltage lines 155 and 195 apply a driving voltage ELVDD); wherein the interconnected second voltage supply network comprises a plurality of first high voltage signal lines (Park et al., 155 in Figs. 1, 3-4;[0084]) and a plurality of second high voltage signal lines (Park et al., 195 in Figs. 1, and 3-5;[0084]) ; and the plurality of second high voltage signal lines are in the second signal line layer (Park et al., Figs. 4-5 show second high voltage signal lines 195 is in the same layer 15 as 196;[0054]) . As to claim 3, Park et al. in view of Li et al. teaches the display panel of claim 2, wherein the plurality of second high voltage signal lines (Park et al., 195 in Figs. 1, and 3-5;[0084]) are connected to the plurality of first high voltage signal lines (Park et al., 155 in Figs. 1, 3-4;[0084]) through a plurality of first vias (Park et al., vias 82, 83 in Fig. 4;[0128]); the plurality of second low voltage signal lines(Park et al., 196 in Figs. 1, 3-4; [0076]; [0084]: driving low voltage lines 156 and 196 apply the driving low voltage ELVSS, Fig. 1; [0129]; [0137]; connection between driving low voltage line 196 and driving low voltage line 156) are connected to the plurality of first low voltage signal lines (Park et al., 156 in Figs. 1, 3-4) through a plurality of second vias (Park et al., two vias 87 in Fig. 4;[0137]); and the plurality of first vias (Park et al., vias 82, 83 in Fig. 4;[0128]) and the plurality of second vias (Park et al., two vias 87 in Fig. 4;[0137]) are in a same layer (Park et al., [0123];[0132-0133]: inorganic insulating layer). As to claim 4, Park et al. in view of Li et al. teaches the display panel of claim 2, further comprising a node connecting line (Park et al., [0127]: storage electrode 174); wherein the node connecting line (Park et al., [0127]: storage electrode 174) is connected to a gate electrode of a driving transistor in the pixel driving circuit (Park et al., [0127]: storage electrode 174 is connected to the second electrode (the output side electrode) of the driving transistor T1 which is connected to gate electrode of transistor T1 as shown in Fig. 1: note that the claim does not recite “directly connected”. All of the elements in Fig. 1 are connected to each other); and the plurality of first high voltage signal lines (Park et al., 155 in Figs. 1, 3-4;[0084]) are in a same layer as the node connecting line (Park et al., storage electrode 174; [0127]: through openings 63, 61, and 66, Fig. 4), and are insulated from the node connecting line(Park et al., [0127]: storage electrode 174;[0123]: insulating layer 13 covers voltage signal lines 155). As to claim 5, Park et al. in view of Li et al. teaches the display panel of claim 2, wherein an orthographic projection of the plurality of first high voltage signal lines (Park et al., 155 in Figs. 1, 3-4;[0084]) on the base substrate at least partially overlaps with an orthographic projection of a second capacitor electrode of a storage capacitor (Park et al., [0127]: storage electrode 174, Fig. 4) in the pixel driving circuit on the base substrate (Park et al., [0112]: substrate 110, Fig. 4); the orthographic projection of the second capacitor electrode (Park et al., [0127]: storage electrode 174, Fig. 4) on the base substrate (Park et al., [0112]: substrate 110, Fig. 4) covers an orthographic projection of a first capacitor electrode of the storage capacitor (Park et al., [0127]: extension part of the storage electrode 174 overlaps the gate electrode 154 (first capacitor electrode) to form the storage capacitor Cst) in the pixel driving circuit on the base substrate (Park et al., [0112]: substrate 110, Fig. 4) except for a hole region (Park et al., Fig. 4, hole region 62) in which a portion of the second capacitor electrode is absent (Park et al., [0127]; storage electrode 174 is absent, Fig. 4); and the orthographic projection of the plurality of first high voltage signal lines (Park et al., 155 in Fig. 4;[0084]) on the base substrate (Park et al., [0112]: substrate 110, Fig. 4) is non-overlapping with an orthographic projection of the hole region (Park et al., Fig. 4, hole region 62) on the base substrate (Park et al., [0112]: substrate 110, Fig. 4).
As to claim 7, Park et al. in view of Li et al. teaches the display panel of claim 2, wherein an orthographic projection of the plurality of first high voltage signal lines (Park et al., 155 in Fig. 4;[0084]) on the base substrate (Park et al., [0112]: substrate 110, Fig. 4) at least partially overlaps with an orthographic projection of a first capacitor electrode of a storage capacitor (Park et al., [0127]: storage electrode 174, Fig. 4) in the pixel driving circuit on the base substrate (Park et al., [0112]: substrate 110, Fig. 4).
As to claim 18, Park et al. teaches a display apparatus ([0002]), comprising the display panel as discussed above, but does not explicitly disclose one or more integrated circuits connected to the display panel.
However, Li et al. teaches one or more integrated circuits connected to the display panel ([0047]; controller 42 is a driver IC; [0093]: controller 42 is coupled with the plurality of power signal lines, Fig. 5).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Park et al. such that one or more integrated circuits are connected to the display panel as taught by Li et al. in order to achieve a driving function.
Claim(s) 6 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 2020/0185481 A1) in view of Li et al. (US 2019/0392768 A1) and further in view of Kim et al. (US 2020/0105849 A1).
As to claim 6, Park et al. in view of Li et al. teaches the display panel as discussed above, but does not explicitly disclose wherein an orthographic projection of the plurality of first high voltage signal lines on the base substrate at least partially overlaps with an orthographic projection of a gate electrode of a driving transistor in the pixel driving circuit on the base substrate.
However, Kim et al. teaches wherein an orthographic projection of the plurality of first high voltage signal lines (PL3 in Fig. 13, [0102]: PL3 supplies power voltage ELVDD) on the base substrate (SUB in Fig. 13; [0063]) at least partially overlaps with an orthographic projection of a gate electrode of a driving transistor (GE1 in Fig. 13; [0119]) in the pixel driving circuit on the base substrate (SUB in Fig. 13; [0063]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Park et al. in view of Li et al. such that an orthographic projection of the plurality of first high voltage signal lines on the base substrate at least partially overlaps with an orthographic projection of a gate electrode of a driving transistor in the pixel driving circuit on the base substrate as taught by Kim et al. in order to provide a display device with improved luminance uniformity.
As to claim 8, Park et al. in view of Li et al. teaches the display panel as discussed above, further comprising at least a reset signal line configured to provide a reset signal to a gate electrode of a driving transistor of the pixel driving circuit or an anode of the light emitting clement (Park et al., [0092]: initialization voltage line 173 applies the initialization voltage Vint to initialize the voltage of the anode); but does not explicitly disclose wherein at least a portion of the reset signal line is in a semiconductor material layer.
However, Kim et al. teaches wherein at least a portion of the reset signal line is in a semiconductor material layer ([0228]: first initialization line VIL1 includes a semiconductor layer).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Park et al. in view of Li et al. such that at least a portion of the reset signal line is in a semiconductor material layer as taught by Kim et al. in order to provide a display device with improved luminance uniformity.
Allowable Subject Matter
Claims 9-17 and 19 are allowed.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 -8 and 18 have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STACY KHOO whose telephone number is (571)270-3698. The examiner can normally be reached Mon-Fri 8:00 am-5:00 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Eason can be reached at 571-270-7230. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/STACY KHOO/Primary Examiner, Art Unit 2624
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