DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 4-7, 10-14, 16-17 and 19-20 is/are rejected under 35 U.S.C. 102a1 as being anticipated by US Patent Pub. 2015/0138254 A1 to Nakayama.
As to claim 1, Nakayama discloses a method for receiving at least one signal in a data driving device, the method comprising:
receiving a logic level signal at a first transmission rate, from a data processing device (Figure 1, the “Drive Controller 11” / “data processing device” of the Claim provides signals to the “Data Driver 13” / “data driving device” of the Claim. Figure 2 shows the “logic levels.” The “plurality of communication lines” are shown in Figure 4 as the various signal lines coming from the “Data Driver 11” to the “Data Driver 13” whose structure is shown in Figure 4: PW1, VPD, STB, PW2, POL. The “Logic Level” is taught by PW1: “[0018] … As illustrated in FIG. 2, when the period switches from the data scanning period SP to the blanking period BP, the drive controller 11 supplies to the data driver 13 a power switch signal PW1 of logic level 0 that is, for example, to stop power supply for a predetermined power stop period T1 starting at the moment of switchover….”] [The first and second transmission rates indicate low and normal power modes and during the PW1=0 the power supply is stopped and the device enters the low power mode.] [Additionally, the “logic levels” of ON and OFF in Figure 2 are a much longer period (lower frequency) and thus lower transmission rate than the STB and VPD signals.);
receiving a training signal, from the data processing device (the “training signal” is taught by TLD of Figure 2 which occurs during the Blanking Period (BP): “[0018] … As illustrated in FIG. 2, when the period switches from the data scanning period SP to the blanking period BP, the drive controller 11 supplies to the data driver 13 a power switch signal PW1 of logic level 0 that is, for example, to stop power supply for a predetermined power stop period T1 starting at the moment of switchover…. As illustrated in FIG. 2, when the power stop period T1 has elapsed from the start time of the blanking period BP, the drive controller 11 starts generating the pixel data sequence signal VPD including a data sequence TLD for clock synchronization training which includes a dummy pixel data sequence and the above-described reference timing signal superimposed thereon. The generated pixel data sequence signals VPD are supplied to the data driver 13.”); and
receiving an image signal at a second transmission rate, from the data processing device (Figure 2, the PW1 logic level 0 at some point and PW1 returns to logic level 1 which teaches the “completion of training” of the Claim. TP1= Training Period and once TP1 ends TP2 which is the training period for the “source voltage stabilizing” begins but TP1 and TP2 can overlap, as shown in Figure 5, and end together. After TP1 (and TP2) end, the application Hs (Horizontal Scanning Pulses) begins which has a different frequency from the “logic level signal.” The “second transmission rate” pertains to the STB or VPD both of which come at a much faster rate than the Logic Level signals of PW1 and PW2. Additionally, the period (inverse of transmission rate) of the Hs is shortened after the training periods (TP1 and TP2) (meaning that transmission rate is increased): “[0018] …The cycle of strobe pulses SB in the strobe signal STB is equal to the horizontal scanning cycle Hs of horizontal scanning pulses (described later), which are applied to drive the display unit 20…. As illustrated in FIG. 2, when the period switches from the data scanning period SP to the blanking period BP, the drive controller 11 supplies to the data driver 13 a power switch signal PW1 of logic level 0 that is, for example, to stop power supply for a predetermined power stop period T1 starting at the moment of switchover. The drive controller 11 then returns the power switch signal PW1 to the state of the logic level 1. …” “[0038] Accordingly, as illustrated in FIG. 2, a training period TP1 including a clock stabilizing period is placed immediately before the transition to the next frame display period in each frame display period, and the drive controller 11 controls the CDR circuit 130 to restart operation in this training period TP1….” “[0035] Further, the horizontal scanning cycle Hs for scanning the horizontal scan lines S.sub.1 to S.sub.m of the display unit 20 is shortened in order to secure the power stop period (T1, T2) within the blanking period BP as illustrated in FIG. 2. This makes it possible to secure the power stop period (T1, T2) within the blanking period BP without extending the frame display period. If, for example, the frame display period is set at 1/30 sec and the horizontal scanning cycle Hs is shortened and the data scanning period SP is set at 1/60 sec, the remaining 1/60 sec can be used as the blanking period BP, and hence the power stop period can be set within this 1/60 sec.”] [The first and second transmission rates indicate low and normal power modes and during the PW1=1 the power supply is reconnected and image data start being transmitted and received.),
wherein the first transmission rate for the logic level signal is lower than the second transmission rate for the image signal (the period of the Horizontal Scanning Pulses (Hs) is shortened (the pulses are made faster) in order to open room for the blanking (training) periods: “[0035] Further, the horizontal scanning cycle Hs for scanning the horizontal scan lines S.sub.1 to S.sub.m of the display unit 20 is shortened in order to secure the power stop period (T1, T2) within the blanking period BP as illustrated in FIG. 2. This makes it possible to secure the power stop period (T1, T2) within the blanking period BP without extending the frame display period. If, for example, the frame display period is set at 1/30 sec and the horizontal scanning cycle Hs is shortened and the data scanning period SP is set at 1/60 sec, the remaining 1/60 sec can be used as the blanking period BP, and hence the power stop period can be set within this 1/60 sec.”), wherein the data at the second transmission rate comprises image data (Nakayama is directed to “Driving Device for Driving a Display” and the Hs are cycle for the video data signals of Figures 2 and 5 are Hs for generating image: “[0032] … The data driver applies the pixel drive voltages respectively corresponding to the luminance levels of each pixel based on the video data signal to the data lines (D.sub.1 to D.sub.n) in each horizontal scanning cycle (Hs) within the data scanning period.” “[0029] As illustrated in FIG. 2, during the data scanning period SP in each of the frame display periods in the display unit 20, scanning pulses synchronized with the strobe pulses SB.sub.1 to SB.sub.m are sequentially applied to the scan lines S.sub.1 to S.sub.m in an alternative way. As a result, a picture corresponding to the pixel drive voltages G.sub.1 to G.sub.n is displayed one scan line at a time in order.”).
As to claim 2, Nakayama discloses wherein the logic level has a first signal level (PW1 is a logical level 1 during the ON period), the image signal has a second signal level (SB1-SBm are pulses at a high signal level from a low signal level), and the first signal level is higher than the second signal level (PW1 is constant at a high level and is intermittently higher than the low levels between the SB1-SBm.).
As to claim 4, Nakayama discloses wherein the data driving device receives the logic level signal in a low power mode (Figures 2 and 5, the PW1/PW2 at logic level 0 corresponds to stop of power supply / “low power mode” of the Claim: “[0018] … In the data scanning period SP, as illustrated in FIG. 2, the drive controller 11 generates power switch signals PW1 and PW2 having, e.g., a logic level of 1 to assert continued power supply. The signals PW1 and PW2 are supplied to the data driver 13. As illustrated in FIG. 2, when the period switches from the data scanning period SP to the blanking period BP, the drive controller 11 supplies to the data driver 13 a power switch signal PW1 of logic level 0 that is, for example, to stop power supply for a predetermined power stop period T1 starting at the moment of switchover.).
As to claim 5, Nakayama discloses wherein the data driving device converts from the low power mode to a normal mode, in response to receiving the logic level signal (Figures 2 and 5, the PW1/PW2 at logic level 1 corresponds to power supply / “normal power mode” of the Claim: “[0018] … In the data scanning period SP, as illustrated in FIG. 2, the drive controller 11 generates power switch signals PW1 and PW2 having, e.g., a logic level of 1 to assert continued power supply…. As illustrated in FIG. 2, when the period switches from the data scanning period SP to the blanking period BP, the drive controller 11 supplies to the data driver 13 a power switch signal PW1 of logic level 0 that is, for example, to stop power supply for a predetermined power stop period T1 starting at the moment of switchover. The drive controller 11 then returns the power switch signal PW1 to the state of the logic level 1.…”).
As to claim 6, Nakayama discloses wherein the data driving device controls a driving power of a clock recovery circuit in the low power mode (Figures 2 and 5: after PW1=0 the TLD signal which is for clock synchronization is generated and applied. “[0018] …As illustrated in FIG. 2, when the power stop period T1 has elapsed from the start time of the blanking period BP, the drive controller 11 starts generating the pixel data sequence signal VPD including a data sequence TLD for clock synchronization training which includes a dummy pixel data sequence and the above-described reference timing signal superimposed thereon….” Figure 4: Clock Data Recovery (CRD 130): “[0022] The CDR circuit 130 extracts the reference timing signal from the pixel data sequence signal VPD supplied from the drive controller 11. The CDR circuit 130 then generates a clock signal CLK synchronized in phase with the reference timing signal, and supplies it to the shift register 133 and the data latch 134.”).
As to claim 7, Nakayama discloses wherein the data driving device trains a signal using the training signal (Figure 4, “CRD circuit 130” which is part of the “Data Driver Circuit 13” / “First Integrated Circuit” of the Claim).
As to claim 10, Nakayama discloses wherein the data driving device converts from the normal mode to the low power mode, in response to receiving a signal corresponding to a conversion of a mode, through the differential communication line, from the data processing device (Nakayama, see the mapping for Claim 1, the transmission of power switch signal PW1 from the Driver Controller 11 to the Data Driver 13 stops and starts the supply of power. When PW1 is back to 1, power supply is back again. “[0031] The drive controller 11 supplies the power switch signals (PW1, PW2) to the data driver 13 so that the power supply to the data driver 13 is selectively stopped for a power stop period (T1, T2) within the data blanking period BP in each frame display period as illustrated in FIG. 2. That is, the drive controller 11 stops the supply of the source voltage VL to the CDR circuit 130, the shift register 133, and the data latch 134 by the power switch signal PW1 of logic level 0 illustrated in FIG. 2. Supply of the source voltage VH to the gradation voltage converter 135 and the output buffer 136 is stopped by the power switch signal PW2 of logic level 0.” “[0032] …That is, the power supply to the data driver is stopped for the power stop period within the blanking period. The data driver applies the pixel drive voltages respectively corresponding to the luminance levels of each pixel based on the video data signal to the data lines (D.sub.1 to D.sub.n) in each horizontal scanning cycle (Hs) within the data scanning period.” “[0033] Thus, power supply to the data driver is stopped for the power stop period within the blanking period of each frame display period, and hence during this time, electric power consumption in the data driver including static power consumption is zero.” “[0034] Thus, power consumption can be greatly reduced with this driving device as compared with conventional driving devices in which static power consumption occurs even if operation is stopped due to the supply of the control signals being stopped.”).
As to claim 11, Nakayama discloses wherein the data driving device corresponds to a source driver (See Fig. 1, 13), and the data processing device corresponds to a timing control circuit (See Fig. 1, 11).
As to claim 12, Nakayama discloses a data processing device for transmitting at least one signal, the data processing device comprising:
a control circuit (See Fig. 1, 11); and
a transmitting circuit configured to
transmit a logic level signal at a first transmission rate, to a data driving device (Figure 1, the “Drive Controller 11” / “data processing device” of the Claim provides signals to the “Data Driver 13” / “data driving device” of the Claim. Figure 2 shows the “logic levels.” The “plurality of communication lines” are shown in Figure 4 as the various signal lines coming from the “Data Driver 11” to the “Data Driver 13” whose structure is shown in Figure 4: PW1, VPD, STB, PW2, POL. The “Logic Level” is taught by PW1: “[0018] … As illustrated in FIG. 2, when the period switches from the data scanning period SP to the blanking period BP, the drive controller 11 supplies to the data driver 13 a power switch signal PW1 of logic level 0 that is, for example, to stop power supply for a predetermined power stop period T1 starting at the moment of switchover….”] [The first and second transmission rates indicate low and normal power modes and during the PW1=0 the power supply is stopped and the device enters the low power mode.] [Additionally, the “logic levels” of ON and OFF in Figure 2 are a much longer period (lower frequency) and thus lower transmission rate than the STB and VPD signals.),
transmit a training signal, to the data driving device (the “training signal” is taught by TLD of Figure 2 which occurs during the Blanking Period (BP): “[0018] … As illustrated in FIG. 2, when the period switches from the data scanning period SP to the blanking period BP, the drive controller 11 supplies to the data driver 13 a power switch signal PW1 of logic level 0 that is, for example, to stop power supply for a predetermined power stop period T1 starting at the moment of switchover…. As illustrated in FIG. 2, when the power stop period T1 has elapsed from the start time of the blanking period BP, the drive controller 11 starts generating the pixel data sequence signal VPD including a data sequence TLD for clock synchronization training which includes a dummy pixel data sequence and the above-described reference timing signal superimposed thereon. The generated pixel data sequence signals VPD are supplied to the data driver 13.”), and
transmit an image signal at a second transmission rate, to the data driving device (Figure 2, the PW1 logic level 0 at some point and PW1 returns to logic level 1 which teaches the “completion of training” of the Claim. TP1= Training Period and once TP1 ends TP2 which is the training period for the “source voltage stabilizing” begins but TP1 and TP2 can overlap, as shown in Figure 5, and end together. After TP1 (and TP2) end, the application Hs (Horizontal Scanning Pulses) begins which has a different frequency from the “logic level signal.” The “second transmission rate” pertains to the STB or VPD both of which come at a much faster rate than the Logic Level signals of PW1 and PW2. Additionally, the period (inverse of transmission rate) of the Hs is shortened after the training periods (TP1 and TP2) (meaning that transmission rate is increased): “[0018] …The cycle of strobe pulses SB in the strobe signal STB is equal to the horizontal scanning cycle Hs of horizontal scanning pulses (described later), which are applied to drive the display unit 20…. As illustrated in FIG. 2, when the period switches from the data scanning period SP to the blanking period BP, the drive controller 11 supplies to the data driver 13 a power switch signal PW1 of logic level 0 that is, for example, to stop power supply for a predetermined power stop period T1 starting at the moment of switchover. The drive controller 11 then returns the power switch signal PW1 to the state of the logic level 1. …” “[0038] Accordingly, as illustrated in FIG. 2, a training period TP1 including a clock stabilizing period is placed immediately before the transition to the next frame display period in each frame display period, and the drive controller 11 controls the CDR circuit 130 to restart operation in this training period TP1….” “[0035] Further, the horizontal scanning cycle Hs for scanning the horizontal scan lines S.sub.1 to S.sub.m of the display unit 20 is shortened in order to secure the power stop period (T1, T2) within the blanking period BP as illustrated in FIG. 2. This makes it possible to secure the power stop period (T1, T2) within the blanking period BP without extending the frame display period. If, for example, the frame display period is set at 1/30 sec and the horizontal scanning cycle Hs is shortened and the data scanning period SP is set at 1/60 sec, the remaining 1/60 sec can be used as the blanking period BP, and hence the power stop period can be set within this 1/60 sec.”] [The first and second transmission rates indicate low and normal power modes and during the PW1=1 the power supply is reconnected and image data start being transmitted and received.),
wherein the first transmission rate for the logic level signal is lower than the second transmission rate for the image signal (the period of the Horizontal Scanning Pulses (Hs) is shortened (the pulses are made faster) in order to open room for the blanking (training) periods: “[0035] Further, the horizontal scanning cycle Hs for scanning the horizontal scan lines S.sub.1 to S.sub.m of the display unit 20 is shortened in order to secure the power stop period (T1, T2) within the blanking period BP as illustrated in FIG. 2. This makes it possible to secure the power stop period (T1, T2) within the blanking period BP without extending the frame display period. If, for example, the frame display period is set at 1/30 sec and the horizontal scanning cycle Hs is shortened and the data scanning period SP is set at 1/60 sec, the remaining 1/60 sec can be used as the blanking period BP, and hence the power stop period can be set within this 1/60 sec.”).
As to claim 13, the same rejection or discussion is used as in the rejection of claim 2.
As to claim 14, Nakayama discloses wherein a clock for reading data is configured to be transmitted by being embedded in the image signal (“[0018] …As illustrated in FIG. 2, when the power stop period T1 has elapsed from the start time of the blanking period BP, the drive controller 11 starts generating the pixel data sequence signal VPD including a data sequence TLD for clock synchronization training which includes a dummy pixel data sequence and the above-described reference timing signal superimposed thereon….” Figure 4: Clock Data Recovery (CRD 130): “[0022] The CDR circuit 130 extracts the reference timing signal from the pixel data sequence signal VPD supplied from the drive controller 11. The CDR circuit 130 then generates a clock signal CLK synchronized in phase with the reference timing signal, and supplies it to the shift register 133 and the data latch 134.”).
As to claim 16, Nakayama discloses a data driving device configured to receive at least one signal, the data driving device comprising:
a control circuit configured to control conversion from a low power mode to a normal mode, based on a logic level signal at a first transmission rate received from a data processing device (Figure 1, the “Drive Controller 11” / “Second Integrated Circuit” of the Claim provides signals to the “Data Driver 13” / “First Integrated Circuit” of the Claim. Figure 2 shows the “logic levels.” The “plurality of communication lines” are shown in Figure 4 as the various signal lines coming from the “Data Driver 11” to the “Data Driver 13” whose structure is shown in Figure 4: PW1, VPD, STB, PW2, POL. The “Logic Level” is taught by PW1: “[0018] … As illustrated in FIG. 2, when the period switches from the data scanning period SP to the blanking period BP, the drive controller 11 supplies to the data driver 13 a power switch signal PW1 of logic level 0 that is, for example, to stop power supply for a predetermined power stop period T1 starting at the moment of switchover….”] [The first and second transmission rates indicate low and normal power modes and during the PW1=0 the power supply is stopped and the device enters the low power mode.] [Additionally, the “logic levels” of ON and OFF in Figure 2 are a much longer period (lower frequency) and thus lower transmission rate than the STB and VPD signals.);
a training circuit configured to train a signal based on a training signal received from the data processing device, in the normal mode (the “training signal” is taught by TLD of Figure 2 which occurs during the Blanking Period (BP): “[0018] … As illustrated in FIG. 2, when the period switches from the data scanning period SP to the blanking period BP, the drive controller 11 supplies to the data driver 13 a power switch signal PW1 of logic level 0 that is, for example, to stop power supply for a predetermined power stop period T1 starting at the moment of switchover…. As illustrated in FIG. 2, when the power stop period T1 has elapsed from the start time of the blanking period BP, the drive controller 11 starts generating the pixel data sequence signal VPD including a data sequence TLD for clock synchronization training which includes a dummy pixel data sequence and the above-described reference timing signal superimposed thereon. The generated pixel data sequence signals VPD are supplied to the data driver 13.”); and
a receiving circuit configured to receive an image signal at a second transmission rate, from the data processing device (Figure 2, the PW1 logic level 0 at some point and PW1 returns to logic level 1 which teaches the “completion of training” of the Claim. TP1= Training Period and once TP1 ends TP2 which is the training period for the “source voltage stabilizing” begins but TP1 and TP2 can overlap, as shown in Figure 5, and end together. After TP1 (and TP2) end, the application Hs (Horizontal Scanning Pulses) begins which has a different frequency from the “logic level signal.” The “second transmission rate” pertains to the STB or VPD both of which come at a much faster rate than the Logic Level signals of PW1 and PW2. Additionally, the period (inverse of transmission rate) of the Hs is shortened after the training periods (TP1 and TP2) (meaning that transmission rate is increased): “[0018] …The cycle of strobe pulses SB in the strobe signal STB is equal to the horizontal scanning cycle Hs of horizontal scanning pulses (described later), which are applied to drive the display unit 20…. As illustrated in FIG. 2, when the period switches from the data scanning period SP to the blanking period BP, the drive controller 11 supplies to the data driver 13 a power switch signal PW1 of logic level 0 that is, for example, to stop power supply for a predetermined power stop period T1 starting at the moment of switchover. The drive controller 11 then returns the power switch signal PW1 to the state of the logic level 1. …” “[0038] Accordingly, as illustrated in FIG. 2, a training period TP1 including a clock stabilizing period is placed immediately before the transition to the next frame display period in each frame display period, and the drive controller 11 controls the CDR circuit 130 to restart operation in this training period TP1….” “[0035] Further, the horizontal scanning cycle Hs for scanning the horizontal scan lines S.sub.1 to S.sub.m of the display unit 20 is shortened in order to secure the power stop period (T1, T2) within the blanking period BP as illustrated in FIG. 2. This makes it possible to secure the power stop period (T1, T2) within the blanking period BP without extending the frame display period. If, for example, the frame display period is set at 1/30 sec and the horizontal scanning cycle Hs is shortened and the data scanning period SP is set at 1/60 sec, the remaining 1/60 sec can be used as the blanking period BP, and hence the power stop period can be set within this 1/60 sec.”] [The first and second transmission rates indicate low and normal power modes and during the PW1=1 the power supply is reconnected and image data start being transmitted and received.),
wherein the first transmission rate for the logic level signal is lower than the second transmission rate for the image signal (the period of the Horizontal Scanning Pulses (Hs) is shortened (the pulses are made faster) in order to open room for the blanking (training) periods: “[0035] Further, the horizontal scanning cycle Hs for scanning the horizontal scan lines S.sub.1 to S.sub.m of the display unit 20 is shortened in order to secure the power stop period (T1, T2) within the blanking period BP as illustrated in FIG. 2. This makes it possible to secure the power stop period (T1, T2) within the blanking period BP without extending the frame display period. If, for example, the frame display period is set at 1/30 sec and the horizontal scanning cycle Hs is shortened and the data scanning period SP is set at 1/60 sec, the remaining 1/60 sec can be used as the blanking period BP, and hence the power stop period can be set within this 1/60 sec.”).
As to claim 17, the same rejection or discussion is used as in the rejection of claim 2.
As to claim 19, the same rejection or discussion is used as in the rejection of claim 6.
As to claim 20, Nakayama discloses wherein a driving power of the clock recovery circuit is blocked in the low power mode (Nakayama, see the mapping for Claim 1, the transmission of power switch signal PW1 from the Driver Controller 11 to the Data Driver 13 stops and starts the supply of power. When PW1 is back to 1, power supply is back again. “[0031] The drive controller 11 supplies the power switch signals (PW1, PW2) to the data driver 13 so that the power supply to the data driver 13 is selectively stopped for a power stop period (T1, T2) within the data blanking period BP in each frame display period as illustrated in FIG. 2. That is, the drive controller 11 stops the supply of the source voltage VL to the CDR circuit 130, the shift register 133, and the data latch 134 by the power switch signal PW1 of logic level 0 illustrated in FIG. 2..
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3, 15 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over US Patent Pub. 2015/0138254 A1 to Nakayama in view of US Patent Pub. 2010/0231787 A1 to Kim et al (“Kim”).
As to claim 3, Nakayama fails to disclose wherein the logic level signal corresponds to a transistor- transistor logic (TTL) signal or a complementary metal oxide semiconductor (CMOS) signal.
Kim discloses wherein the logic level signal corresponds to a transistor- transistor logic (TTL) signal or a complementary metal oxide semiconductor (CMOS) signal ([0034], “The receiver 11 receives externally input signals, for example, including video signals LVDS and control signals, and converts them into digital signals, e.g., a TTL or CMOS level signals, suitable to an internal circuit. The input signal may conform to low voltage differential signaling or a digital visual interface (DVI) signal. …”).
Before the effective filing date, it would have been obvious to one of ordinary skill in the art to have modified Nakayama with the teachings of Kim wherein the logic level signal corresponds to a transistor- transistor logic (TTL) signal or a complementary metal oxide semiconductor (CMOS) signal, as suggested by Kim thereby similarly using known configurations for transistors in the device of Nakayama.
As to claim 15, the same rejection or discussion is used as in the rejection of claim 3.
As to claim 18, the same rejection or discussion is used as in the rejection of claim 3.
Claim(s) 8-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over US Patent Pub. 2015/0138254 A1 to Nakayama in view of US Patent Pub. 2020/0042264 A1 to Zheng et al (“Zheng”).
As to claim 8, Nakayama fails to disclose wherein the data driving device converts from the normal mode to the low power mode, in response to the completion of receiving the image signal.
Zheng discloses wherein the data driving device converts from the normal mode to the low power mode, in response to the completion of receiving the image signal (Zheng teaches the existence of “[0084] … frame start/end indication (see, e.g., Frame Start and Frame End) …” and also teaches power saving at the end of transmission: “[0042] The example of FIG. 3 shows a one port PDI 250 between host circuitry 300 and signal lines 252 to CDIC(s) 202. In the example of FIG. 3, PDI 250 consists of a two-lane high speed link 258 for data in two lanes labeled lane0 and lane1, a power down (PWDN) control pin 303 and a multi-purpose backchannel (MBC) pin 305. Host 300 uses high-speed link 258 to transmit CDIC configuration information together with pixel data. PWDN pin 303 is used to receive a powerdown signal from host 300 to put CDIC(s) 202 into a deep power saving mode when there is no data transmission.).
Before the effective filing date, it would have been obvious to one of ordinary skill in the art to have modified Nakayama with the teachings of Zheng wherein the data driving device converts from the normal mode to the low power mode, in response to the completion of receiving the image signal, as suggested by Zheng thereby similarly using known configurations for operating mode switching in the device of Nakayama.
As to claim 9, Zheng discloses wherein, when data corresponding to an end of frame is received, the first integrated circuit determines that data reception is completed (Zheng teaches the existence of “[0084] … frame start/end indication (see, e.g., Frame Start and Frame End) …”).
Conclusion
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/NICHOLAS J LEE/Primary Examiner, Art Unit 2624
