DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1,3,14-15 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Yamamoto et al. (US 2026/0065860).
As to Claim 1, Yamamoto et al. A display panel, comprising a plurality of pixel circuits and a plurality of light- emitting devices, wherein the pixel circuits are electrically connected to the light-emitting devices (fig.1,22,27; pixels 18 connected to respective organic EL element OL),
each pixel circuit comprises a driving transistor (fig.27, drive transistor T4; para.0195,0197, ) and a data writing transistor (fig.27, write control transistor T3; para.0195,0197)
the driving transistor is configured to generate a driving current (fig.27, organic EL element emits light based current I1 from driving transistor T4; para.0207) and
the data writing transistor is electrically connected to a first electrode of the driving transistor (fig.27, write control transistor T3 connected to first electrode (source) of drive transistor T4);
wherein an operation of the pixel circuit comprises a data writing stage (fig.27-29; data write period Twr; para.0199-0204), and a bias stage (fig.27-29; para.0199-0204, on-bias period Tobs); and
wherein the display panel further comprises a writing frame (fig.28-29), and in the writing frame: the data writing transistor is turned on in the data writing stage to write a data voltage to the driving transistor (para.0199- During this data write period Twr, the write control transistor T3, the threshold compensation transistor T2, and the second initialization transistor T7 are in ON state…in the data write period Twr, the data signal D(j) is applied from the data-side drive circuit 30 to the corresponding data signal line Dj via the first selection transistor Ta, the voltage of the data signal D(j), which is the voltage of the corresponding data signal line Dj, is written as the data voltage Vdata to the holding capacitor Cst via the driving transistor T4); and
the data writing transistor is turned on in the bias stage to write a first bias voltage to the first electrode of the driving transistor (para.0199- During the on-bias period Tobs, the write control transistor T3 and the second initialization transistor T7 are in ON state… in the multiplexer MXj connected to the corresponding data signal line Dj, the first selection transistor Ta is in OFF state and the second selection transistor Tb is in ON state. Therefore, in the on-bias period Tobs, the on-bias voltage Vobs applied to the corresponding data signal line Dj via the second selection transistor Tb is applied to the source terminal of the driving transistor T4 via the write control transistor T3).
As to Claim 3, Yamamoto et al. disclsoes wherein the operation of the pixel circuit further comprises a light-emitting stage, in which the driving transistor generates the driving current (fig.29, light emission period Tem, para.0207); and in the writing frame: the bias stage is between the data writing stage and the light- emitting stage (fig.29, on-bias period Tobs is between data write period Twr and light emitting period Tem).
As to Claim 14, Yamamoto et al. discloses wherein the pixel circuit comprises a gate reset transistor (fig.27, initialization transistor T1; para.0196) and a threshold compensation transistor (fig.27, threshold compensation transistor T2; para.0196), the gate reset transistor is connected to a control terminal of the driving transistor (fig.27, initialization transistor T1 connected to gate of drive transistor T4), and the threshold compensation transistor is connected between the control terminal of the driving transistor and a second electrode of the driving transistor (fig.27, threshold compensation transistor T2, connected between gate and second electrode (drain) of drive transistor T4; para.0179); and an active layer of the gate reset transistor and an active layer of the threshold compensation transistor comprise metal oxide (para.0196).
As to Claim 15 has limitations similar to those of Claim 1 and are met by the reference as set forth above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 4-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto et al. (US 2026/0065860) in view of Kim et al. (US 2022/0173189).
As to Claim 4, Yamamoto et al. discloses wherein the pixel circuit further comprises a first light-emitting control transistor (fig.27, transistor T6) and a second light-emitting control transistor (fig.27, transistor T5), and the driving transistor is connected between the first light- emitting control transistor and the second light-emitting control transistor (fig.29, drive transistor T4); the display panel further comprises a first scan line (fig.27, scan line PS(i)) and a light-emitting control line (fig.27, emission control line EM(i)), a control terminal of the data writing transistor is connected to the first scan line (fig.27, gate of write transistor T3 connected to PS(i)), and a control terminal of the first light-emitting control transistor and a control terminal of the second light-emitting control transistor are connected to the light-emitting control line (fig.27, gate of transistors T6 and T5 connected to emission signal EM(i)); and in the writing frame: the first scan line controls the data writing transistor to be turned on in the data writing stage and controls the data writing transistor to be turned on in the bias stage (para.0199);
the light-emitting control line controls the first light-emitting control transistor and the second light-emitting control transistor to be turned on in the light-emitting stage (para.0207); and
a time interval t1 exists between an end moment when the first scan line provides an effective level in the bias stage and a start moment when the light-emitting control line provides an effective level in the light-emitting stage, t1> H, and H is a row scanning time (fig.29, time from when Psi changes from low to high (end of bias Tobs) to when Emi changes from high to low (start period Tem).
Yamamoto et a. does not expressly disclose where t1>H, H is a row scanning time.
Kim et al. discloses where a time interval t1 exists between an end moment when a first scan line provides an effective level in the bias stage (fig.3c- scan signal SC2, from high to low, period Tp; fig.6a- scan signal SC4, end of bias period Tobs1) and a start moment when the light-emitting control line provides an effective level in the light-emitting stage (fig.3c-d, emission signal EM1, EM2 from high to low, period Te; fig.6e- low level period Te), t1> H, and H is a row scanning time (fig.3c-d, para.0076,0090; period Tp is one horizontal scanning time 1H, and the time from end of period Tp to the fall of Em1/EM2 is greater than 1H; figs.6-period Tp is 1H, and the time from end of Tobs1 to start of Te is greater than 1H).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Yamamoto et al. with the teachings of Kim et al., the motivation being to ensure sufficient compensation time for compensating threshold voltage of driving transistor to improve image quality.
As to Claim 5, Yamamoto et al. discloses wherein the pixel circuit further comprises a threshold compensation transistor connected between a second electrode of the driving transistor and a control terminal of the driving transistor (Yamamoto-fig.27, threshold compensation transistor T2; para.0196);
the display panel further comprises a first scan line (fig.27, scan signal PS(i)) and a second scan line (fig.27, scan signal NS(i)), a control terminal of the data writing transistor is connected to the first scan line (fig.27, gate of write transistor T3 connected to scan signal PS(i)), and a control terminal of the threshold compensation transistor is connected to the second scan line (fig.27, gate of threshold compensation transistor T2 connected to scan signal NS(i)); and in the writing frame: the first scan line controls the data writing transistor to be turned on in the data writing stage and controls the data writing transistor to be turned on in the bias stage (para.0199); the second scan line controls the threshold compensation transistor to be turned on in the data writing stage (para.0199); and a time interval t2 exists between an end moment when the second scan line provides an effective level and a start moment when the first scan line provides an effective level in the bias stage (fig.29, pulse of scan line NS(i) changes from high to low and end of period Tobs).
Yamamoto et al. does not expressly disclose, t2 > H, and H is a row scanning time.
Kim et al. discloses a time interval t2 exists between an end moment when the second scan line provides an effective level and a start moment when the first scan line provides an effective level in the bias stage (fig.6a, c, time between end of period Ts, scan line SC3 and end of bias period Tobs2, SC4), t2 > H, and H is a row scanning time (fig.6a,c; para.0076,0090; period Tp (sc2) is one horizontal scanning time 1H, and a time from end of period Ts (SC3) to end of period Tobs (SC4) is greater than 1H).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Yamamoto et al. with the teachings of Kim et al., the motivation being to ensure sufficient compensation time for compensating threshold voltage of driving transistor to improve image quality.
Claim(s) 6-7, 10-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto et al. (US 2026/0065860) in view of Li et al. (US 2022/0122522).
As to Claim 6, Yamamoto et al. discloses wherein the pixel circuit further comprises a gate reset transistor connected to a control terminal of the driving transistor (fig.27, initialization transistor T1 connected to gate of drive transistor T4; para.0199); the operation of the pixel circuit further comprises a gate reset stage (fig.29, initialization period Tini), and the gate reset transistor is turned on in the gate reset stage to reset the control terminal of the driving transistor (fig.29, during initialization period Tini, initialization transistor T1 is turned on; para.0181).
Yamamoto et al. does not expressly disclose, but Li et al. discloses: in the writing frame: the bias stage and the gate reset stage at least partially overlap with each other in time (fig.22, para.0130, the reset stage and the bias stage may partially overlap).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Yamamoto et al. with the teachings of Li et al., the motivation being to improve an effect of bias adjustment of the bias stage.
As to Claim 7, Yamamoto et al. in view of Li et al. disclose wherein in the writing frame: a start moment of the bias stage is not earlier than a start moment of the gate reset stage, and an end moment of the bias stage is not earlier than an end moment of the gate reset stage (Li-fig.22, bias stage starts when s2-p2 changes from high to low, and ends after an end of the gate reset stage, when s1-p2 changes from low to high).
As to Claim 10, Yamamoto et al. does not expressly disclose, but Li et al. discloses: wherein the display panel further comprises a holding frame, and at least one holding frame is provided between two adjacent writing frames; and in the holding frame: the data writing transistor is turned on in the bias stage and writes a second bias voltage to the first electrode of the driving transistor (fig.8-9; a refresh frame may include a data writing frame and plurality of holding frames; para.0084, 0093-0099, holding frame may include a bias stage).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Yamamoto et al. with the teachings of Li et al., the motivation being to so that bias adjustment of the driving transistor may be improved.
As to Claim 11, Yamamoto et al. in view of Li et al. disclose, wherein in the holding frame, the operation of the pixel circuit comprises two bias stages (fig.8-9; para.0093, 0098).
As to Claim 12, Yamamoto et al. in view of Li et al. disclose wherein the display panel comprises a first scan line, and a control terminal of the data writing transistor is connected to the first scan line (Yamamoto-fig.27, data transistor T3, scan signal PS(i); Li-fig.5, data transistor T1, scan signal s1-p1 ); and a pulse signal provided by the first scan line in the writing frame is the same as a pulse signal provided by the first scan line in the holding frame (fig.7-8, scan signal s1-p1 is the same in writing frame (fig.7) and holding frame (fig.8))
Claim(s) 8-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto et al. (US 2026/0065860) in view of Sano (US 2024/0304144).
As to Claim 8, Yamamoto et al. discloses wherein in the writing frame: a duration of the data writing stage is t3, a duration of the bias stage is t4 (fig.29, duration of data write period Twr and duration of on-bias period Tobs).
Yamamoto et al. does not expressly where t3> t4.
Sano discloses where a duration of an on-bias period (fig.16,period t12-t14) may be set equal or shorter than a duration of data write period (fig.16, period t6-t7).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Yamamoto et al. with the teachings of Sano, the motivation being to achieve desired duration for the biasing period and data write period to make it possible to display satisfactory image perceivable from flickering across all areas of the image.
As to Claim 9, Yamamoto et al. in view of Sano disclose wherein the display panel further comprises a first scan line, and a control terminal of the data writing transistor is connected to the first scan line (fig.27, data transistor T3 connected to scan line PS(i)); and in the writing frame: a duration for which the first scan line provides an effective level in the data writing stage is t3 (fig.29, scan line PS(i) duration of data writing period Twr), and a duration for which the first scan line provides the effective level in the bias stage is t4 (fig.29,scan line PS(i) duration of on-bias period Tobs).
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto et al. (US 2026/0065860) in view of Lai et al. (US 2021/0407383).
As to Claim 13, Yamamoto et al. disclosed wherein the pixel circuit further comprises an electrode reset transistor connected to one electrode of one of the light-emitting devices (fig.27, initialization transistor T1 is turned on; para.0181); the display panel further comprises a first scan line (Yamamoto-fig.27, scan line PS(i)); and a control terminal of the electrode reset transistor and a control terminal of the data writing transistor are connected to the first scan line (Yamamoto-fig.27, gate of data transistor T3 connected to PS(i)).
Yamamoto et al. does not expressly disclose where a control terminal of the electrode reset transistor is connected to the first scan line.
Lai et al. discloses a pixel circuit including a reset transistor T7 connected to scan signal S1, and data transistor T5 connected to scan signal S4, where at least two scan signals out of the plurality of scan signals, may be the same signal (para.0069; fig.6).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Yamamoto et al. with the teachings of Lai et al., since doing so would not have modified the operation of the device, yielding predictable results, in particular turning off reset transistor during data write period Twr and turned on during initialization period.
Allowable Subject Matter
Claim 2 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 2 is allowable over the prior of art of record since the cited references alone one or in combination do not teach or suggest “the bias stage of the pixel circuit in the n-th pixel circuit row and the data writing stage of the pixel circuit in an m-th pixel circuit row at least partially overlap with each other in time, and an overlapping period is a first period; and n and m are both positive integers, and |n-m|> 1; and in the first period, the data writing transistor in the m-th pixel circuit row is turned on, the data line writes the data voltage to the driving transistor, the data writing transistor in the n-th pixel circuit row is turned on, the data line writes the first bias voltage to the driving transistor, and the data voltage provided by the data line is reused as the first bias voltage” in combination with the other limitations in the claim.
Conclusion
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/DISMERY MERCEDES/Primary Examiner, Art Unit 2627
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