DETAILED ACTION
The Action is responsive to Applicant’s Application filed September 12, 2025.
Please note claims 1-20 are pending.
Priority
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, or 365(c) is acknowledged.
Drawings
The drawings, filed September 12, 2025 are considered in compliance with 37 CFR 1.81 and accepted.
Information Disclosure Statement
The information disclosure statements filed December 12, 2025 are in compliance with 37 CFR 1.97(c) and therein have been considered. Its corresponding PTO-1449 has been electronically signed as attached.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 6-8, 13-15 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-3, 6, 8-9, 14, 16 of U.S. Patent No. 12,488,051. Although the claims at issue are not identical, they are not patentably distinct from each other because:
Instant Application 19/327757
US Patent. No. 12,488,051
1. A method, comprising:
ordering and reordering execution of operators of a hypergraph comprising a first query graph representative of a first user query and a second query graph representative of a second user query, the first query graph comprising a first operator of the operators and the second query graph comprising a second operator of the operators; determining a plurality of execution sequences based on said ordering and
reordering;
selecting a first execution sequence of the plurality of execution sequences; and
scheduling execution of the first execution sequence.
9. A method, comprising:
receiving a first user query; generating an independent first query graph representative of the first user query, the first query graph comprising at least one operator; enlisting the first query graph into a hypergraph containing query graphs that are representative of user queries including the enlisted first query graph; analyzing the hypergraph at least by ordering and reordering execution of operators of the hypergraph, the analysis resulting in a plurality of execution sequences;
selecting, based at least on the analysis, a first execution sequence of the plurality of execution sequences; and scheduling execution of the first execution sequence.
6. The method of claim 5, further comprising: determining a failure in execution of the first execution sequence by the first query processing device; and
causing a second query processing device to replay at least a portion of the first execution sequence.
14. The method of claim 12, further comprising: determining a failed execution of a first operator of the hypergraph; determining a scope of failure in the hypergraph related to the failed execution of the first operator, the scope of failure including operators scheduled for execution after the scheduled execution of the first operator in the selected execution sequence; generating a composite set of states for the operators included in the determined scope of failure; and rescheduling execution of the operators in the generated composite set of states.
7. The method of claim 6, further comprising: dynamically redetermining, during execution of the first execution sequence, a set of states corresponding to operators executed during the execution of the first execution sequence, resulting in a redetermined set of states; and storing the redetermined set of states, wherein said causing the second query processing device to replay at least the portion of the first execution sequence comprises: causing the second query processing device to replay at least a portion of the redetermined set of states.
16. The method of claim 15, further comprising: dynamically redetermining the set of states of the hierarchical state machine during the scheduled execution; storing the redetermined set of states; and replaying at least a portion of the redetermined set of states.
8. A system, comprising:
a processor; and
a memory device storing program code structured to cause the processor to:
order and reorder execution of operators of a graph comprising a first
operator corresponding to a first query and a second operator corresponding to a
second query; determine a plurality of execution sequences based on said ordering and reordering;
select a first execution sequence of the plurality of execution sequences; and
schedule execution of the first execution sequence.
1. A system, comprising:
a processor; and
a memory device that stores program code structured to cause the processor to:
receive a first user query, generate an independent first query graph representative of the first user query, the first query graph comprising at least one operator, enlist the first query graph into a hypergraph containing query graphs that are representative of user queries including the enlisted first query graph, analyze the hypergraph at least by ordering and reordering execution of operators of the hypergraph, the analysis resulting in a plurality of execution sequences,
select, based at least on the analysis, a first execution sequence of the plurality of execution sequences, and schedule execution of the first execution sequence.
13. The system of claim 12, wherein the program code is further structured to cause the processor to:
determine a failure in execution of the first execution sequence by the first query
processing device; and
cause a second query processing device to replay at least a portion of the first
execution sequence.
6. The system of claim 4, the program code is structured to further cause the processor to:
determine a failed execution of a first operator of the hypergraph, and determine a scope of failure in the hypergraph related to the failed execution of the first operator, the scope of failure including operators scheduled for execution after the scheduled execution of the first operator in the selected execution sequence; generate a composite set of states for the operators included in the determined scope of failure; and reschedule execution of the operators in the generated composite set of states.
14. The system of claim 13, wherein the program code is further structured to cause the processor to:
dynamically redetermine, during execution of the first execution sequence, a set of states corresponding to operators executed during the execution of the first execution sequence, resulting in a redetermined set of states; and
store the redetermined set of states, wherein to cause the second query processing device to replay at least the portion of the first execution sequence, the program code is further structured to cause the processor to:
cause the second query processing device to replay at least a portion of the
redetermined set of states.
8. The system of claim 7, wherein the program code is further structured to cause the processor to: dynamically redetermine the set of states of the hierarchical state machine during the scheduled execution; store the redetermined set of states; and replay at least a portion of the redetermined set of states.
15. The system of claim 8, wherein the graph is a hypergraph comprising a first query graph and a second query graph, the first query graph comprising the first operator and the second query graph comprising the second operator.
2. The system of claim 1, wherein to enlist the first query graph into the hypergraph, the program code is further structured to cause the processor to: determine an instance of an operator present in both the first query graph and the hypergraph; and connect the first query graph into the hypergraph to share the operator.
3. The system of claim 1, wherein the program code is further structured to cause the processor to: receive a second user query; generate an independent second query graph representative of the second user query, the second query graph including at least one operator; and enlist the second query graph into the hypergraph.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-2, 4-5, 8-9, 11-12, 15-17, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wolf et al. (US Pub. No. 2023/0141462) further in view of Breß et al. (US Pat. No. 11,615,092)
Regarding claim 1, Wolf teaches a method, comprising:
‘ordering and reordering execution of operators comprising a first query graph representative of a first user query and a second query graph representative of a second user query, the first query graph comprising a first operator of the operators and the second query graph comprising a second operator of the operators’ as receiving query execution plan with multiple execution pipelines and determining precedence relationships to identify multiple candidate execution orders (¶0041-42)
‘determining a plurality of execution sequences based on said ordering and
reordering’ as determining a plurality of execution pipelines (¶0042)
‘selecting a first execution sequence of the plurality of execution sequences’ as selecting a pipeline execution order from several pipeline execution orders (¶0020)
‘scheduling execution of the first execution sequence’ as providing the selection execution order to the execution engine for execution (¶0029)
Wolf fails to explicitly teach:
‘of a hypergraph’
Breß teaches:
‘of a hypergraph’ as fragments into a directed acyclic graph that models relationships of RSOs that are implemented to process query fragments (Col. 9, Lines 52- Col.10, Line 17; Fig. 4)
It would have been obvious to one of ordinary skill in the art at the time that the present invention was effectively filed to modify the teachings of the cited references because Breß’s would have allowed Wolf’s to increase efficiency in scheduling operations for execution (Col. 1, Lines 15-20)
Regarding claim 2, Wolf teaches wherein said determining a plurality of execution sequences comprises:
‘determining a first predicted execution duration of the first execution sequence’ as estimation of execution costs associated with query execution plans (¶0032)
Regarding claim 4, Wolf teaches wherein said determining a plurality of execution sequences comprises:
‘determining a second predicted execution duration of a second execution sequence; and said selecting the first execution sequence comprises: selecting the first execution sequence based on the first predicted execution duration being shorter than the second predicted execution duration’ as estimation of execution costs associated with query execution plans (¶0032) and selecting a pipeline execution order from several pipeline execution orders (¶0020) based on lowest execution cost (¶0054)
Regarding claim 5, Wolf teaches wherein said scheduling execution of the first execution sequence comprises:
‘causing a first query processing device to execute the first execution sequence’ as providing the execution plan to the execution engine to execute the plan according to the execution order (¶0040)
Regarding claim 8, Wolf teaches system, comprising:
‘a processor’ (¶0030)
‘a memory device storing program code (¶0030) structured to cause the processor to:
order and reorder execution of operators of a graph comprising a first
operator corresponding to a first query and a second operator corresponding to a
second query’ as receiving query execution plan with multiple execution pipelines and determining precedence relationships to identify multiple candidate execution orders (¶0041-42)
‘determine a plurality of execution sequences based on said ordering and
reordering’ as determining a plurality of execution pipelines (¶0042)
‘select a first execution sequence of the plurality of execution sequences’ as selecting a pipeline execution order from several pipeline execution orders (¶0020)
‘schedule execution of the first execution sequence’ as providing the selection execution order to the execution engine for execution (¶0029)
Breß teaches:
‘a graph’ as fragments into a directed acyclic graph that models relationships of RSOs that are implemented to process query fragments (Col. 9, Lines 52- Col.10, Line 17; Fig. 4)
It would have been obvious to one of ordinary skill in the art at the time that the present invention was effectively filed to modify the teachings of the cited references because Breß’s would have allowed Wolf’s to increase efficiency in scheduling operations for execution (Col. 1, Lines 15-20)
Regarding claim 9, Wolf teaches wherein to determine the plurality of execution sequences, the program code is further structured to cause the processor to:
‘determine a first predicted execution duration of the first execution sequence’ as estimation of execution costs associated with query execution plans (¶0032)
Regarding claim 11, Wolf teaches wherein the program code is further structured to cause the processor: to determine the plurality of execution sequences by:
‘determining a second predicted execution duration of a second execution sequence; and to select the first execution sequence by: selecting the first execution sequence based on the first predicted execution duration being shorter than the second predicted execution duration’ as estimation of execution costs associated with query execution plans (¶0032) and selecting a pipeline execution order from several pipeline execution orders (¶0020) based on lowest execution cost (¶0054)
Regarding claim 12, Wolf teaches wherein to schedule execution of the first execution sequence, the program code is further structured to cause the processor to:
‘cause a first query processing device to execute the first execution sequence’ as providing the execution plan to the execution engine to execute the plan according to the execution order (¶0040)
Regarding claim 15, Breß teaches ‘wherein the graph is a hypergraph comprising a first query graph and a second query graph, the first query graph comprising the first operator and the second query graph comprising the second operator’ as fragments into a directed acyclic graph that models relationships of RSOs that are implemented to process query fragments (Col. 9, Lines 52- Col.10, Line 17; Fig. 4)
Regarding claim 16, Wolf teaches a method, comprising:
‘ordering and reordering execution of operators of a graph comprising a first operator corresponding to a first query and a second operator corresponding to a second query, resulting in a first execution sequence and a second execution sequence’ receiving query execution plan with multiple execution pipelines and determining precedence relationships to identify multiple candidate execution orders (¶0041-42)
‘determining a first expected execution duration of the first execution sequence is shorter than a second expected execution duration of the second execution sequence’ as estimation of execution costs associated with query execution plans (¶0032) and determining the pipeline execution order with the lowest memory cost (¶0054)
‘select the first execution sequence based at least on said determining the first expected execution duration is shorter than the second expected execution duration’ as selecting a pipeline execution order from several pipeline execution orders (¶0020) based on execution cost (¶0054)
‘scheduling execution of the first execution sequence’ as providing the selection execution order to the execution engine for execution (¶0029)
Breß teaches:
‘a graph’ as fragments into a directed acyclic graph that models relationships of RSOs that are implemented to process query fragments (Col. 9, Lines 52- Col.10, Line 17; Fig. 4)
It would have been obvious to one of ordinary skill in the art at the time that the present invention was effectively filed to modify the teachings of the cited references because Breß’s would have allowed Wolf’s to increase efficiency in scheduling operations for execution (Col. 1, Lines 15-20)
Regarding claim 17, Wolf teaches wherein said scheduling execution of the first execution sequence comprises:
‘causing a first query processing device to execute the first execution sequence’ as providing the execution plan to the execution engine to execute the plan according to the execution order (¶0040)
Regarding claim 20, Breß teaches ‘wherein the graph is a hypergraph comprising a first query graph and a second query graph, the first query graph comprising the first operator and the second query graph comprising the second operator’ as fragments into a directed acyclic graph that models relationships of RSOs that are implemented to process query fragments (Col. 9, Lines 52- Col.10, Line 17; Fig. 4)
Allowable Subject Matter
Claims 3, 6-7, 10, 13-14, 18-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Examiner’s Note
Examiner has cited particular columns/paragraphs and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention. This will assist in expediting compact prosecution. MPEP 714.02 recites: “Applicant should also specifically point out the support for any amendments made to the disclosure. See MPEP § 2163.06. An amendment which does not comply with the provisions of 37 CFR 1.121(b), (c), (d), and (h) may be held not fully responsive. See MPEP § 714.” Amendments not pointing to specific support in the disclosure may be deemed as not complying with provisions of 37 C.F.R. 1.131(b), (c), (d), and (h) and therefore held not fully responsive. Generic statements such as “Applicants believe no new matter has been introduced” may be deemed insufficient.
Conclusion
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/VAN H OBERLY/Primary Examiner, Art Unit 2166
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