DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is responsive to the application filed 17 September 2025.
Claims 1-20 are pending and have been presented for examination.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by SUTARDJA (U.S. Patent Application Publication #2024/0394200).
1. SUTARDJA discloses A memory device comprising: a memory die stack comprising a plurality of memory dies stacked thereon (see [0299]: HBM with up to 8 DRAM dies stacked on top); and a base die under the memory die stack (see [0300]: HBM base die), wherein the base die comprises: a via interface circuit connected to the memory die stack (see [0303]: memory interconnect); a die-to-die (D2D) interface circuit connected to a processor (see [0301]: die-to-die chiplet interface with a CPU/GPU); a memory interface circuit connected to an external memory device (see [0304]: external physical memory layer with memory controller); and a memory management circuit (see [0302]: FLC engine) configured to: control data migration between the memory die stack and the external memory device (see [0305]: when there is a miss, the FLC engine retrieves the data from external memory); based on access information related to first data stored in the memory die stack, determine whether to migrate the first data from the memory die stack to the external memory device (see [0203]: data determined to be least used is removed from the FLC by the FLC engine; [0299]-[0302]: with the FLC engine incorporated into the HBM, data would be migrated from the stacked memory of the HBM to the external memory); and based on an access request from the processor to access second data stored on the external memory device, provide the second data to the processor (see [0305]: data retrieved from the DRAM, or from external memory, is provided to the processor).
2. The memory device of claim 1, wherein the memory management circuit comprises: a first controller (see [0302]: FLC lookup engine); a second controller configured to access the memory die stack and the external memory device, under control of the first controller (see [0302], [0305]: FLC controller access the memory die stack or the external memory based on the results of the FLC lookup engine;[ 0311]: HBMx controller to access the memory dies); and an access monitor configured to store the access information related to the first data stored in the memory die stack (see [0321]-[0323]: FLC status register that stores information about access recency for lines stored in the stacked dies).
3. The memory device of claim 2, wherein the memory management circuit is further configured to: monitor an access pattern for accessing the first data stored in the memory die stack, and store a memory address of the first data and a last access time for the first data as the access information (see [0323]: FLC stats register logs when the lines where used and an address for the line).
4. The memory device of claim 1, wherein the via interface circuit is connected to the plurality of memory dies through a plurality of vias penetrating the plurality of memory dies in a vertical direction (see figure 26).
5. The memory device of claim 1, further comprising an interconnect circuit connected to the D2D interface circuit, the memory interface circuit, and the memory management circuit (see [0303]: interpose layer).
6. The memory device of claim 1, further comprising a first memory controller configured to write data to the memory die stack or read data stored in the memory die stack, based on a request from the processor, wherein the first memory controller is further configured to be connected to the via interface circuit (see [0311]: HBMx controller; [0055]: a host CPU will issue memory access requests to the memory die stack).
7. The memory device of claim 1, further comprising a second memory controller configured to write data on the external memory device or read data stored in the external memory device, based on a request from the processor, wherein the second memory controller is connected to the memory interface circuit (see [0304]: controller to access external memory; [0055]: a host CPU will issue memory access requests to the memory die stack).
8. The memory device of claim 1, wherein the D2D interface circuit is configured to communicate with the processor based on universal chip interconnect express (UCIe) standard specification (see [0310]: UCIe interface), and wherein the memory interface circuit is configured to communicate with the external memory device based on a Joint Electron Device Engineering Council (JEDEC) standard specification based on a Joint Electron Device Engineering Council (JEDEC) standard specification (see [0306]: LP DRAM is a JEDEC standard).
9. The memory device of claim 1, wherein the access information comprises an access elapse time indicating an elapse time since a last access to the first data stored in the memory die stack by the processor, and wherein the memory management circuit is further configured to, based on the access elapse time being equal to or greater than a migration reference value, migrate the first data from the memory die stack to the external memory device (see [0325]: least recently used lines are evicted from the FLC).
10. The memory device of claim 1, wherein the memory management circuit is further configured to, based on a request from the processor to access the second data stored in the external memory device, determine whether to migrate the second data from the external memory device to the memory die stack (see [0135]: prevent certain data from being loaded into the FLC; [0142]: loading data based on predicted usage; [0199]: maintain most recently used lines in the FLC).
11. SUTARDJA discloses A system comprising: a first memory device comprising a first memory die stack configured to store first data (see [0299]: DRAM stack) and a first base die (see [0303]: base die; in a cascaded FLC system there are two FLC systems, the FLC-HS would be the first memory die stack and base die); a second memory device comprising a second memory die stack configured to store second data (see [0299]: DRAM stack) and a second base die (see [0303]: base die; [0207]: the FLC-SS module would be the second die stack and base die); a third memory device configured to store third data and connected to the first base die (see [0304]: external memory pool); and a logic die comprising a host processor (see [0055]: host CPU), connected to the first base die, and configured to generate an access request related to the first data, the second data, and the third data (see [0217]: access request from the processor is sent to the FLC-HS), wherein the first base die comprises: a via interface circuit connected to the first memory die stack (see [0303]: memory interconnect); a first die-to-die (D2D) interface circuit connected to the logic die (see [0301]: die-to-die chiplet interface with a CPU/GPU); a second D2D interface circuit connected to the second base die (see [0218]: FLC-HS controller forwards the request to the FLC-SS controller); a memory interface circuit connected to the third memory device (see [0304]: external physical memory layer with memory controller; [0220]: data not found in the FLC-HS and FLC-SS is retrieved from external storage); and a memory management circuit configured to control data migration among the first memory die stack, the second memory die stack, and the third memory device (see [0203]: data determined to be least used is removed from the FLC by the FLC engine; [0299]-[0302]: with the FLC engine incorporated into the HBM, data would be migrated from the stacked memory of the HBM to the external memory).
12. The system of claim 11, wherein the first base die is configured to: based on an access request from the logic die to access the first data, access the first data via the via interface circuit (see [0217]: when the processor accessed data stored in the FLC-HS, the data is returned to the processor from the FLC-HS), based on an access request from the logic die to access the second data, access the second data via the second D2D interface circuit (see [0218]: when the processor accessed data in the FLC-SS, the data is returned to the processor from the FLC-SS), and based on an access request from the logic die to access the third data, access the third data via the memory interface circuit (see [0220]: if the processor access data not in the FLC, data is accessed from the external storage and sent to the processor).
13. The system of claim 11, wherein the memory management circuit is further configured to: based on access information related to the first data stored in the first memory die stack (see [0321]-[0323]: FLC status register to track access recency for data in the die stack), migrate the first data to the third memory device (see [0325]: least recently used lines are evicted from the FLC), and based on an access request from the logic die to access the third data, determine whether to migrate the third data to the first memory die stack (see [0135]: prevent certain data from being loaded into the FLC; [0142]: loading data based on predicted usage; [0199]: maintain most recently used lines in the FLC).
14. The system of claim 11, wherein the first D2D interface circuit and the second D2D interface circuit are configured to communicate with the logic die based on a universal chip interconnect express (UCIe) standard specification (see [0310]: UCIe interface), and wherein the memory interface circuit is configured to communicate with the third memory device based on a Joint Electron Device Engineering Council (JEDEC) standard specification ased on a Joint Electron Device Engineering Council (JEDEC) standard specification (see [0306]: LP DRAM is a JEDEC standard).
15. The system of claim 11, wherein each of the first memory die stack and the second memory die stack comprises a plurality of memory dies stacked in a vertical direction (see figure 26).
16. SUTARDJA discloses A system comprising: a logic die comprising a host processor (see [0055]: hose CPU); a first memory device comprising a memory die stack comprising a plurality of memory dies stacked thereon (see [0299]: HBM with up to 8 DRAM dies stacked on top), and a base die under the memory die stack and connected to the logic die (see [0300]: HBM base die; [0303]: interface between processor and FLC controller); and a second memory device connected to the base die (see [0304]: external memory), wherein the base die comprises: a via interface circuit connected to the memory die stack (see [0303]: memory interconnect); a die-to-die (D2D) interface circuit connected to the logic die (see [0301]: die-to-die chiplet interface with a CPU/GPU); a memory interface circuit connected to the second memory device (see [0304]: external memory physical layer with memory controller); and a memory management circuit (see [0302]: FLC engine) configured to control data migration between the memory die stack and the second memory device (see [0305]: when there is a miss, the FLC engine retrieves the data from external memory), and based on access information related to first data stored in the memory die stack, migrate the first data stored in the memory die stack to the second memory device (see [0203]: data determined to be least used is removed from the FLC by the FLC engine; [0299]-[0302]: with the FLC engine incorporated into the HBM, data would be migrated from the stacked memory of the HBM to the external memory), and based on an access request from the logic die to access second data stored in the second memory device, migrate the second data to the memory die stack (see [0305]: data retrieved from the DRAM, or from external memory, is provided to the processor).
17. The system of claim 16, wherein the system comprises: a first substrate (see [0299]: DRAM); a second substrate on the first substrate (see [0300]: base die); and an interposer on the second substrate (see [0303]: interposer is part of the base die), wherein the logic die and the base die are on the interposer (see [0302]: FLC controller is part of the base die; [0303]: interposer is part of the base die), and wherein the second memory device is on the first substrate, and apart from the second substrate in a horizontal direction (see [0304]: external memory is separate from the base die).
18. The system of claim 16, wherein the D2D interface circuit is configured to communicate with the logic die based on a universal chip interconnect express (UCIe) standard specification (see [0310]: UCIe interface), and wherein the memory interface circuit performs communication with the second memory device based on a Joint Electron Device Engineering Council (JEDEC) standard specification (see [0306]: LP DRAM is a JEDEC standard).
19. The system of claim 16, wherein the access information comprises an access elapse time indicating an elapse time since a last access to the first data stored in the memory die stack by the logic die, and wherein the memory management circuit is further configured to, based on the access elapse time being equal to or greater than a migration reference value, migrate the first data from the memory die stack to the second memory device (see [0325]: least recently used lines are evicted from the FLC).
20. The system of claim 16, wherein the memory management circuit is further configured to, based on a request from the logic die to access the second data stored in the second memory device, determine whether to migrate the second data from the second memory device to the memory die stack (see [0135]: prevent certain data from being loaded into the FLC; [0142]: loading data based on predicted usage; [0199]: maintain most recently used lines in the FLC).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
CHANG [2026/0140878] discloses a vertically stacked memory with a based die. [0006]
KUMAR [2026/0094628] discloses a vertically stacked memory system and HBM being adopted as a JEDEC standard. [0003]
KULKARNI [2026/0096475]: discloses a base die with a memory controller and memory dies stacked on the base die. [0091]-[0108]
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EDWARD J DUDEK JR whose telephone number is (571)270-1030. The examiner can normally be reached Monday - Friday, 8:00A-4:00P.
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/EDWARD J DUDEK JR/Primary Examiner, Art Unit 2132
