Prosecution Insights
Last updated: August 17, 2026
Application No. 19/331,790

Display Device

Non-Final OA §102§103
Filed
Sep 17, 2025
Priority
Nov 22, 2024 — RE 10-2024-0168967
Examiner
BOYD, JONATHAN A
Art Unit
2627
Tech Center
2600 — Communications
Assignee
LG Display Co., Ltd.
OA Round
1 (Non-Final)
69%
Grant Probability
Favorable
1-2
OA Rounds
1y 11m
Est. Remaining
76%
With Interview

Examiner Intelligence

Grants 69% — above average
69%
Career Allowance Rate
496 granted / 718 resolved
+7.1% vs TC avg
Moderate +7% lift
Without
With
+7.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
17 currently pending
Career history
736
Total Applications
across all art units

Statute-Specific Performance

§101
3.1%
-36.9% vs TC avg
§103
56.6%
+16.6% vs TC avg
§102
25.7%
-14.3% vs TC avg
§112
8.4%
-31.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 718 resolved cases

Office Action

§102 §103
DETAILED ACTIONNotice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1 and 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park et al (2021/0111240) (herein “Park”). In regards to claims 1 and 19, Park teaches a display device comprising: a substrate; a plurality of light emitting devices disposed on the substrate and positioned in a display area (See; Fig. 1 for a display substrate with a matrix of pixels PX); a plurality of column lines electrically connected to a first electrode of each of the plurality of light emitting devices; a plurality of row lines electrically connected to a second electrode of each of the plurality of light emitting devices (See; Fig. 1 for data lines 171 and gate lines 151 connected to the electrodes of the pixels) a plurality of drivers configured to drive the plurality of column lines and the plurality of row lines (See; Fig. 1 and p[0029]-p[0031] for gate and data drivers); and a plurality of row connection lines electrically connecting the plurality of row lines and the plurality of drivers (See; Figs. 1, 2, p[0035] and p[0050]-p[0053] for connection lines), wherein at least one of the plurality of row connection lines includes a multi-wiring section including two or more conductive layers vertically overlapping with each other with an insulating layer interposed therebetween (See; Figs. 2, 4 and p[0054] where the second portion 62a of the connection line 60a has a dual layer structure having a first and second layer separated from each other by an insulating layer). Claim(s) 1-4, 6, 12 and 19-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by KOZUMA et al (2024/0090284) (herein “KOZUMA”). In regards to claim 1, KOZUMA teaches a display device comprising: a substrate; a plurality of light emitting devices disposed on the substrate and positioned in a display area (See; Figs. 1 and 3A for PXAL); a plurality of column lines electrically connected to a first electrode of each of the plurality of light emitting devices; a plurality of row lines electrically connected to a second electrode of each of the plurality of light emitting devices (See; Figs. 1, 3A, 6A for wiring groups GLS SLS connected to the gate and data lines which connect to the electrodes of the pixels) a plurality of drivers configured to drive the plurality of column lines and the plurality of row lines (See; Figs. 1, 3A for gate and data drivers in the circuit layer SICL); and a plurality of row connection lines electrically connecting the plurality of row lines and the plurality of drivers (See; Figs. 1, 3A, 6A for wiring groups GLS and SLS), wherein at least one of the plurality of row connection lines includes a multi-wiring section including two or more conductive layers vertically overlapping with each other with an insulating layer interposed therebetween (See; Figs. 3A, 3B where the wiring groups having a plurality of vertically overlapping conductive layers with dispersed insulating layers). In regards to claim 2, KOZUMA teaches wherein the plurality of drivers and the plurality of row connection lines are disposed in the display area (See; Fig. 3A). In regards to claim 3, KOZUMA teaches wherein the plurality of drivers are disposed between the substrate and the plurality of light emitting devices (See; Fig. 3A). In regards to claim 4, KOZUMA teaches wherein each of the plurality of column lines is a single wiring (See; Figs. 3A,3B). In regards to claim 6, KOZUMA teaches further comprising: a side protection layer disposed on a side of the plurality of drivers; an upper protection layer disposed on the side protection layer; a plurality of insulating layers disposed on the upper protection layer; a bank disposed on the plurality of insulating layers; and an optical layer disposed on a side of the bank, wherein the plurality of light emitting devices are positioned on the bank, wherein the optical layer is disposed on a side of the plurality of light emitting devices (See; Fig. 3B for “side protection layers” in SICL and “upper protection layers” in LINL with pixels situation in banks). In regards to claim 12, KOZUMA teaches wherein the display area includes a plurality of unit driving areas respectively corresponding to the plurality of drivers, and the plurality of unit driving areas include a first unit driving area corresponding to a first driver among the plurality of drivers, wherein the first unit driving area includes two or more row lines electrically connected to the first driver among the plurality of row lines, and two or more column lines electrically connected to the first driver among the plurality of column lines, wherein each of the two or more column lines is electrically connected to a first electrode of two or more light emitting devices arranged in a same column among the plurality of light emitting devices, and wherein each of the two or more row lines is electrically connected to a second electrode of two or more light emitting devices arranged in the same row among the plurality of light emitting devices (See; Figs. 3A, 3B). In regards to claim 19, KUZUMA teaches a display device comprising: a substrate; a plurality of light emitting devices disposed on the substrate (See; Figs. 1 and 3A for PXAL); a first line overlapping with the plurality of light emitting devices (See; Figs. 6A, 7 for gate and data lines overlapping the pixels); and a first connection line electrically connected to the first line (See; Figs. 1, 3A, 6A for wiring groups GLS and SLS), and including a multi-wiring section including two or more conductive layers vertically overlapping with each other with an insulating layer interposed therebetween (See; Figs. 3A, 3B where the wiring groups having a plurality of vertically overlapping conductive layers with dispersed insulating layers). In regards to claim 20, KUZUMA teaches further comprising a driver disposed on the substrate and driving the first line (See; Figs. 1, 3A for gate and data drivers in the circuit layer SICL). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 13-17 and 21-23 is/are rejected under 35 U.S.C. 103 as being unpatentable over KOZUMA et al (2024/0090284) (herein “KOZUMA”) in view of SO et al (2018/0004329) (herein “SO”). In regards to claim 13, KOZUMA teaches wherein the plurality of row connection lines include a first row connection line that electrically connects a first row line among the two or more row lines and the first driver (See; Figs. 1, 3A, 6A for wiring groups GLS and SLS). KOZUMA fails to explicitly teach wherein, during a first period, the first row line is supplied with a first low-potential voltage from the first driver through the first row connection line, and wherein, during a second period different from the first period, the first row line is supplied with a second low-potential voltage different from the first low-potential voltage from the first driver through the first row connection line. However, SO teaches during a first period, the first row line is supplied with a first low-potential voltage from the first driver through the first row connection line, and wherein, during a second period different from the first period, the first row line is supplied with a second low-potential voltage different from the first low-potential voltage from the first driver through the first row connection line (See; Fig. 5 and p[0051]-p[0059]). Therefore it would have been obvious to one of ordinary skill in the art at the time of filing to modify KOZUMA with SO in order to enable touch functionality of the display panel using time division by using the same signal lines. In regards to claim 14, SO teaches wherein two or more light emitting devices overlapping with the first row line emit light during the first period, wherein the two or more light emitting devices overlapping with the first row line do not emit light during the second period, and wherein the second low-potential voltage is higher than the first low-potential voltage (See; Fig. 5 and p[0051]-p[0059]). In regards to claim 15, SO teaches wherein, during a third period different from the first period and the second period, the first row line is supplied with a touch driving signal having a variable voltage level from the first driver through the first row connection line (See; Fig. 5 and p[0051]-p[0059]). In regards to claim 16, SO teaches wherein a low level voltage of the touch driving signal is higher than the first low-potential voltage (See; Fig. 5 and p[0051]-p[0059]). In regards to claim 17, SO teaches wherein a frequency of the touch driving signal is variable according to time (See; Fig. 5 and p[0051]-p[0059]). In regards to claim 21, KOZUMA fails to explicitly teach wherein, during a first period, the first line is supplied with a first low-potential voltage through the first connection line, wherein, during a second period different from the first period, the first line is supplied with a second low-potential voltage different from the first low-potential voltage through the first connection line. However, SO teaches wherein, during a first period, the first line is supplied with a first low-potential voltage through the first connection line, wherein, during a second period different from the first period, the first line is supplied with a second low-potential voltage different from the first low-potential voltage through the first connection line (See; Fig. 5 and p[0051]-p[0059]). Therefore it would have been obvious to one of ordinary skill in the art at the time of filing to modify KOZUMA with SO in order to enable touch functionality of the display panel using time division by using the same signal lines. In regards to claim 22, SO teaches wherein, during a third period different from the first period and the second period, the first line is supplied with a touch driving signal having a variable voltage level through the first connection line (See; Fig. 5 and p[0051]-p[0059]). In regards to claim 23, KOZUMA teaches a display device comprising: a substrate; a driver disposed on the substrate; a plurality of light emitting devices disposed over the driver (See; Figs. 1 and 3A for PXAL layer over driver layer SICL); and a first line overlapping with the plurality of light emitting devices and electrically connected with the plurality of light emitting devices (See; Figs. 6A, 7 for gate and data lines overlapping the pixels). KOZUMA fails to explicitly teach wherein during a touch period of the display device, the first line is supplied with a touch driving signal from the driver. However, SO teaches during a touch period of the display device, the first line is supplied with a touch driving signal from the driver (See; Fig. 5 and p[0051]-p[0059]). Therefore it would have been obvious to one of ordinary skill in the art at the time of filing to modify KOZUMA with SO in order to enable touch functionality of the display panel using time division by using the same signal lines. Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over KOZUMA et al (2024/0090284) (herein “KOZUMA”) in view of SO et al (2018/0004329) (herein “SO”) and further in view of LEE (2021/0200375). In regards to claim 18, SO fails to explicitly teach a touch ground arranged below the first row line and supplied with a load-free driving signal whose signal characteristics correspond to the touch driving signal during the third period. However, LEE teaches a touch ground arranged below the first row line and supplied with a load-free driving signal whose signal characteristics correspond to the touch driving signal during the third period (See; p[0122]-p[0124]). Therefore it would have been obvious to one of ordinary skill in the art at the time of filing to modify SO with the touch electrode layout of LEE as it is a well-known means of integrating touch sensing with a display to utilize the same signal lines. Allowable Subject Matter Claims 5 and 7-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONATHAN A BOYD whose telephone number is (571)270-7503. The examiner can normally be reached Mon - Fri 8:00 - 5:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ke Xiao can be reached at (571) 272-7776. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JONATHAN A BOYD/Primary Examiner, Art Unit 2627
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Prosecution Timeline

Sep 17, 2025
Application Filed
Jul 28, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
69%
Grant Probability
76%
With Interview (+7.2%)
2y 10m (~1y 11m remaining)
Median Time to Grant
Low
PTA Risk
Based on 718 resolved cases by this examiner. Grant probability derived from career allowance rate.

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