DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on October 3, 2025 included a foreign language NPL document. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement considered by the Examiner is limited to the content of the English language portions provided in the Translation of Abstract.
However, Applicant is reminded of the procedure outlined in MPEP 609.04(a)(III) and the duty under 37 CFR 1.56 regarding the remaining content that was not provided in a concise explanation of relevance or translated, and therefore was not considered by Examiner.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: “a selection unit electrically connected with the drain electrode of the first transistor” (claim 1 – emphasis added).
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Examiner is interpreting a selection unit to include at least an inverter (see at least claim 3), or a buffer (see at least claim 4) or a plurality of second transistors having the same polarity (see at least claim 12).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-9 and 11-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Young (TW200809718A) (Machine translation used).
With respect to claim 1, Young teaches a pixel circuit (Figs. 1-9), comprising:
a first transistor comprising a gate electrode, a source electrode, and a drain electrode (Figs. 1-9. At least Fig. 5, item T7);
a scan line electrically connected with the gate electrode of the first transistor (Figs. 1-9. At least Fig. 5, item 64);
a data line electrically connected with the source electrode of the first transistor (Figs. 1-9. At least Fig. 5, item 62);
a selection unit electrically connected with the drain electrode of the first transistor (Figs. 1-9. At least Fig. 5, item 54);
a storage capacitor, wherein a first end of the storage capacitor is electrically connected with the drain electrode of the first transistor and an input node of the selection unit (Figs. 1-9. At least Fig. 5, item 50); and
a pixel electrode electrically connected with an output node of the selection unit, and wherein the selection unit provides a driving voltage to the pixel electrode (Figs. 1-9. At least Fig. 5, item 56).
With respect to claim 2, Young teaches the pixel circuit of claim 1, discussed above, further comprising:
a front plate lamination top electrode forming a front plate lamination capacitor with the pixel electrode (Figs. 1-9. At least Fig. 5, item 42).
With respect to claim 3, Young teaches the pixel circuit of claim 1, discussed above, wherein the selection unit is an inverter (Figs. 1-9. At least Fig. 5, item 42 includes an inverter item 58).
With respect to claim 4, Young teaches the pixel circuit of claim 1, discussed above, wherein the selection unit is a buffer (Figs. 1-9. At least Fig. 5, item 42 teaches a buffer unit).
With respect to claim 5, Young teaches the pixel circuit of claim 1, discussed above, wherein the selection unit includes a high voltage source and a low voltage source (Figs. 1-9. At least Fig. 5, item 42 includes 15V and 0V).
With respect to claim 6, Young teaches the pixel circuit of claim 1, discussed above, wherein a second end of the storage capacitor is electrically connected with a high voltage source (Figs. 1-9. At least Fig. 5, item 50 is electrically connected to +10V).
With respect to claim 7, Young teaches the pixel circuit of claim 1, discussed above, wherein a second end of the storage capacitor is electrically connected with a low voltage source (Figs. 1-9. At least Fig. 5, item 50 is electrically connected to 0V).
With respect to claim 8, Young teaches the pixel circuit of claim 1, discussed above, wherein the selection unit includes a plurality of second transistors, and the first transistor and the plurality of second transistors have the same polarity (Figs. 1-9. At least Fig. 5, items T5 and T6 have the same polarity as T7).
With respect to claim 9, Young teaches the pixel circuit of claim 8, discussed above, wherein the plurality of second transistors of the selection unit are N type transistors (Figs. 1-9. At least Fig. 5, items T5 and T6).
With respect to claim 11, Young teaches the pixel circuit of claim 1, discussed above, wherein a second end of the storage capacitor is connected to a common voltage (Figs. 1-9. At least Fig. 5, item 50).
With respect to claim 12, Young teaches a pixel circuit (Figs. 1-9), comprising:
a first transistor comprising a gate electrode, a source electrode, and a drain electrode (Figs. 1-9. At least Fig. 5, item T7);
a scan line electrically connected with the gate electrode of the first transistor (Figs. 1-9. At least Fig. 5, item 64);
a data line electrically connected with the source electrode of the first transistor (Figs. 1-9. At least Fig. 5, item 62);
a selection unit electrically connected with the drain electrode of the first transistor, wherein the selection unit includes a plurality of second transistors having the same polarity (Figs. 1-9. At least Fig. 5, item 54 teaches a selection unit. Fig. 5, items T1-T4 and T5/T6 teach a plurality of second transistors having the same polarity); and
a storage capacitor, wherein a first end of the storage capacitor is electrically connected with the drain electrode of the first transistor and an input node of the selection unit, and a second end of the storage capacitor is electrically connected with a high voltage source or a low voltage source (Figs. 1-9. At least Fig. 5, item 50 is electrically connected to both +10V and 0V).
With respect to claim 13, Young teaches the pixel circuit of claim 12, discussed above, further comprising:
a pixel electrode electrically connected with an output node of the selection unit, and wherein the selection unit provides a driving voltage to the pixel electrode (Figs. 1-9. At least Fig. 5, item 56).
With respect to claim 14, Young teaches the pixel circuit of claim 13, discussed above, further comprising:
a front plate lamination top electrode forming a front plate lamination capacitor with the pixel electrode (Figs. 1-9. At least Fig. 5, item 42).
With respect to claim 15, Young teaches the pixel circuit of claim 12, discussed above, wherein the first transistor and the plurality of second transistors have the same polarity (Figs. 1-9. At least Fig. 5, items T5 and T6 have the same polarity as T7).
With respect to claim 16, Young teaches the pixel circuit of claim 12, discussed above, wherein the selection unit is an inverter (Figs. 1-9. At least Fig. 5, item 42 includes an inverter item 58).
With respect to claim 17, Young teaches the pixel circuit of claim 12, discussed above, wherein the selection unit is a buffer (Figs. 1-9. At least Fig. 5, item 42 teaches a buffer unit).
With respect to claim 18, Young teaches the pixel circuit of claim 12, discussed above, wherein the selection unit connects with the high voltage source and the low voltage source (Figs. 1-9. At least Fig. 5, item 42 connects to 15V and 0V).
With respect to claim 19, Young teaches the pixel circuit of claim 12, discussed above, wherein the plurality of second transistors of the selection unit are N type transistors (Figs. 1-9. At least Fig. 5, items T5 and T6).
With respect to claim 20, Young teaches the pixel circuit of claim 12, discussed above, wherein the plurality of second transistors of the selection unit are P type transistors (Figs. 1-9. At least Fig. 5, item T1-T4).
*Examiner notes an alternative interpretation of claim 8 is required for dependent claim 10
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 10 is rejected under 35 U.S.C. 103 as being unpatentable over Young (TW200809718A) (Machine translation used).
With respect to claim 10, Young teaches the pixel circuit of claim 8, discussed above, wherein the plurality of second transistors of the selection unit are P type transistors (Figs. 1-9. At least Fig. 5, items T1 and T2).
However, Young fails to expressly teach that the first transistor and the plurality of second transistors have the same polarity (Examiner notes claim 10 is dependent on claim 8 which includes this limitation).
Examiner takes Official Notice that swapping a transistor type from N type to P type and vice versa including inverting respective control signals to maintain circuit functionality is well known in the art.
Young teaches a base process/product of a pixel circuit including an N type first transistor and a plurality of P type second transistors which the claimed invention can be seen as an improvement in that the first transistor and the plurality of second transistors have the same polarity. Official Notice teaches a known technique of swapping a transistor type from N type to P type and vice versa including inverting respective control signals to maintain circuit functionality that is comparable to the base process/product.
Official Notice’s known technique of swapping a transistor type from N type to P type and vice versa including inverting respective control signals to maintain circuit functionality would have been recognized by one skilled in the art as applicable to the base process/product of Young and the results would have been predictable and resulted in replacing the first transistor with a P type transistor such that the first transistor and the plurality of second transistors have the same polarity which results in an improved process/product.
Therefore, the claimed subject matter would have been obvious to a person having ordinary skill in the art.
The rationale to support a conclusion that the claim would have been obvious is that a particular known technique was recognized as part of the ordinary capabilities of one skilled in the art. One of ordinary skill in the art would have been capable of applying this known technique to a known device (method, or product) that was ready for improvement and the results would have been predictable to one of ordinary skill in the art.
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to Applicant's disclosure:
Kuo et al. (USPN 2018/0158388 teaches an e-paper display including an electronic ink layer;
Lin et al. (USPN 2019/0122603) teaches current leakage in an e-paper display; and
Paragraph [0085] of Wang (USPN 2022/0310009) teaches swapping N type and P type transistors.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTONIO J XAVIER whose telephone number is (571)270-7688. The examiner can normally be reached on M-F 830am-5pm PST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, PATRICK EDOUARD can be reached on 571-272-7603. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ANTONIO XAVIER/
Primary Examiner, Art Unit 2622
Prosecution Insights