Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the application filed September 23, 2025, claims 1-20 are presented for examination. Claim 1 is an independent claim.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119(a)-(d), and based on application # 10-2024-0190710 filed in the Republic of Korea on December 19, 2024 which papers have been placed of record in the file.
Oath/Declaration
The Office acknowledges receipt of a properly signed Oath/Declaration submitted September 23, 2025.
Information Disclosure Statement
The Applicant’s Information Disclosure Statement filed (September 23, 2025) has been received, entered into the record, and considered.
Drawings
The drawings filed September 23, 2025 are accepted by the examiner.
Abstract
The abstract filed September 23, 2025 is accepted by the examiner.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
8. Claims 1-20 in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “configured” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “configured” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the words “a timing controlling unit configured to,
a data driving unit configured to,
a gate driving unit configured to,
a display panel configured to,
in a claim, such as in claim 1 with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 2 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (US 20180012542 A1) in view of Park (US 20160365070 A1).
As to Claim 1:
Lee et al. discloses a display device (Lee, see Abstract, where Lee discloses that a display panel includes a displaying area including pixels, a non-displaying area including a dummy pixel, and a switching circuit to transfer a data signal to the dummy pixel in response to a control signal. The display panel may compensate for defective pixels located in different data lines using only one dummy pixel column and may minimize an area (e.g., a dead space) including the dummy pixel
column by including a distributor buffering a signal of an output line and a switching circuit selecting/providing a portion of a signal of the output line to a dummy data line), comprising: a timing controlling unit (Lee, see timing controller 140 in figure 1) configured to generate data (Lee, see paragraphs [0045] and [0032], where Lee discloses that the timing controller 140 may convert the input data to be used by the data driver 130, control the scan driver 120, and control the data driver 130. The display device 100 may display an image based on input data. For example, the timing controller 140 may generate the data driving control signal DCS and may provide the converted data (e.g., the second data DATA2) and the data driving control signal DCS to the data driver 130. The timing controller 140 may generate and provide the scan driving control signal SCS to the scan driver 120. The timing controller 140 may generate and provide the control signal CL ( or the first through third control signal) and the fourth control signal CL (or the repairing control signal) to the display panel 110), a data control signal and a gate control signal (Lee, see paragraphs [0045] and [0032], where Lee discloses that the timing controller 140 may convert the input data to be used by the data driver 130, control the scan driver 120, and control the data driver 130. The display device 100 may display an image based on input data. For example, the timing controller 140 may generate the data driving control signal DCS and may provide the converted data (e.g., the second data DATA2) and the data driving control signal DCS to the data driver 130. The timing controller 140 may generate and provide the scan driving control signal SCS to the scan driver 120. The timing controller 140 may generate and provide the control signal CL ( or the first through third control signal) and the fourth control signal CL (or the repairing control signal) to the display panel 110); a data driving unit (Lee, see Data Driver 130 in figure 1) configured to generate a data signal using the data and the data control signal (Lee, see paragraphs [0044], [0045] and [0032], where Lee discloses that the data driver 130 may generate the data signal corresponding to converted data (e.g., second data DATA2) using reference gamma voltages and may provide the data signal to the display panel 110 through the output lines 01 through Ok. The timing controller 140 provides the converted data (e.g., the second data DATA2) and the data driving control signal DCS to the data driver 130. The data driver 130 may sequentially output certain data signals (e.g., first through third data signals) to a certain output line (e.g., the first output line 01) because the display panel 110 ( or the display device 100) includes the distributor 111); a gate driving unit (Lee, see Scan driver 120 in figure 1) configured to generate a gate signal using the gate control signal (Lee, see paragraph [0042], where Lee discloses that the scan driver 120 may generate a scan signal based on a scan driving control signal SCS. The scan driving control signal SCS may include a start signal ( or a start pulse) and clock signals, and the scan driver 120 may include gate driving units (or shift registers) sequentially generating the scan signal based on the start signal and the clock signals); and a display panel (Lee, see display panel 110 in figure 1 and paragraph [0032], where Lee discloses that the display device 100 may include a display panel 110) configured to display an image using the gate signal and the data signal (Lee, see paragraph [0033], where Lee discloses that the display panel 110 may include data lines Dl through Dm, a dummy data line DO, scan lines Sl through Sn, light emission control signal lines El through En, dummy lines DLl through DLn (or repairing lines), pixels Pll through Pnm, dummy pixels Pdl through Pdm, a distributor 111, and a switching circuit 112, where each of m and n is a positive integer. The pixels Pll through Pnm may be included in a displaying region DR (or an active area)), the display panel (Lee, see display panel 110 in figure 1) comprising a display area (Lee, see display region DR as per figure 1 and paragraph [0033]) and a non-display area at a periphery of the display area (Lee, see non-displaying region NDR (or a non-active area) as per figure 1 and paragraph [0033]), wherein: the display area comprises a plurality of subpixels arranged as a plurality of horizontal pixel lines (Lee, see paragraph [0004], where Lee discloses that three sub pixels ( e.g., three sub pixels included in the same pixel row)), the non-display area comprises a plurality of dummy subpixels (Lee, see paragraph [0033], where Lee discloses that the dummy pixels Pdl through Pdm may be included in
a non-displaying region NDR (or a non-active area)).
Lee differs from the claimed subject matter in that Lee discloses that a plurality of repair lines (Lee, see DL1 through DLn in figure 1 and paragraph [0033], where Lee discloses dummy lines DLl through DLn (or repairing lines)), extend to the plurality of horizontal pixel lines (Lee, see D0, DL1 through DLn connected to horizontal pixel lines P11 through Pnm to the dummy pixels Pd1 through Pdm as shown in figure 1 and paragraph [0040], where Lee discloses that the dummy lines DLl through DLn may electrically connect the pixels P11 through Pnm to the dummy pixels Pdl through Pdm. For example, a first dummy line DLl may electrically connect one of the eleventh pixel P11 through mth pixel Pm to the first dummy pixel Pdl), respectively, and each of the plurality of dummy subpixels is connected to at least two of the plurality of repair lines extending to at least two of the plurality of horizontal pixel lines (Lee, see D0, DL1 through DLn connected to horizontal pixel lines P11 through Pnm to the dummy pixels Pd1 through Pdm as shown in figure 1 and paragraph [0040], where Lee discloses that the dummy lines DLl through DLn may electrically connect the pixels P11 through Pnm to the dummy pixels Pdl through Pdm. For example, a first dummy line DLl may electrically connect one of the eleventh pixel P11 through mth pixel Pm to the first dummy pixel Pdl).
PNG
media_image1.png
850
1114
media_image1.png
Greyscale
Lee differs from the claimed subject matter in that Lee does not explicitly disclose timing controlling unit configured to generate image data.
However in an analogous art, Park discloses timing controlling unit configured to generate image data (Park, see paragraph [0046], where Park discloses that a timing controller 110 may generate a data driving control signal DCS and a scan driving control signal SCS in response to synchronization signals (e.g., a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and/or a video data signal). The timing controller 110 may supply the data driving control signal DCS to the data driver 130, and may supply the scan driving control signal SCS to the scan driver 120. Also, the timing controller 110 may supply externally supplied video data "Data" to the data driver 130).
It would have been obvious to one of ordinary skill in the art to modify the invention of Lee with Park. One would be motivated to modify Lee by disclosing timing controlling unit configured to generate image data as taught by Park thereby emitting light with a desired brightness without generating a brightness deviation (Park, see paragraph [0007]).
As to Claim 2:
Lee in view of Park discloses that the display device of claim 1, wherein a number of the plurality of dummy subpixels is smaller than a number of the plurality of horizontal pixel lines (Park, see three horizontal pixel lines corresponding to one dummy subpixel DPx in figure 2).
Claims 3 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (US 20180012542 A1) in view of Park (US 20160365070 A1) in further view of Park2 (US 20230038359 A1).
As to Claim 3:
Lee in view of Park discloses that the display device of claim 1, wherein each of the plurality of subpixels includes a respective plurality of transistors (Lee, see T5, T1, T3, T2 and T4 in figure 2B), storage capacitor (Lee, see CST in figure 2B) and light emitting diode (Lee, see diode in 210 of figure 2B), and wherein each of the plurality of dummy subpixels (Lee, se 220 in figure 2B) includes a respective plurality of transistors (Lee, see T2, T5, T3, T1, T4 and T6 in figure 2B), storage capacitor (Lee, see CST in 220 in figure 2B) and auxiliary capacitor (Lee, see C_Sharing in 220 of figure 2B).
Lee in view of Park does not explicitly disclose an auxiliary capacitor included in each of the plurality of subpixels.
However in an analogous art, Park2 discloses auxiliary capacitor (Park, see Chold and Cld in figure 3).
It would have been obvious to one of ordinary skill in the art to modify the invention of Lee and Park with Park2. One would be motivated to modify Lee and Park by disclosing auxiliary capacitor as taught by Park2 thereby repair pixels (or dummy pixels) may be formed in the display device, and a bad pixel which has a defect may be connected to any one of the repair pixels (or dummy pixels), thereby repairing the bad pixel (Park2, see paragraph [0004]).
As to Claim 4:
Lee in view of Park in further view of Park2 discloses that the display device of claim 3, wherein each of the plurality of repair lines overlaps an anode of the light emitting diode of one of the plurality of subpixels (Lee, see anode of diode in 210 in figure 2B).
Allowable Subject Matter
Claims 5-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Referring to claim 5, the following is a statement of reasons for the indication of allowable subject matter: the prior art fail to suggest limitations “wherein when at least one of the plurality of transistors, the storage capacitor and the auxiliary capacitor of the one of the plurality of subpixels abnormally operates, a connection of the plurality of transistors and the light emitting diode in the one of the plurality of subpixels is cut, and the anode of the light emitting diode of the one of the plurality of subpixels is connected to one of the plurality of repair lines overlapping the anode”.
Referring to claim 6, the following is a statement of reasons for the indication of allowable subject matter: the prior art fail to suggest limitations “wherein the output line of each of the plurality of dummy subpixels outputs a current having a size depending from a capacitance ratio between the storage capacitor and the auxiliary capacitor”.
Referring to claim 7, the following is a statement of reasons for the indication of allowable subject matter: the prior art fail to suggest limitations “wherein an area of the auxiliary capacitor in each of the plurality of dummy subpixels is greater than an area of the auxiliary capacitor in each of the plurality of subpixels”.
Referring to claim 8, the following is a statement of reasons for the indication of allowable subject matter: the prior art fail to suggest limitations “wherein two output lines of two of the plurality of dummy subpixels are commonly connected to three of the plurality of repair lines corresponding to three of the plurality of horizontal pixel lines”.
Referring to claim 9, the following is a statement of reasons for the indication of allowable subject matter: the prior art fail to suggest limitations “wherein three output lines of three of the plurality of dummy subpixels are commonly connected to four of the plurality of repair lines corresponding to four of the plurality of horizontal pixel lines”.
Referring to claim 10, the following is a statement of reasons for the indication of allowable subject matter: the prior art fail to suggest limitations “a plurality of gate lines extending to the plurality of horizontal pixel lines, respectively, to transmit the gate signal; and an input line connected to a gate electrode of at least one of the plurality transistors of each of the plurality of dummy subpixels, wherein when at least one of the plurality of transistors, the storage capacitor and the auxiliary capacitor of the one of the plurality of subpixels abnormally operates, one of the plurality of gate lines corresponding to the one of the plurality of subpixels is connected to the input line”.
Referring to claim 11, the following is a statement of reasons for the indication of allowable subject matter: the prior art fail to suggest limitations “wherein the plurality of horizontal pixel lines include (N−1)th, (N)th and (N+1)th horizontal pixel lines, wherein the plurality of subpixels include an (N−1)th subpixel in the (N−1)th horizontal pixel line, an (N)th subpixel in the (N)th horizontal pixel line and an (N+1)th subpixel in the (N+1)th horizontal pixel line, wherein the plurality of dummy subpixels include (N−1)th and (N)th dummy subpixels, wherein the plurality of repair lines include (N−1)th, (N)th and (N+1)th repair lines overlapping the anodes of the light emitting diodes of the (N−1)th, (N)th and (N+1)th subpixels, respectively, and wherein an (N−1)th output line of the (N−1)th dummy subpixel and an (N)th output line of the (N)th dummy subpixel are connected to a first connecting line connecting the (N−1)th, (N)th and (N+1)th repair lines”.
Referring to claim 12, the following is a statement of reasons for the indication of allowable subject matter: the prior art fail to suggest limitations “wherein when at least one of the plurality of transistors, the storage capacitor and the auxiliary capacitor of the (N−1)th subpixel abnormally operates and at least one of the plurality of transistors, the storage capacitor and the auxiliary capacitor of the (N)th subpixel abnormally operates, a connection of the (N−1)th output line and the (N)th repair line is cut, and a connection of the (N)th output line and the (N+1)th repair line is cut”.
Referring to claim 13, the following is a statement of reasons for the indication of allowable subject matter: the prior art fail to suggest limitations “wherein data signals corresponding to the (N−1)th and (N)th subpixels are supplied to the (N−1)th and (N)th dummy subpixels, respectively”.
Referring to claim 14, the following is a statement of reasons for the indication of allowable subject matter: the prior art fail to suggest limitations “wherein when at least one of the plurality of transistors, the storage capacitor and the auxiliary capacitor of the (N−1)th subpixel abnormally operates and at least one of the plurality of transistors, the storage capacitor and the auxiliary capacitor of the (N+1)th subpixel abnormally operates, a connection of the (N−1)th output line and the (N)th repair line is cut, and a connection of the (N)th output line and the (N)th repair line is cut”.
Referring to claim 15, the following is a statement of reasons for the indication of allowable subject matter: the prior art fail to suggest limitations “wherein data signals corresponding to the (N−1)th and (N+1)th subpixels are supplied to the (N−1)th and (N)th dummy subpixels, respectively”.
Referring to claim 16, the following is a statement of reasons for the indication of allowable subject matter: the prior art fail to suggest limitations “wherein when at least one of the plurality of transistors, the storage capacitor and the auxiliary capacitor of the (N)th subpixel abnormally operates and at least one of the plurality of transistors, the storage capacitor and the auxiliary capacitor of the (N+1)th subpixel abnormally operates, a connection of the (N−1)th output line and the (N−1)th repair line is cut, and a connection of the (N)th output line and the (N)th repair line is cut”.
Referring to claim 17, the following is a statement of reasons for the indication of allowable subject matter: the prior art fail to suggest limitations “wherein data signals corresponding to the (N)th and (N+1)th subpixels are supplied to the (N−1)th and (N)th dummy subpixels, respectively”.
Referring to claim 18, the following is a statement of reasons for the indication of allowable subject matter: the prior art fail to suggest limitations “comprising: (N−1)th, (N)th and (N+1)th gate lines connected to the (N−1)th, (N)th and (N+1)th subpixels, respectively, and (N−1)th and (N)th input lines connected to a gate electrode of at least one of the plurality of transistors of the (N−1)th dummy subpixel and a gate electrode of at least one of the plurality of transistors of the (N)th dummy subpixel, respectively, wherein when at least one of the plurality of transistors, the storage capacitor and the auxiliary capacitor of the (N−1)th subpixel abnormally operates and at least one of the plurality of transistors, the storage capacitor and the auxiliary capacitor of the (N)th subpixels abnormally operates, the (N−1)th input line is connected to the (N−1)th gate line, and the (N)th input line is connected to the (N)th gate line, wherein when at least one of the plurality of transistors, the storage capacitor and the auxiliary capacitor of the (N−1)th subpixel abnormally operates and at least one of the plurality of transistors, the storage capacitor and the auxiliary capacitor of the (N+1)th subpixel abnormally operates, the (N−1)th input line is connected to the (N−1)th gate line, and the (N)th input line is connected to the (N+1)th gate line, wherein when at least one of the plurality of transistors, the storage capacitor and the auxiliary capacitor of the (N)th subpixel abnormally operates and at least one of the plurality of transistors, the storage capacitor and the auxiliary capacitor of the (N+1)th subpixel abnormally operates, the (N−1)th input line is connected to the (N)th gate line, and the (N)th input line is connected to the (N+1)th gate line”.
Referring to claim 19, the following is a statement of reasons for the indication of allowable subject matter: the prior art fail to suggest limitations “wherein the respective plurality of transistors for each subpixel and for each dummy subpixel comprises: a first transistor switched according to a voltage of a first node and connected to a second node; a second transistor switched according to a scan1 signal and connected to the first node and the data signal; a third transistor switched according to a scan2 signal and connected to the first node and a reference signal; a fourth transistor switched according to a scan3 signal and connected to a third node and an anode reset signal; a fifth transistor switched according to an emission1 signal and connected to the first transistor and a high level signal; and a sixth transistor switched according to an emission2 signal and connected to the third node and the second node”
Referring to claim 20, the following is a statement of reasons for the indication of allowable subject matter: the prior art fail to suggest limitations “wherein a gate electrode of the first transistor, a first capacitor electrode of the storage capacitor, a source electrode of the second transistor and a source electrode of the third transistor constitute the first node, wherein a source electrode of the first transistor, a second capacitor electrode of the storage capacitor, a first capacitor electrode of the auxiliary capacitor and a drain electrode of the sixth transistor constitute the second node, and wherein a source electrode of the fourth transistor and a source electrode of the sixth transistor constitute the third node”
Conclusion
The prior art made of record and not relied upon is considered pertinent to
applicant's disclosure. Park (US 20160372029 A1) discloses a display device includes a plurality of pixels at respective crossing regions of data lines and scan lines, a plurality of repair lines in parallel with the scan lines, one or more dummy pixels coupled to a respective one of the repair lines, one or more dummy data lines that are respectively coupled to the one or more of the dummy pixels, and that overlap the data lines, and a test line coupled between a first test pad and the dummy pixels.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NELSON ROSARIO whose telephone number is (571)270-1866. The examiner can normally be reached on Monday through Friday, 7:30am- 5:00pm EST. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Eason can be reached on (571) 270-7230. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/NELSON M ROSARIO/ Primary Examiner, Art Unit 2624
Prosecution Insights