CTNF 19/339,198 CTNF 90238 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-01-aia AIA 07-03-01-r-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claims 1-20 are pending. Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA/25, or PTO/AIA/26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. 08-34 AIA Claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over Claim 2 of U.S. Patent No. 12,456,533 . Although the claims at issue are not identical, they are not patentably distinct from each other because the reference application Claim anticipates the examined application Claim . MPEP 804.II.B.2 states: a nonstatutory double patenting rejection is appropriate where a claim in an application under examination claims subject matter that is different, but not patentably distinct, from the subject matter claimed in a prior patent or a copending application. The claim under examination is not patentably distinct from the reference claim(s) if the claim under examination is anticipated by the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 1052, 29 USPQ2d 2010, 2015-16 (Fed. Cir. 1993). US Patent 12,456,533 (Reference Application) US Patent Application 19/339,198 (Examined Application) 1. A shift register, comprising a first control sub-circuit, a second control sub-circuit, a third control sub-circuit, a first output sub-circuit, and a second output sub-circuit; the first control sub-circuit is respectively connected with a signal input terminal, a first node, a second node, a first clock signal terminal, a second clock signal terminal, and a first power supply terminal, and is configured to provide a signal of the signal input terminal to the first node under control of signals from the first clock signal terminal, the second clock signal terminal, the second node, and the first power supply terminal and maintain a potential of the first node; the second control sub-circuit is respectively connected with a second power supply terminal, the first clock signal terminal, the first node, and the second node, and is configured to provide a signal of the second power supply terminal or the first clock signal terminal to the second node under control of signals from the first clock signal terminal and the first node; the third control sub-circuit is respectively connected with the first node, the second node, a fourth node, the second clock signal terminal, and the first power supply terminal, and is configured to provide a signal of the second clock signal terminal or the first power supply terminal to the fourth node under control of signals from the second clock signal terminal, the first node, and the second node and maintain a potential of the fourth node; the first output sub-circuit is respectively connected with the first power supply terminal, the second power supply terminal, the first node, the fourth node, and a first signal output terminal, and is configured to provide a signal of the first power supply terminal or the second power supply terminal to the first signal output terminal under control of signals from the first node and the fourth node; and the second output sub-circuit is connected with the first signal output terminal, the third control sub-circuit, the first power supply terminal, the second power supply terminal, and a second signal output terminal, respectively, and is configured to provide a signal of the first power supply terminal or the second power supply terminal to the second signal output terminal under control of signals from the third control sub-circuit and the first signal output terminal. 2. The shift register according to claim 1, wherein the first control sub-circuit comprises a first transistor, a fourth transistor, a fifth transistor, and a first capacitor, and the first capacitor comprises a first electrode plate and a second electrode plate; a control electrode of the first transistor is connected with the first clock signal terminal, a first electrode of the first transistor is connected with the signal input terminal, and a second electrode of the first transistor is connected with the first node; a control electrode of the fourth transistor is connected with the second node, a first electrode of the fourth transistor is connected with the first power supply terminal, and a second electrode of the fourth transistor is connected with a seventh node; a control electrode of the fifth transistor is connected with the second clock signal terminal, a first electrode of the fifth transistor is connected with the seventh node, and a second electrode of the fifth transistor is connected with the first node; the first electrode plate of the first capacitor is connected with the first node, and the second electrode plate of the first capacitor is connected with the second clock signal terminal, or the first control sub-circuit comprises a first transistor, a fourth transistor, a fifth transistor, a first capacitor, and a fourth capacitor, the first capacitor comprises a first electrode plate and a second electrode plate, and the fourth capacitor comprises a first electrode plate and a second electrode plate; a control electrode of the first transistor is connected with the first clock signal terminal, a first electrode of the first transistor is connected with the signal input terminal, and a second electrode of the first transistor is connected with the first node; a control electrode of the fourth transistor is connected with the second node, a first electrode of the fourth transistor is connected with the first power supply terminal, and a second electrode of the fourth transistor is connected with a seventh node; a control electrode of the fifth transistor is connected with the first node, a first electrode of the fifth transistor is connected with the second clock signal terminal, and a second electrode of the fifth transistor is connected with the seventh node; the first electrode plate of the first capacitor is connected with the first node, and the second electrode plate of the first capacitor is connected with the first signal output terminal; the first electrode plate of the fourth capacitor is connected with the seventh node, and the second electrode plate of the fourth capacitor is connected with the first node, or, the first control sub-circuit comprises a first transistor, a fourth transistor, a fifth transistor, and a first capacitor, and the first capacitor comprises a first electrode plate and a second electrode plate; the second control sub-circuit comprises a second transistor and a third transistor; the third control sub-circuit comprises a sixth transistor, a seventh transistor, an eighth transistor, a second capacitor, and a third capacitor; the first output sub-circuit comprises a ninth transistor and a tenth transistor; the second output sub-circuit comprises an eleventh transistor, a twelfth transistor, a thirteenth transistor, and a fourteenth transistor; a control electrode of the first transistor is connected with the first clock signal terminal, a first electrode of the first transistor is connected with the signal input terminal, and a second electrode of the first transistor is connected with the first node; a control electrode of the second transistor is connected with the first clock signal terminal, a first electrode of the second transistor is connected with the second power supply terminal, and a second electrode of the second transistor is connected with the second node; a control electrode of the third transistor is connected with the first node, a first electrode of the third transistor is connected with the first clock signal terminal, and a second electrode of the third transistor is connected with the second node; a control electrode of the fourth transistor is connected with the second node, a first electrode of the fourth transistor is connected with the first power supply terminal, and a second electrode of the fourth transistor is connected with a seventh node; a control electrode of the fifth transistor is connected with the second clock signal terminal, a first electrode of the fifth transistor is connected with the seventh node, and a second electrode of the fifth transistor is connected with the first node; a control electrode of the sixth transistor is connected with the second node, a first electrode of the sixth transistor is connected with the second clock signal terminal, and a second electrode of the sixth transistor is connected with a third node; a control electrode of the seventh transistor is connected with the second clock signal terminal, a first electrode of the seventh transistor is connected with the third node, and a second electrode of the seventh transistor is connected with the fourth node; a control electrode of the eighth transistor is connected with the first node, a first electrode of the eighth transistor is connected with the first power supply terminal, and a second electrode of the eighth transistor is connected with the fourth node; a control electrode of the ninth transistor is connected with the fourth node, a first electrode of the ninth transistor is connected with the first power supply terminal, and a second electrode of the ninth transistor is connected with the first signal output terminal; a control electrode of the tenth transistor is connected with the first node, a first electrode of the tenth transistor is connected with the second power supply terminal, and a second electrode of the tenth transistor is connected with the first signal output terminal; a control electrode of the eleventh transistor is connected with the third node or the fourth node, a first electrode of the eleventh transistor is connected with the second power supply terminal, and a second electrode of the eleventh transistor is connected with a sixth node; a control electrode of the twelfth transistor is connected with the first signal output terminal, a first electrode of the twelfth transistor is connected with the first power supply terminal, and a second electrode of the twelfth transistor is connected with the sixth node; a control electrode of the thirteenth transistor is connected with the sixth node, a first electrode of the thirteenth transistor is connected with the second power supply terminal, and a second electrode of the thirteenth transistor is connected with the second signal output terminal; a control electrode of the fourteenth transistor is connected with the first signal output terminal, a first electrode of the fourteenth transistor is connected with the first power supply terminal, and a second electrode of the fourteenth transistor is connected with the second signal output terminal; the first electrode plate of the first capacitor is connected with the first node, and the second electrode plate of the first capacitor is connected with the second clock signal terminal; a first electrode plate of the second capacitor is connected with the second node, and a second electrode plate of the second capacitor is connected with the third node; a first electrode plate of the third capacitor is connected with the fourth node, and a second electrode plate of the third capacitor is connected with the first power supply terminal. 1. A shift register, comprising a first control sub-circuit, a second control sub-circuit, a third control sub-circuit, a first output sub-circuit, and a second output sub-circuit; the first control sub-circuit is respectively connected with a signal input terminal, a first node, a second node, a first clock signal terminal, a second clock signal terminal, and a first power supply terminal, and is configured to provide a signal of the signal input terminal to the first node under control of the first clock signal terminal, the second clock signal terminal, the second node, and the first power supply terminal and maintain a potential of the first node; the second control sub-circuit is respectively connected with a second power supply terminal, the first clock signal terminal, the first node, and the second node, and is configured to provide a signal of the second power supply terminal or the first clock signal terminal to the second node under control of the first clock signal terminal and the first node; the third control sub-circuit is respectively connected with the first node, the second node, a fourth node, the second clock signal terminal, and the first power supply terminal, and is configured to provide a signal of the second clock signal terminal or the first power supply terminal to the fourth node under control of the second clock signal terminal, the first node, and the second node and maintain a potential of the fourth node; the first output sub-circuit is respectively connected with the first power supply terminal, the second power supply terminal, the first node, the fourth node, and a first signal output terminal, and is configured to provide a signal of the first power supply terminal or the second power supply terminal to the first signal output terminal under control of the first node and the fourth node; and the second output sub-circuit is connected with the first signal output terminal, the third control sub-circuit, the first power supply terminal, the second power supply terminal, and a second signal output terminal, respectively and is configured to provide a signal of the first power supply terminal or the second power supply terminal to the second signal output terminal under control of the third control sub-circuit and the first signal output terminal, wherein the first control sub-circuit comprises a first transistor, a fourth transistor, a fifth transistor, and a first capacitor, and the first capacitor comprises a first electrode plate and a second electrode plate; a control electrode of the first transistor is connected with the first clock signal terminal, a first electrode of the first transistor is connected with the signal input terminal, and a second electrode of the first transistor is connected with the first node; a control electrode of the fourth transistor is connected with the second node, a first electrode of the fourth transistor is connected with the first power supply terminal, and a second electrode of the fourth transistor is connected with a seventh node; a control electrode of the fifth transistor is connected with the second clock signal terminal, a first electrode of the fifth transistor is connected with the seventh node, and a second electrode of the fifth transistor is connected with the first node; the first electrode plate of the first capacitor is connected with the first node, and the second electrode plate of the first capacitor is connected with the second clock signal terminal . 08-34 AIA Claim 9 is rejected on the ground of nonstatutory double patenting as being unpatentable over Claim 15 of U.S. Patent No. 12,456,533 . Although the claims at issue are not identical, they are not patentably distinct from each other because the reference application Claim anticipates the examined application Claim . 12,456,533 (Reference Application) 19/339,198 (Examined Application) 12. A display substrate, comprising a base substrate and a circuit structure layer disposed on the base substrate, the circuit structure layer comprises a light emitting drive circuit, and the light emitting drive circuit comprises a plurality of cascaded shift registers; a first signal output terminal of a shift register in an i-th stage is electrically connected with a signal input terminal of a shift register in an (i+1)-th stage , wherein 1<i<M-1 and M is a total number of stages of the shift registers; at least one shift register comprises a first control sub-circuit, a second control sub-circuit, a third control sub-circuit, a first output sub-circuit, and a second output sub-circuit; the first control sub-circuit is respectively connected with a signal input terminal, a first node, a second node, a first clock signal terminal, a second clock signal terminal, and a first power supply terminal, and is configured to provide a signal of the signal input terminal to the first node under control of signals from the first clock signal terminal, the second clock signal terminal, the second node, and the first power supply terminal and maintain a potential of the first node; the second control sub-circuit is respectively connected with a second power supply terminal, the first clock signal terminal, the first node, and the second node, and is configured to provide a signal of the second power supply terminal or the first clock signal terminal to the second node under control of signals from the first clock signal terminal and the first node; the third control sub-circuit is respectively connected with the first node, the second node, a fourth node, the second clock signal terminal, and the first power supply terminal, and is configured to provide a signal of the second clock signal terminal or the first power supply terminal to the fourth node under control of signals from the second clock signal terminal, the first node, and the second node and maintain a potential of the fourth node; the first output sub-circuit is respectively connected with the first power supply terminal, the second power supply terminal, the first node, the fourth node, and the first signal output terminal, and is configured to provide a signal of the first power supply terminal or the second power supply terminal to the first signal output terminal under control of signals from the first node and the fourth node; the second output sub-circuit is connected with the first signal output terminal, the third control sub-circuit, the first power supply terminal, the second power supply terminal, and the second signal output terminal, respectively, and is configured to provide a signal of the first power supply terminal or the second power supply terminal to the second signal output terminal under control of signals from the third control sub-circuit and the first signal output terminal, 13. The display substrate according to claim 12, further comprising: an initial signal line, a first clock signal line, a second clock signal line, a second power supply line, and a third power supply line extending along a second direction, the initial signal line, the first clock signal line, the second clock signal line, the third power supply line, and the second power supply line are arranged along a first direction, and the first direction intersects with the second direction; a signal input terminal of a shift register in a first stage is electrically connected with the initial signal line, first power supply terminals of all shift registers are electrically connected with the third power supply line, second power supply terminals of all shift registers are electrically connected with the second power supply line, first clock signal terminals of shift registers in odd-numbered stages are connected with the first clock signal line, second clock signal terminals of shift registers in odd-numbered stages are connected with the second clock signal line, first clock signal terminals of shift registers in even-numbered stages are connected with the second clock signal line, and second clock signal terminals of shift registers in even-numbered stages are connected with the first clock signal line. 14. The display substrate according to claim 13, wherein the circuit structure layer comprises: a semiconductor layer, a first insulation layer, a first conductive layer, a second insulation layer, a second conductive layer, a third insulation layer, and a third conductive layer which are sequentially stacked on the base substrate; the semiconductor layer comprises: active layers of all transistors located in the light emitting drive circuit; the first conductive layer comprises: control electrodes of all transistors and a first electrode plate of a first capacitor to a first electrode plate of a third capacito r located in the light emitting drive circuit; the second conductive layer comprises a second electrode plate of the first capacitor to a second electrode plate of the third capacitor located in the light emitting drive circuit; the third conductive layer comprises an initial signal line, a first clock signal line, a second clock signal line, a first power supply line , and a second power supply line. 15. The display substrate according to claim 14, wherein the shift register comprises: a first transistor to a fourteenth transistor ; in a plane where the display substrate is located, in the first direction, all transistors and capacitors are located between the third power supply line and the second power supply line, a second capacitor is located between the third power supply line and an eighth transistor, the eighth transistor is located between the second capacitor and a ninth transistor and a tenth transistor, the ninth transistor and the tenth transistor are located between the eighth transistor and, an eleventh transistor and a twelfth transistor, the eleventh transistor and the twelfth transistor are located between the ninth transistor and the tenth transistor and a thirteenth transistor and the fourteenth transistor, and the thirteenth transistor and the fourteenth transistor are located between the eleventh transistor and the twelfth transistor and the second power supply line; in the second direction, the third capacitor, the ninth transistor, the tenth transistor, and the first capacitor are sequentially arranged along the second direction, the twelfth transistor and the eleventh transistor are sequentially arranged along the second direction, and the fourteenth transistor and the thirteenth transistor are sequentially arranged along the second direction. 9. A display substrate, comprising a base substrate and a circuit structure layer disposed on the base substrate, the circuit structure layer comprises a light emitting drive circuit, and the light emitting drive circuit comprises a plurality of cascaded shift registers; a first signal output terminal of a shift register in an i-th stage is electrically connected with a signal input terminal of a shift register in an (i+1)-th stage, wherein 1<i<M-1 and M is a total number of stages of the shift registers; at least one shift register comprises a first control sub-circuit, a second control sub-circuit, a third control sub-circuit, a first output sub-circuit, and a second output sub-circuit; the first control sub-circuit is respectively connected with a signal input terminal, a first node, a second node, a first clock signal terminal, a second clock signal terminal, and a first power supply terminal, and is configured to provide a signal of the signal input terminal to the first node under control of the first clock signal terminal, the second clock signal terminal, the second node, and the first power supply terminal and maintain a potential of the first node; the second control sub-circuit is respectively connected with a second power supply terminal, the first clock signal terminal, the first node, and the second node, and is configured to provide a signal of the second power supply terminal or the first clock signal terminal to the second node under control of the first clock signal terminal and the first node; the third control sub-circuit is respectively connected with the first node, the second node, a fourth node, the second clock signal terminal, and the first power supply terminal, and is configured to provide a signal of the second clock signal terminal or the first power supply terminal to the fourth node under control of the second clock signal terminal, the first node, and the second node and maintain a potential of the fourth node; the first output sub-circuit is respectively connected with the first power supply terminal, the second power supply terminal, the first node, the fourth node, and the first signal output terminal, and is configured to provide a signal of the first power supply terminal or the second power supply terminal to the first signal output terminal under control of the first node and the fourth node; the second output sub-circuit is connected with the first signal output terminal, the third control sub-circuit, the first power supply terminal, the second power supply terminal, and the second signal output terminal, respectively, and is configured to provide a signal of the first power supply terminal or the second power supply terminal to the second signal output terminal under control of the third control sub-circuit and the first signal output terminal, wherein the display substrate further comprises a first power supply line [claim 14], a second power supply line [claim 13], a third power supply line [claim 13], a first capacitor [claim 14], a second capacitor [claim 15] and a third capacitor [claim 14], the shift register comprises: a first transistor to a fourteenth transistor [claim 15] . Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. Claims 1-20 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which a joint inventor regards as the invention. Regarding Claims 1 and 9. Claims 1 and 12 contains several limitations, similar to the following examples: “configured to provide a signal of the signal input terminal to the first node under control of the first clock signal terminal , the second clock signal terminal, the second node, and the first power supply terminal and maintain a potential of the first node”, “configured to provide a signal of the second clock signal terminal or the first power supply terminal to the fourth node under control of the second clock signal terminal , the first node, and the second node and maintain a potential of the fourth node” The broadest reasonable interpretation (BRI) of the cited limitations is a passive circuit component actively controlling an input signal to achieve a claimed result. Control of the input signal is actually performed by varying a signal present on the passive circuit component. Claims 1 and 9 are indefinite because they contain limitations that do not accurately represent how the claimed circuit function is performed and can be reasonably interpreted as (1) passive circuit components performing an active control function and as (2) an active component at the location of the passive component performs an active control function. Regarding Claims 2-8, and 10-20 . Claims 2-8, and 10-20 are rejected under 35 USC §112(b) for containing the indefinite subject matter of their respective parent claim. In support of compact prosecution the limitations containing “under control of a [passive element]” are construed “under control of signals from the [passive element]”. Allowable Subject Matter Claims 1 and 9 would be allowable if rewritten or amended to overcome the rejection under 35 U.S.C. 112(b) set forth in this Office action. 07-43-02 Claims 2-8, and 10-20 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) set forth in this Office action and to include all of the limitations of the base claim and any intervening claims. 13-03-01 AIA The following is a statement of reasons for the indication of allowable subject matter: Claim 1 contains the following subject matter that is neither taught nor suggested by the prior art, either alone or in combination: a shift register, wherein the second output sub-circuit is connected with the first signal output terminal, the third control sub-circuit, the first power supply terminal, the second power supply terminal, and a second signal output terminal, respectively and is configured to provide a signal of the first power supply terminal or the second power supply terminal to the second signal output terminal under control of signals from the third control sub-circuit and the first signal output terminal. Claim 9 contains the following subject matter that is neither taught nor suggested by the prior art, either alone or in combination: a display substrate, comprising a plurality of cascaded shift registers; wherein the second output sub-circuit is connected with the first signal output terminal, the third control sub-circuit, the first power supply terminal, the second power supply terminal, and the second signal output terminal, respectively, and is configured to provide a signal of the first power supply terminal or the second power supply terminal to the second signal output terminal under control of signals from the third control sub-circuit and the first signal output terminal . Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Douglas Wilson whose telephone number is (571)272-5640. The examiner can normally be reached 1000-1800 EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Patrick Edouard can be reached at 571-272-7603. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Douglas Wilson/Primary Examiner, Art Unit 2622 Application/Control Number: 19/339,198 Page 2 Art Unit: 2622 Application/Control Number: 19/339,198 Page 3 Art Unit: 2622 Application/Control Number: 19/339,198 Page 4 Art Unit: 2622 Application/Control Number: 19/339,198 Page 5 Art Unit: 2622 Application/Control Number: 19/339,198 Page 6 Art Unit: 2622 Application/Control Number: 19/339,198 Page 7 Art Unit: 2622 Application/Control Number: 19/339,198 Page 8 Art Unit: 2622 Application/Control Number: 19/339,198 Page 9 Art Unit: 2622 Application/Control Number: 19/339,198 Page 10 Art Unit: 2622 Application/Control Number: 19/339,198 Page 11 Art Unit: 2622 Application/Control Number: 19/339,198 Page 12 Art Unit: 2622 Application/Control Number: 19/339,198 Page 13 Art Unit: 2622 Application/Control Number: 19/339,198 Page 14 Art Unit: 2622 Application/Control Number: 19/339,198 Page 15 Art Unit: 2622 Application/Control Number: 19/339,198 Page 16 Art Unit: 2622 Application/Control Number: 19/339,198 Page 17 Art Unit: 2622 Application/Control Number: 19/339,198 Page 19 Art Unit: 2622 Application/Control Number: 19/339,198 Page 20 Art Unit: 2622 Application/Control Number: 19/339,198 Page 21 Art Unit: 2622
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