DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Application
This office action is in response to the Application filed on 09/25/2025.
Claims 1-20 are presented for examination.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 21-40 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,436,902.
Comparison of claims is shown in the table below as an example.
Current application
US 12,436,902
21
obtaining memory registration information from a memory server, the memory registration information comprising a key for a memory registration at the memory server,
the memory registration information further comprising a location of a resource tracking entry for the memory registration;
performing a remote direct memory access operation at the memory server using the key; and updating the resource tracking entry for the memory registration by directly writing to the location of the resource tracking entry..
1
obtaining memory registration information from a memory server, the memory registration information comprising a key for a memory registration of a shared memory region of the memory server,
the memory registration information further comprising a location of a resource tracking entry for the memory registration, the location of the resource tracking entry comprising a location within a tracking memory region of the memory server;
accessing the shared memory region of the memory server by
performing a remote direct memory access operation using the key; and
updating the resource tracking entry for the memory registration by directly writing to the location within the tracking memory region of the memory server
.
22,
wherein the location of the resource tracking entry comprises a location within a tracking memory region
1
…the location of the resource tracking entry comprising a location within a tracking memory region of the memory server
23,
wherein directly writing to the location of the resource tracking entry comprises performing an atomic compare-and-exchange operation at the location of the resource tracking entry.
2
wherein writing to the location within the tracking memory region of the memory server comprises performing an atomic compare-and-exchange operation at the location within the tracking memory region of the memory server
24,
wherein the resource tracking entry comprises a status of the memory registration and a global reference count for the memory registration..
3
wherein the resource tracking entry comprises a status of the memory registration and a global reference count for the memory registration..
25,
wherein the resource tracking entry comprises a binary word, first bits of the binary word indicate the status of the memory registration, and second bits of the binary word indicate the global reference count for the memory registration
4
wherein the resource tracking entry comprises a binary word, a first portion of the binary word indicating the status of the memory registration, a second portion of the binary word indicating the global reference count for the memory registration.
26,
wherein updating the resource tracking entry for the memory registration comprises overwriting the binary word
5
wherein updating the resource tracking entry for the memory registration comprises overwriting the binary word
27,
wherein obtaining the memory registration information comprises: searching a local resource cache of the compute node for the memory registration information; and requesting the memory registration information from the memory server in response to the memory registration information being unavailable in the local resource cache
7
wherein obtaining the memory registration information comprises: searching a local resource cache of the compute node for the memory registration information; and
requesting the memory registration information from the memory server in response to the memory registration information being unavailable in the local resource cache
28,
wherein obtaining the memory registration information further comprises: taking the memory registration information from the local resource cache in response to the memory registration information being available in the local resource cache
8
wherein obtaining the memory registration information further comprises: taking the memory registration information from the local resource cache in response to the memory registration information being available in the local resource cache
29,
wherein requesting the memory registration information from the memory server comprises invoking a remote operation at the memory server.
9
wherein requesting the memory registration information from the memory server comprises sending a remote procedure call request to the memory server
30
creating a memory registration at a network interface card of the memory server;
storing a resource tracking entry for the memory registration; and
sending memory registration information to a compute node, the memory registration information comprising a key for the memory registration,
the memory registration information further comprising a location of the resource tracking entry
10
creating a memory registration by registering a shared memory region of the memory server with a network interface card of the memory server;
storing a resource tracking entry for the memory registration in a tracking memory region of the memory server; and
sending memory registration information to a compute node, the memory registration information comprising a key for the memory registration and a location of the resource tracking entry,
the location of the resource tracking entry comprising a location within the tracking memory region of the memory server
31
wherein the location of the resource tracking entry comprises a location within a tracking memory region
10
the location of the resource tracking entry comprising a location within the tracking memory region of the memory server
32
wherein the memory registration is for a shared memory region, and the tracking memory region and the shared memory region are both within a memory of the memory server
10
a memory registration by registering a shared memory region of the memory server with a network interface card of the memory server
33
wherein the resource tracking entry comprises a status of the memory registration and a global reference count for the memory registration
11
wherein the resource tracking entry comprises a status of the memory registration and a global reference count for the memory registration
34
wherein the resource tracking entry comprises a binary word, first bits of the binary word indicate the status of the memory registration, and second bits of the binary word indicate the global reference count for the memory registration
12
wherein the resource tracking entry comprises a binary word, a first portion of the binary word indicating the status of the memory registration, a second portion of the binary word indicating the global reference count for the memory registration
35
releasing the memory registration from the network interface card in response to the status of the memory registration being ready-to-release
13
unregistering the shared memory region from the network interface card in response to the status of the memory registration being ready-to-release
36
deallocating memory for the resource tracking entry.
14
after the unregistering of the shared memory region, deallocating memory for the resource tracking entry
37
wherein the releasing of the memory registration is performed by a background thread of the memory server
15
wherein the unregistering of the shared memory region is performed in the background of the memory server
38
a memory server configured to: create a memory registration at the memory server; store a resource tracking entry for the memory registration; and
create memory registration information comprising a key for the memory registration and a location of the resource tracking entry; and
a compute node configured to:
obtain the memory registration information from the memory server; perform a remote direct memory access operation at the memory server using the key; and update the resource tracking entry for the memory registration by directly writing to the location of the resource tracking entry.
18
a memory server configured to:
create a memory registration of a shared memory region of the memory server;
store a resource tracking entry for the memory registration in a tracking memory region of the memory server; and
create memory registration information comprising a key for the memory registration and a location of the resource tracking entry, the location of the resource tracking entry comprising a location within the tracking memory region of the memory server; and
a compute node configured to:
obtain the memory registration information from the memory server;
access the shared memory region of the memory server by performing a remote direct memory access operation using the key; and
update the resource tracking entry for the memory registration by directly writing to the location within the tracking memory region of the memory server.
39
wherein the location of the resource tracking entry comprises a location within a tracking memory region
18
…the location of the resource tracking entry comprising a location within the tracking memory region of the memory server
40
wherein the resource tracking entry comprises a binary word, first bits of the binary word indicate a status of the memory registration, and second bits of the binary word indicate a global reference count for the memory registration
19
wherein the resource tracking entry comprises a binary word, a first portion of the binary word indicating a status of the memory registration, a second portion of the binary word indicating a global reference count for the memory registration
Appropriate action is required.
Allowable Subject Matter
Claims 21-40 would be allowable if rejections on the ground of double patenting are overcome.
The following is an examiner’s statement of reasons for allowance:
Frank (US20150039712A1) teaches registering a memory region for RDMA, providing a corresponding access key to a remote client, caching the key, and using the key for subsequent RDMA operations. However, Frank does not teach providing, as part of the memory registration information, a location of a resource tracking entry for that registration, together with the claimed compute-node update of that entry by directly writing to the supplied location. See Frank, Figs. 2–3.
Forin (US6360220B1) teaches a memory registration cache having entries containing memory handles and in-use counters, returning an entry index with a memory handle, and using the index to decrement the entry’s counter after use. Forin also teaches removing unused entries and deregistering associated handles. However, these operations concern access to a local registration cache by threads or processes. Forin does not teach the claimed arrangement in which a memory server sends a compute node both a key for a registration at the memory server and a location of the corresponding resource tracking entry. Nor does Forin teach the claimed compute-node direct update of that entry in that arrangement. See Forin, Figs. 3–4 and 6–10.
Neverovitch (US20220413743A1) teaches remote atomic operations on shared metadata using offsets, including metadata associated with file reference counts and counter arrays. However, the identified metadata does not provide the claimed relationship between a memory registration, its key, and a resource tracking entry whose location is supplied to a compute node in the memory registration information. See Neverovitch, Figs. 3, 5A–5B, and 6A.
Shalev (US20170187496A1) teaches RDMA communications, remote memory access information, and atomic operations.
Tsirkin (US20150089010A1) teaches registering memory for RDMA transfers during virtual-machine migration and deregistering memory after transfer. These teachings do not supply the claimed registration-information arrangement linking a registration key with the location of a resource tracking entry for the same registration.
Venkataramani (US20220206852A1) teaches allocation and caching of pre-registered memory for RDMA, including assigning preregistered chunks to threads to facilitate lockless buffer acquisition. Its buffer-management teachings do not establish the claimed provision, from a memory server to a compute node, of the registration key and corresponding resource-tracking-entry location. See Venkataramani, Figs. 2A–4.
The Bell and Bonachea Firehose paper, “A New DMA Registration Strategy for Pinning-Based High Performance Networks” (2003), teaches reference counts associated with pinned memory buckets, accounting for local RDMA operations and remote mappings, and deferred deregistration. However, it does not teach supplying the compute node with the claimed tracking-entry location and having the compute node directly update that entry in the claimed arrangement. See §3.2 and Table 1.
The additional teachings of Messmer et al. (US20110093851A1), Fig. 1 and paragraphs [0022]–[0025], concerning atomically updated count and status fields, and US7549152B2, Figs. 4 and 6, concerning registration records and deferred cleanup, do not remedy these deficiencies.
Regarding independent claims 21 and 38, the prior art considered does not teach or render obvious the claimed combination of obtaining, from a memory server, memory registration information comprising both a registration key and a location of a resource tracking entry for that registration; performing RDMA using the key; and updating the corresponding resource tracking entry by directly writing to its location.
Regarding independent claim 30, the distinction resides in the claimed server-side combination of creating a memory registration at the server’s network interface card, storing a resource tracking entry for that registration, and sending a compute node memory registration information comprising both the registration key and the location of the corresponding resource tracking entry. Claim 30 does not require the compute node’s subsequent direct update.
Although the references establish that registration caching, usage counting, remote atomic operations, and deferred cleanup were individually known, their teachings, considered individually and in combination, do not provide a sufficient basis for arranging those features in the particular relationships recited in independent claims 21, 30, and 38. In particular, the identified record does not sufficiently support modifying the registration-key exchange to include the corresponding tracking-entry location and, for claims 21 and 38, using that location for the compute node’s direct update.
Accordingly, independent claims 21, 30, and 38, and claims 22–29, 31–37, and 39–40 depending therefrom, are allowable over the prior art considered.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
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/TRACY C CHAN/ Primary Examiner, Art Unit 2138
