Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This office action is in response to the application filed 9/26/2025 in which Claims 1-14 are pending.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 9/26/2025 was filed on the mailing date of the application. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Patent Publication 2022/0139302 to Tsuchihashi et al (“Tsuchihashi”).
As to Claim 1, Tsuchihashi teaches a display driving device of a pixel array having a plurality of gate lines and a plurality of data lines, and a plurality of pixel driving circuits respectively connected to the plurality of gate lines and the plurality of data lines (a pixel drive control device is configured to control driving of an array of pixels in M (M≥2) rows and N (N≥2) columns on a display device, see Abstract; in the display 14 of this drawing, M selection lines ST(1) to ST(M) extend in the horizontal (row) direction [plurality of gate lines], and N data lines DT(1) to DT(N) extend in the vertical (column) direction, see ¶ 0036),
the display driving device comprising: a data driver configured to output pixel data to the plurality of data lines; a data selection circuit configured to process the outputted pixel data and transmit the processed pixel data to the plurality of pixel driving circuits (data driver 200 applies data signals to the odd-numbered data lines DT(1), DT(3)…(an example of the columns to be driven) every other horizontal scanning period to apply a scanning signal to the selection lines ST. The data driver 200 does not apply a data signal to the even-numbered data lines DT(2), DT(4), …in the drawing, the data lines DT to which the data signal is applied are indicated as [ON], and the data lines DT to which the data signal is not applied are indicated as [OFF], see ¶ 0063);
a gate driver configured to output gate information to the plurality of gate lines; and a gate selection circuit configured to process the outputted gate information and control a timing at which the pixel data is stored in the plurality of pixel driving circuits (in a period of one field, the vertical scanning driver 100 first applies a scanning signal to the selection line ST(1) in the corresponding horizontal scanning period, but does not apply a scanning signal to the selection line ST(2) in the next horizontal scanning period. Then, the vertical scanning driver 100 applies a scanning signal to the selection line ST(3) in the next horizontal scanning period, but does not apply a scanning signal to the selection line ST(4) in the next horizontal scanning period. In the drawing, the selection lines ST to which the scanning signal is applied are indicated as [ON], and the selection lines ST to which the scanning signal is not applied are indicated as [OFF], see ¶ 0061; Also for the subsequent lines, the vertical scanning driver 100 similarly applies a scanning signal during the horizontal scanning period corresponding to the odd-numbered selection line ST (an example of the driven line), and does not apply a scanning signal during the horizontal scanning period corresponding to the even-numbered selection line ST, thus scanning of the selection lines ST every other line, see ¶ 0062),
wherein the data selection circuit and the gate selection circuit are configured to select some of the plurality of pixel driving circuits and to simultaneously store the processed pixel data in the selected pixel driving circuit (in a period of one field, the vertical scanning driver 100 first applies a scanning signal to the selection line ST(1) in the corresponding horizontal scanning period, but does not apply a scanning signal to the selection line ST(2) in the next horizontal scanning period. Then, the vertical scanning driver 100 applies a scanning signal to the selection line ST(3) in the next horizontal scanning period, but does not apply a scanning signal to the selection line ST(4) in the next horizontal scanning period. In the drawing, the selection lines ST to which the scanning signal is applied are indicated as [ON], and the selection lines ST to which the scanning signal is not applied are indicated as [OFF], see ¶ 0061; Also for the subsequent lines, the vertical scanning driver 100 similarly applies a scanning signal during the horizontal scanning period corresponding to the odd-numbered selection line ST (an example of the driven line), and does not apply a scanning signal during the horizontal scanning period corresponding to the even-numbered selection line ST, thus scanning of the selection lines ST every other line, see ¶ 0062; The data driver 200 applies data signals to the odd-numbered data lines DT(1), DT(3) . . . (an example of the columns to be driven) every other horizontal scanning period to apply a scanning signal to the selection lines ST. The data driver 200 does not apply a data signal to the even-numbered data lines DT(2), DT(4), . . . . In the drawing, the data lines DT to which the data signal is applied are indicated as [ON], and the data lines DT to which the data signal is not applied are indicated as [OFF], see ¶ 0063; To display an image, the scanning signals and the data signals are applied as described above, whereby as illustrated in the drawing, only the upper left pixel px of each of the unit pixels UN is driven in the entire array of pixels px, see ¶ 0064).
As to Claim 2, Tsuchihashi depends on Claim 1, Tsuchihashi teaches wherein the data selection circuit and the gate selection circuit are configured to reduce the number of driven pixels to 1/N so as to simultaneously drive a pixel array having N pixel driving circuits among the pixel arrays having the plurality of pixel driving circuits (To display an image, the scanning signals and the data signals are applied as described above, whereby as illustrated in the drawing, only the upper left pixel px of each of the unit pixels UN is driven in the entire array of pixels px, see ¶ 0064; Figure 6 illustrates 4 total pixels per array with 1 pixel driven simultaneously by the scanning signal and data signal).
As to Claim 3, Tsuchihashi depends on Claim 1, Tsuchihashi teaches
wherein the gate selection circuit is configured to receive the gate information in a number less than the number of rows of the pixel array from the gate driver and process the gate information into a gate driving signal having the number of rows (in a period of one field, the vertical scanning driver 100 first applies a scanning signal to the selection line ST(1) in the corresponding horizontal scanning period, but does not apply a scanning signal to the selection line ST(2) in the next horizontal scanning period. Then, the vertical scanning driver 100 applies a scanning signal to the selection line ST(3) in the next horizontal scanning period, but does not apply a scanning signal to the selection line ST(4) in the next horizontal scanning period. In the drawing, the selection lines ST to which the scanning signal is applied are indicated as [ON], and the selection lines ST to which the scanning signal is not applied are indicated as [OFF], see ¶ 0061; Also for the subsequent lines, the vertical scanning driver 100 similarly applies a scanning signal during the horizontal scanning period corresponding to the odd-numbered selection line ST (an example of the driven line), and does not apply a scanning signal during the horizontal scanning period corresponding to the even-numbered selection line ST, thus scanning of the selection lines ST every other line, see ¶ 0062).
As to Claim 4, Tsuchihashi depends on Claim 1, Tsuchihashi teaches wherein the output of the data driver is less than that of the pixel array (The data driver 200 applies data signals to the odd-numbered data lines DT(1), DT(3) . . . (an example of the columns to be driven) every other horizontal scanning period to apply a scanning signal to the selection lines ST. The data driver 200 does not apply a data signal to the even-numbered data lines DT(2), DT(4), . . . . In the drawing, the data lines DT to which the data signal is applied are indicated as [ON], and the data lines DT to which the data signal is not applied are indicated as [OFF], see ¶ 0063).
As to Claim 5, Tsuchihashi teaches a display driving device for driving multiple resolutions by an EN signal of a pixel array having a plurality of gate lines and a plurality of data lines, and a plurality of pixel driving circuits respectively connected to the plurality of gate lines and the plurality of data lines (a pixel drive control device is configured to control driving of an array of pixels in M (M≥2) rows and N (N≥2) columns on a display device, see Abstract; in the display 14 of this drawing, M selection lines ST(1) to ST(M) extend in the horizontal (row) direction [plurality of gate lines], and N data lines DT(1) to DT(N) extend in the vertical (column) direction, see ¶ 0036; the electronic apparatus 1 displays either an image (UHD content) having a resolution (3840×2160) corresponding to the UHD standard or an image content (FHD content) having a resolution(1920×1080) corresponding to the FHD standard, see ¶ 0047; In the normal mode, the drawing describes “ON” in all the pixels px of eight rows X eight columns. The “ON” [EN signal] indicates that the corresponding pixel px is driven to display an image. That is, in the normal mode, all the pixels in the display 14 are driven to display an image, see ¶ 0050; As illustrated in this drawing, “ON” is described in the upper left (1st row and 1st column) pixel px for each pixel unit UN. Then, “OFF” [EN signal] is described in the remaining three pixels px of 1st row and 2nd column, 2nd row and 1st column, 2nd row and 2nd column. The “OFF” indicates that the corresponding pixel px is not driven to display an image…the low power consumption mode drives only one pixel px at a specific position for each pixel unit UN, and does not drive the remaining three pixel px, see ¶ 0057; the intra-unit pixel driving pattern configured so that the upper left and lower left two pixels px are driven in a single pixel unit UN having two rows by two columns, and the remaining upper right and lower right two pixels px are not driven, see ¶ 0097), the display driving device comprising:
a data driver configured to output pixel data to the plurality of data lines; a data selection circuit configured to process the outputted pixel data and transmitting the processed pixel data to the plurality of pixel driving circuits (data driver 200 applies data signals to the odd-numbered data lines DT(1), DT(3)…(an example of the columns to be driven) every other horizontal scanning period to apply a scanning signal to the selection lines ST. The data driver 200 does not apply a data signal to the even-numbered data lines DT(2), DT(4), …in the drawing, the data lines DT to which the data signal is applied are indicated as [ON], and the data lines DT to which the data signal is not applied are indicated as [OFF], see ¶ 0063);
an EN signal generating unit configured to generate an EN signal for controlling storage of the pixel data in the pixel driving circuits (In the normal mode, the drawing describes “ON” in all the pixels px of eight rows X eight columns. The “ON” [EN signal] indicates that the corresponding pixel px is driven to display an image. That is, in the normal mode, all the pixels in the display 14 are driven to display an image, see ¶ 0050; As illustrated in this drawing, “ON” is described in the upper left (1st row and 1st column) pixel px for each pixel unit UN. Then, “OFF” [EN signal] is described in the remaining three pixels px of 1st row and 2nd column, 2nd row and 1st column, 2nd row and 2nd column. The “OFF” indicates that the corresponding pixel px is not driven to display an image, see ¶ 0057);
a gate driver configured to output gate information to the plurality of gate lines; and a gate selection circuit configured to process the outputted gate information and control a time point at which the pixel data is stored in the plurality of pixel driving circuits based on the generated EN signals (in a period of one field, the vertical scanning driver 100 first applies a scanning signal to the selection line ST(1) in the corresponding horizontal scanning period, but does not apply a scanning signal to the selection line ST(2) in the next horizontal scanning period. Then, the vertical scanning driver 100 applies a scanning signal to the selection line ST(3) in the next horizontal scanning period, but does not apply a scanning signal to the selection line ST(4) in the next horizontal scanning period. In the drawing, the selection lines ST to which the scanning signal is applied are indicated as [ON], and the selection lines ST to which the scanning signal is not applied are indicated as [OFF], see ¶ 0061; Also for the subsequent lines, the vertical scanning driver 100 similarly applies a scanning signal during the horizontal scanning period corresponding to the odd-numbered selection line ST (an example of the driven line), and does not apply a scanning signal during the horizontal scanning period corresponding to the even-numbered selection line ST, thus scanning of the selection lines ST every other line, see ¶ 0062; the pixel drive controller 101 may set the driving pixel change condition so that after the display time has elapsed as described above, the display of an image on the display 14 starts from the state of no image being displayed [EN signal], see ¶ 0093),
wherein the data selection circuit and the gate selection circuit are configured to simultaneously and selectively store the processed pixel data in the plurality of pixel driving circuits based on control of the generated EN signals (in a period of one field, the vertical scanning driver 100 first applies a scanning signal to the selection line ST(1) in the corresponding horizontal scanning period, but does not apply a scanning signal to the selection line ST(2) in the next horizontal scanning period. Then, the vertical scanning driver 100 applies a scanning signal to the selection line ST(3) in the next horizontal scanning period, but does not apply a scanning signal to the selection line ST(4) in the next horizontal scanning period. In the drawing, the selection lines ST to which the scanning signal is applied are indicated as [ON], and the selection lines ST to which the scanning signal is not applied are indicated as [OFF], see ¶ 0061; Also for the subsequent lines, the vertical scanning driver 100 similarly applies a scanning signal during the horizontal scanning period corresponding to the odd-numbered selection line ST (an example of the driven line), and does not apply a scanning signal during the horizontal scanning period corresponding to the even-numbered selection line ST, thus scanning of the selection lines ST every other line, see ¶ 0062; The data driver 200 applies data signals to the odd-numbered data lines DT(1), DT(3) . . . (an example of the columns to be driven) every other horizontal scanning period to apply a scanning signal to the selection lines ST. The data driver 200 does not apply a data signal to the even-numbered data lines DT(2), DT(4), . . . . In the drawing, the data lines DT to which the data signal is applied are indicated as [ON], and the data lines DT to which the data signal is not applied are indicated as [OFF], see ¶ 0063; To display an image, the scanning signals and the data signals are applied as described above, whereby as illustrated in the drawing, only the upper left pixel px of each of the unit pixels UN is driven in the entire array of pixels px, see ¶ 0064).
As to Claim 6, Tsuchihashi depends on Claim 5, Tsuchihashi teaches
wherein the pixel driving circuit is configured to store the pixel data in the pixel driving circuit when the generated EN signal is 'ON', and not to store the pixel data in the pixel driving circuit when the generated EN signal is 'OFF' (In the normal mode, the drawing describes “ON” in all the pixels px of eight rows X eight columns. The “ON” [EN signal] indicates that the corresponding pixel px is driven to display an image. That is, in the normal mode, all the pixels in the display 14 are driven to display an image, see ¶ 0050; As illustrated in this drawing, “ON” is described in the upper left (1st row and 1st column) pixel px for each pixel unit UN. Then, “OFF” [EN signal] is described in the remaining three pixels px of 1st row and 2nd column, 2nd row and 1st column, 2nd row and 2nd column. The “OFF” indicates that the corresponding pixel px is not driven to display an image, see ¶ 0057).
As to Claim 7, Tsuchihashi depends on Claim 5, Tsuchihashi teaches wherein the EN signal generating unit is configured to divide an area of the pixel array to generate an EN signal of 'ON' in the driving pixel array and an EN signal of 'OFF' in the non-driving pixel array (In the normal mode, the drawing describes “ON” in all the pixels px of eight rows X eight columns. The “ON” [EN signal] indicates that the corresponding pixel px is driven to display an image. That is, in the normal mode, all the pixels in the display 14 are driven to display an image, see ¶ 0050; As illustrated in this drawing, “ON” is described in the upper left (1st row and 1st column) pixel px for each pixel unit UN. Then, “OFF” [EN signal] is described in the remaining three pixels px of 1st row and 2nd column, 2nd row and 1st column, 2nd row and 2nd column. The “OFF” indicates that the corresponding pixel px is not driven to display an image, see ¶ 0057).
As to Claim 8, Tsuchihashi depends on Claim 5, Tsuchihashi teaches
wherein the data selection circuit and the gate selection circuit are configured to reduce the number of driven pixels to 1/N so as to simultaneously drive a pixel array having N pixel driving circuits among the pixel arrays having the plurality of pixel driving circuits (To display an image, the scanning signals and the data signals are applied as described above, whereby as illustrated in the drawing, only the upper left pixel px of each of the unit pixels UN is driven in the entire array of pixels px, see ¶ 0064; Figure 6 illustrates 4 total pixels per array with 1 pixel driven simultaneously by the scanning signal and data signal).
As to Claim 9, Tsuchihashi depends on Claim 5, Tsuchihashi teaches wherein the output of the data driver is less than that of the pixel array (The data driver 200 applies data signals to the odd-numbered data lines DT(1), DT(3) . . . (an example of the columns to be driven) every other horizontal scanning period to apply a scanning signal to the selection lines ST. The data driver 200 does not apply a data signal to the even-numbered data lines DT(2), DT(4), . . . . In the drawing, the data lines DT to which the data signal is applied are indicated as [ON], and the data lines DT to which the data signal is not applied are indicated as [OFF], see ¶ 0063).
As to Claim 10, Tsuchihashi teaches a display driving device for driving multiple resolutions by an EN signal received from an external EN signal generating unit of a pixel array having a plurality of gate lines and a plurality of data lines, and a plurality of pixel driving circuits respectively connected to the plurality of gate lines and the plurality of data lines (a pixel drive control device is configured to control driving of an array of pixels in M (M≥2) rows and N (N≥2) columns on a display device, see Abstract; in the display 14 of this drawing, M selection lines ST(1) to ST(M) extend in the horizontal (row) direction [plurality of gate lines], and N data lines DT(1) to DT(N) extend in the vertical (column) direction, see ¶ 0036; the electronic apparatus 1 displays either an image (UHD content) having a resolution (3840×2160) corresponding to the UHD standard or an image content (FHD content) having a resolution(1920×1080) corresponding to the FHD standard, see ¶ 0047; In the normal mode, the drawing describes “ON” in all the pixels px of eight rows X eight columns. The “ON” [EN signal] indicates that the corresponding pixel px is driven to display an image. That is, in the normal mode, all the pixels in the display 14 are driven to display an image, see ¶ 0050; As illustrated in this drawing, “ON” is described in the upper left (1st row and 1st column) pixel px for each pixel unit UN. Then, “OFF” [EN signal] is described in the remaining three pixels px of 1st row and 2nd column, 2nd row and 1st column, 2nd row and 2nd column. The “OFF” indicates that the corresponding pixel px is not driven to display an image…the low power consumption mode drives only one pixel px at a specific position for each pixel unit UN, and does not drive the remaining three pixel px, see ¶ 0057; the intra-unit pixel driving pattern configured so that the upper left and lower left two pixels px are driven in a single pixel unit UN having two rows by two columns, and the remaining upper right and lower right two pixels px are not driven, see ¶ 0097), the display driving device comprising:
a data driver configured to output pixel data to the plurality of data lines; a data selection circuit configured to process the outputted pixel data and transmit the processed pixel data to the plurality of pixel driving circuits (data driver 200 applies data signals to the odd-numbered data lines DT(1), DT(3)…(an example of the columns to be driven) every other horizontal scanning period to apply a scanning signal to the selection lines ST. The data driver 200 does not apply a data signal to the even-numbered data lines DT(2), DT(4), …in the drawing, the data lines DT to which the data signal is applied are indicated as [ON], and the data lines DT to which the data signal is not applied are indicated as [OFF], see ¶ 0063);
an EN signal receiving unit configured to receive an EN signal from an external terminal, the EN signal controlling the storage of the pixel data of the pixel driving circuit (In the normal mode, the drawing describes “ON” in all the pixels px of eight rows X eight columns. The “ON” [EN signal] indicates that the corresponding pixel px is driven to display an image. That is, in the normal mode, all the pixels in the display 14 are driven to display an image, see ¶ 0050; As illustrated in this drawing, “ON” is described in the upper left (1st row and 1st column) pixel px for each pixel unit UN. Then, “OFF” [EN signal] is described in the remaining three pixels px of 1st row and 2nd column, 2nd row and 1st column, 2nd row and 2nd column. The “OFF” indicates that the corresponding pixel px is not driven to display an image, see ¶ 0057);
a gate driver configured to output gate information to the plurality of gate lines; and a gate selection circuit configured to process the outputted gate information and control a point in time at which the pixel data is stored in the plurality of pixel driving circuits based on the received EN signals (In the normal mode, the drawing describes “ON” in all the pixels px of eight rows X eight columns. The “ON” [EN signal] indicates that the corresponding pixel px is driven to display an image. That is, in the normal mode, all the pixels in the display 14 are driven to display an image, see ¶ 0050; As illustrated in this drawing, “ON” is described in the upper left (1st row and 1st column) pixel px for each pixel unit UN. Then, “OFF” is described in the remaining three pixels px of 1st row and 2nd column, 2nd row and 1st column, 2nd row and 2nd column. The “OFF” [EN signal] indicates that the corresponding pixel px is not driven to display an image, see ¶ 0057; in a period of one field, the vertical scanning driver 100 first applies a scanning signal to the selection line ST(1) in the corresponding horizontal scanning period, but does not apply a scanning signal to the selection line ST(2) in the next horizontal scanning period. Then, the vertical scanning driver 100 applies a scanning signal to the selection line ST(3) in the next horizontal scanning period, but does not apply a scanning signal to the selection line ST(4) in the next horizontal scanning period. In the drawing, the selection lines ST to which the scanning signal is applied are indicated as [ON], and the selection lines ST to which the scanning signal is not applied are indicated as [OFF], see ¶ 0061; Also for the subsequent lines, the vertical scanning driver 100 similarly applies a scanning signal during the horizontal scanning period corresponding to the odd-numbered selection line ST (an example of the driven line), and does not apply a scanning signal during the horizontal scanning period corresponding to the even-numbered selection line ST, thus scanning of the selection lines ST every other line, see ¶ 0062),
wherein the data selection circuit and the gate selection circuit are configured to simultaneously and selectively store the processed pixel data in the plurality of pixel driving circuits based on control of the received EN signals (In the normal mode, the drawing describes “ON” in all the pixels px of eight rows X eight columns. The “ON” [EN signal] indicates that the corresponding pixel px is driven to display an image. That is, in the normal mode, all the pixels in the display 14 are driven to display an image, see ¶ 0050; As illustrated in this drawing, “ON” is described in the upper left (1st row and 1st column) pixel px for each pixel unit UN. Then, “OFF” is described in the remaining three pixels px of 1st row and 2nd column, 2nd row and 1st column, 2nd row and 2nd column. The “OFF” [EN signal] indicates that the corresponding pixel px is not driven to display an image, see ¶ 0057; in a period of one field, the vertical scanning driver 100 first applies a scanning signal to the selection line ST(1) in the corresponding horizontal scanning period, but does not apply a scanning signal to the selection line ST(2) in the next horizontal scanning period. Then, the vertical scanning driver 100 applies a scanning signal to the selection line ST(3) in the next horizontal scanning period, but does not apply a scanning signal to the selection line ST(4) in the next horizontal scanning period. In the drawing, the selection lines ST to which the scanning signal is applied are indicated as [ON], and the selection lines ST to which the scanning signal is not applied are indicated as [OFF], see ¶ 0061; Also for the subsequent lines, the vertical scanning driver 100 similarly applies a scanning signal during the horizontal scanning period corresponding to the odd-numbered selection line ST (an example of the driven line), and does not apply a scanning signal during the horizontal scanning period corresponding to the even-numbered selection line ST, thus scanning of the selection lines ST every other line, see ¶ 0062; The data driver 200 applies data signals to the odd-numbered data lines DT(1), DT(3) . . . (an example of the columns to be driven) every other horizontal scanning period to apply a scanning signal to the selection lines ST. The data driver 200 does not apply a data signal to the even-numbered data lines DT(2), DT(4), . . . . In the drawing, the data lines DT to which the data signal is applied are indicated as [ON], and the data lines DT to which the data signal is not applied are indicated as [OFF], see ¶ 0063).
As to Claim 11, Tsuchihashi depends on Claim 10, Tsuchihashi teaches wherein the pixel driving circuit is configured to store the pixel data in the pixel driving circuit when the received EN signal is 'ON', and not to store the pixel data in the pixel driving circuit when the received EN signal is 'OFF' (In the normal mode, the drawing describes “ON” in all the pixels px of eight rows X eight columns. The “ON” [EN signal] indicates that the corresponding pixel px is driven to display an image. That is, in the normal mode, all the pixels in the display 14 are driven to display an image, see ¶ 0050; As illustrated in this drawing, “ON” is described in the upper left (1st row and 1st column) pixel px for each pixel unit UN. Then, “OFF” is described in the remaining three pixels px of 1st row and 2nd column, 2nd row and 1st column, 2nd row and 2nd column. The “OFF” [EN signal] indicates that the corresponding pixel px is not driven to display an image, see ¶ 0057).
As to Claim 12, Tsuchihashi depends on Claim 10, Tsuchihashi teaches an EN signal control unit, wherein the EN signal control unit is configured to divide an area of the pixel array, classify the divided area as a driving pixel array when the EN signal receiving unit receives an EN signal of 'ON', and classify the divided area as a non-driving pixel array when the EN signal receiving unit receives an EN signal of 'OFF' (In the normal mode, the drawing describes “ON” in all the pixels px of eight rows X eight columns. The “ON” [EN signal] indicates that the corresponding pixel px is driven to display an image. That is, in the normal mode, all the pixels in the display 14 are driven to display an image, see ¶ 0050; As illustrated in this drawing, “ON” is described in the upper left (1st row and 1st column) pixel px for each pixel unit UN. Then, “OFF” is described in the remaining three pixels px of 1st row and 2nd column, 2nd row and 1st column, 2nd row and 2nd column. The “OFF” [EN signal] indicates that the corresponding pixel px is not driven to display an image, see ¶ 0057).
As to Claim 13, Tsuchihashi depends on Claim 10, Tsuchihashi teaches
wherein the data selection circuit and the gate selection circuit are configured to reduce the number of driven pixels to 1/N so as to simultaneously drive a pixel array having N pixel driving circuits among the pixel arrays having the plurality of pixel driving circuits (To display an image, the scanning signals and the data signals are applied as described above, whereby as illustrated in the drawing, only the upper left pixel px of each of the unit pixels UN is driven in the entire array of pixels px, see ¶ 0064; Figure 6 illustrates 4 total pixels per array with 1 pixel driven simultaneously by the scanning signal and data signal).
As to Claim 14, Tsuchihashi depends on Claim 11, Tsuchihashi teaches wherein the output of the data driver is less than that of the pixel array (The data driver 200 applies data signals to the odd-numbered data lines DT(1), DT(3) . . . (an example of the columns to be driven) every other horizontal scanning period to apply a scanning signal to the selection lines ST. The data driver 200 does not apply a data signal to the even-numbered data lines DT(2), DT(4), . . . . In the drawing, the data lines DT to which the data signal is applied are indicated as [ON], and the data lines DT to which the data signal is not applied are indicated as [OFF], see ¶ 0063).
Conclusion
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/EBONI N GILES/Examiner, Art Unit 2622
/PATRICK N EDOUARD/Supervisory Patent Examiner, Art Unit 2622
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