DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
2. Claim(s) 14 and 21 is/are rejected on the ground of nonstatutory double patenting as being unpatentable over Claim(s) 12 and 16 of U.S. Patent No. 19/341947. Although the claims at issue are not identical, they are not patentably distinct from each other because the instant application’s claims are essentially broader than the patent’s recited claims.
Instant Application 19/341949
Co-pending Application 19/341947
14. A method for controlling an electronic display comprising:
receiving a control signal from a comparator of a content-addressable control cell into a column driver circuit of the content-addressable control cell;
propagating the control signal or an inverse of the control signal to a pixel active array of the electronic display using the column driver circuit; and
switching a display pixel to turn off in response to the control signal.
12. A method for controlling an electronic display comprising:
reading pixel data corresponding to pixel data of a display pixel in a pixel active area of the electronic display from a memory located outside of the pixel active area into a comparator located outside of the pixel active area;
comparing the pixel data to a counter value corresponding to a gray level using the comparator, wherein:
when the counter value does not correspond to the pixel data, the comparator outputs a control signal in a first state to a column driver located outside of the pixel active area; and
when the counter value corresponds to the pixel data, the comparator outputs the control signal in a second state different from the first state to the column driver located outside of the pixel active area; propagating the control signal to the pixel active area using the column driver; and
switching the display pixel to turn off in response to the control signal being in the second state.
21. An electronic device comprising:
data processing circuitry configured to generate pixel data for a plurality of display pixels; and
an electronic display comprising:
a pixel active array comprising the plurality of display pixels; and
a plurality of control cells each corresponding to one respective display pixel of the pixel active array, wherein each control cell comprises:
a column driver configured to propagate a control signal based on the pixel data corresponding to the one respective display pixel to the pixel active array.
16. An electronic device comprising:
data processing circuitry configured to generate pixel data for a plurality of display pixels; and
an electronic display comprising:
a pixel active array comprising the plurality of display pixels; and
a plurality of control cells each corresponding to one respective display pixel of the pixel active array, wherein each control cell comprises:
pixel data memory configured to store pixel data for the respective display pixel corresponding to its respective display pixel;
a comparator configured to generate a control signal based on a comparison between the pixel data and a counter corresponding to a gray level; and
a column driver configured to propagate the control signal to the pixel active array.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
3. Claim(s) 1, 14-15, and 21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cok et al. (US Patent/PGPub. No. 20170330509).
Regarding Claim 1,
Cok et al. teach
an electronic display ([0072], FIG. 1-2, i.e. distributed pulse-width modulation system 10 can be a display system) comprising:
pixel active array ([0072], FIG. 1-2, i.e. full-color pixel 70 (an array of 70s shown in FIG. 1)); and
a plurality of content-addressable ([0099], FIG. 11, i.e. content addressable memory (CAM) as the digital memory 28) control cells ([0069], FIG. 9, i.e. pulse-width modulation elements 20 … and a drive circuit 26) configured to control display pixels ([0072], FIG. 1-2, i.e. light emitters 50 … a pixel includes a single output device 27) of the pixel active array (i.e. please see above citation(s)) using control signals ([0099], FIG. 11, i.e. the output state flip-flop 92 is toggled from an off state to an on state) propagated to the pixel active array on column lines (FIG. 1 & 10-13, i.e. as shown by the figure(s) column lines in FIGs. 1 and 13, and as Vdd in FIGs. 10-12) by column driver circuits ([0099], FIG. 11, i.e. drive circuit 26) of the content-addressable control cells (i.e. please see above citation(s)).
Regarding Claim 14,
Cok et al. teach
a method for controlling ([0024], FIG. 11, i.e. method of controlling a distributed pulse-width modulation system) an electronic display ([0072], FIG. 1-2, i.e. distributed pulse-width modulation system 10 can be a display system) comprising:
receiving a control signal ([0096], FIG. 11, i.e. output of the comparator circuit 90 … to drive the output device 27) from a comparator ([0096], FIG. 11, i.e. comparator circuit 90) of a content-addressable ([0099], FIG. 11, i.e. content addressable memory (CAM) as the digital memory 28) control cell ([0069], FIG. 9, i.e. pulse-width modulation elements 20 … and a drive circuit 26) into a column driver circuit ([0099], FIG. 11, i.e. drive circuit 26) of the content-addressable control cell (i.e. please see above citation(s));
propagating the control signal ([0087], FIG. 8, i.e. the next set of multi-bit digital values and corresponding clock rates are calculated or provided in step 155) or an inverse of the control signal to a pixel active array ([0072], FIG. 1-2, i.e. full-color pixel 70 (an array of 70s shown in FIG. 1)) of the electronic display using the column driver circuit (i.e. please see above citation(s)); and
switching a display pixel to turn off ([0096], FIG. 11, i.e. “from an off state to an on state” (please see below for detail)) in response to the control signal (i.e. please see above citation(s)).
Regarding Claim 15,
Cok et al. teach
the method of claim 14, wherein the control signal or the inverse of the control signal is propagated to the pixel active array (i.e. please see above citation(s)) by way downstream column driver circuits ([0087], FIG. 8, i.e. the next set of multi-bit digital values and corresponding clock rates are calculated or provided in step 155).
Regarding Claim 21,
Cok et al. teach
an electronic device ([0072], FIG. 1-2, i.e. distributed pulse-width modulation system 10 can be a display system) comprising:
data processing circuitry ([0069], FIG. 1, i.e. system controller 40) configured to generate pixel data ([0099], FIG. 11, i.e. data signals) for a plurality of display pixels ([0072], FIG. 1-2, i.e. light emitters 50 … a pixel includes a single output device 27); and
an electronic display ([0072], FIG. 1-2, i.e. distributed pulse-width modulation system 10 can be a display system) comprising:
a pixel active array ([0072], FIG. 1-2, i.e. full-color pixel 70 (an array of 70s shown in FIG. 1)) comprising the plurality of display pixels; and
a plurality of control cells ([0069], FIG. 9, i.e. pulse-width modulation elements 20 … and a drive circuit 26) each corresponding to one respective display pixel ([0069], FIG. 11, i.e. output device 27) of the pixel active array, wherein each control cell comprises:
a column driver ([0099], FIG. 11, i.e. drive circuit 26) configured to propagate a control signal ([0096], FIG. 11, i.e. output of the comparator circuit 90 … to drive the output device 27) based on the pixel data corresponding to the one respective display pixel to the pixel active array ([0099], FIG. 11, i.e. PWM counter 22; [0080], FIG. 11, i.e. full-bit pixel value).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claim(s) 2 and 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cok et al. (US Patent/PGPub. No. 20170330509) in view of Wang et al. (US Patent/PGPub. No. 20210304682).
Regarding Claim 2,
Cok et al. teach
the electronic display of claim 1.
However, Cok et al. do not explicitly teach
wherein the column driver circuits comprise:
a dynamic column driver;
a static column driver;
an analog complementary metal-oxide-semiconductor multiplexer (CMOS- mux) column driver; or
a digital multiplexer-based column driver.
In the same field of endeavor, Wang et al. teach
wherein the column driver circuits ([0077], FIG. 6-7, i.e. column driver 62) comprise:
a dynamic column driver;
a static column driver;
an analog complementary metal-oxide-semiconductor multiplexer (CMOS- mux) column driver; or
a digital multiplexer-based column driver ([0077], FIG. 6-7, i.e. multiplexing circuit 96 that receives image data 98 of size N bits from the column driver 62).
It would have been obvious to a person having ordinary skill in the art at the time the invention’s effective date was filed to combine Cok et al. teaching of display comprising content-addressable memory driving display pixels with Wang et al. teaching of display comprising column driver having digital multiplexer to effectively transmit image data to respective pixels utilizing column driver having digital multiplexer (Wang et al.’s [0077]).
Regarding Claim 22,
Cok et al. teach
the electronic device of claim 21.
However, Cok et al. do not explicitly teach
wherein the column driver of each control cell comprises a digital multiplexer configured to select between the control signal of its control cell or another control signal corresponding to a different control cell.
In the same field of endeavor, Wang et al. teach
wherein the column driver of each control cell ([0070], FIG. 6-7, i.e. columns of pixels 72) comprises a digital multiplexer ([0077], FIG. 6-7, i.e. multiplexing circuit 96 that receives image data 98 of size N bits) configured to select between the control signal of its control cell ([0077], FIG. 6-7, i.e. multiplexing control signal (MUX control signal) 100) or another control signal corresponding to a different control cell.
It would have been obvious to a person having ordinary skill in the art at the time the invention’s effective date was filed to combine Cok et al. teaching of display comprising content-addressable memory driving display pixels with Wang et al. teaching of display comprising column driver having digital multiplexer to effectively transmit image data to respective pixels utilizing column driver having digital multiplexer (Wang et al.’s [0077]).
5. Claim(s) 11-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cok et al. (US Patent/PGPub. No. 20170330509) in view of LIM et al. (US Patent/PGPub. No. 20220137743).
Regarding Claim 11,
Cok et al. teach
the electronic display of claim 1.
However, Cok et al. do not explicitly teach
wherein the pixel active array comprises rows and columns of display pixels, wherein the number of column lines used by the driver circuits exceeds the number of columns of display pixels of the pixel active array.
In the same field of endeavor, LIM et al. teach
wherein the pixel active array ([0203], FIG. 12, i.e. PX11 to PX14, PX21 to PX24, and PX31 to PX34) comprises rows ([0203], FIG. 12, i.e. SL1 to SL6) and columns ([0203], FIG. 12, i.e. DL1 to DL4) of display pixels, wherein the number of column lines ([0206], FIG. 12, i.e. pixel data signal PD1… CD4 (that is, four pixel data signals PD1-PD4 and four compensation signals CD1-CD4, total of 8 lines)) used by the driver circuits ([0204], FIG. 12, i.e. data driving circuit 100C3-1) exceeds the number of columns of display pixels ([0206], FIG. 12, i.e. data line DL1… DL4 (that is, total of 4 lines)) of the pixel active array (i.e. please see above citation(s)).
It would have been obvious to a person having ordinary skill in the art at the time the invention’s effective date was filed to combine Cok et al. teaching of display comprising content-addressable memory driving display pixels with LIM et al. teaching of display comprising column driver having multiplexers to effectively transmit image data and/or compensating data to respective pixels utilizing column driver having multiplexers selecting according data lines (LIM et al.’s [0011]).
Regarding Claim 12,
the electronic display of claim 11, wherein
LIM et al. teach
the number of column lines ([0206], FIG. 12, i.e. pixel data signal PD1… CD4 (that is, four pixel data signals PD1-PD4 and four compensation signals CD1-CD4, total of 8 lines)) used by the driver circuits is at least double ([0206], FIG. 12, i.e. (that is, 8 = 4x2 )) the number of columns of display pixels ([0206], FIG. 12, i.e. data line DL1… DL4 (that is, total of 4 lines)) of the pixel active array (i.e. please see above citation(s)).
Allowable Subject Matter
6. Claim(s) 3-10, 13, 16-20, and 23 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
7. The following is an examiner’s statement of reasons for allowance:
Cok et al. (US Patent/PGPub. No. 20170330509) teach a distributed pulse-width modulation system includes an array of pulse-width modulation elements, each element including a digital memory for storing a plurality of multi-bit digital values, a drive circuit for each stored multi-bit digital value, and an output device for each stored multi-bit digital value. The multi-bit digital values all have the same number of bits. For each stored multi-bit digital value, the corresponding drive circuit drives the corresponding output device in response to the multi-bit digital value stored in the digital memory. A system controller includes a memory for storing the multi-bit digital values for each pulse-width modulation element and a communication circuit communicates each multi-bit digital value to each corresponding pulse-width modulation element.
Wang et al. (US Patent/PGPub. No. 20210304682) teach a display system may include a memory external to a pixel that stores a first digital data value, a memory internal to the pixel that stores a second digital data signal, where a combination of the first digital data signal and the second digital data signal may indicate a target gray level assigned to the pixel for a particular image frame. The pixel may be driven for a first duration of time according to the first digital data signal and for a second duration of time according to the second digital data signal.
The subject matter of the claim(s) that could neither be found/suggested nor obviously combinable in the prior arts of record. The subject matter was a device/method including
“…wherein the analog CMOS-mux column driver comprises:
an analog CMOS-mux circuit configured to select, based on a row enable signal, either a first input comprising an upstream control signal output from a serially connected upstream analog CMOS-mux column driver and a second input comprising a second control signal output from its respective content-addressable control cell, to output as an output control signal; and
a digital buffer configured to propagate the output control signal of the analog CMOS-mux column driver to a serially connected downstream analog CMOS-mux column driver.” (Claim 3),
“…wherein the analog CMOS-mux column driver comprises:
an analog CMOS-mux circuit configured to select, based on a row enable signal, either a first input comprising an inverse upstream output control signal output from a serially connected upstream analog CMOS-mux column driver and a second input comprising a second control signal output from its respective content-addressable control cell, to output as an output control signal; and
a digital inverter configured to propagate an inverse of the output control signal of the analog CMOS-mux column driver to a serially connected downstream analog CMOS-mux column driver.” (Claim 4),
“…wherein the analog CMOS-mux column driver comprises an analog CMOS-mux circuit comprising four transistors.” (Claim 6),
“…wherein the number of column lines used by the driver circuits is at least six times the number of columns of display pixels of the pixel active array.” (Claim 13),
“…wherein the column driver circuit and the downstream column driver circuits comprise:
a static column driver circuit; or
an analog complementary metal-oxide-semiconductor multiplexer (CMOS- mux) column driver circuit.” (Claim 16),
“…wherein the control signal or the inverse of the control signal is propagated to the pixel active array using the column driver circuit, wherein the column driver circuit comprises a dynamic column driver.” (Claim 17),
“…wherein the column driver of each control cell comprises one or more digital logic gates configured to propagate the control signal of its control cell or another control signal corresponding to an upstream control cell.” (Claim 23),
in combination with the other elements (or steps) of the device or apparatus and method recited in the claims.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VINH TANG LAM whose telephone number is (571) 270-3704. The examiner can normally be reached Monday to Friday 8:00 AM to 5:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Nitin K Patel can be reached at (571) 272-7677. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/VINH T LAM/Primary Examiner, Art Unit 2628
Prosecution Insights