Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. Claims 1-20 are pending.
Claim Objections
3. Claim 17 is objected to because of the following informalities: the claim states “the” multiple flip-flops which is originally claimed in claim 16. However, claim 17 is dependent upon claim 15. Appropriate correction is required.
Claim Rejections - 35 USC § 102
4. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Guy et al. (US Patent 8,289,233), herein after referred to as Guy.
Regarding independent claim 1, Guy discloses an electronic display (Figure F 3 described in column C 6 lines L 19-20 to regard a display.) comprising:
a pixel active (C1 L35-37) array (F3 38) configured to display an image (C9 L52-65) frame over a series of subframes (F1-F2 C5 L1 to C6 L18 and F9B C9 L65 to C10 L6 describes subfields/subframes of a frame/field to display an image in accordance with grayscale levels of the pixel being active for a sustained subfield. Further, F9a depicts the dither table with a repeated 4 frame cycle describing frames 1-4 as subframes of the frame repeat cycle. F9b, for example, may be interpreted as subframe 0-3.); and
content-addressable control circuitry (F3 31-37 (including X and Y electrodes)) configured to control (C6 L19-23) the pixel active array (38), wherein the content-addressable control circuitry (31-37) comprises circuitry (F4) configured to perform subframe dithering (5) to generate control signals (signals from dither 5 to frame buffer 6) to control the display pixels of the pixel active array (38) to correspond to different gray levels for different subframes of the series of subframes of the image frame to be displayed on the pixel active array (F4 6 C9 L26-29 dither unit 5 outputs coefficients added to LSB and carry to frame buffer 6 for display (image) on screen. F9b-9e depicts changes to the turn on order for each pixel of each frame).
Regarding claim 2, Guy discloses the electronic display of claim 1, wherein the content-addressable control circuitry comprises circuitry configured to perform 1-bit subframe dithering (C9 L26-29 describes adding a dither bit (1) to the LSB).
Regarding claim 4, Guy discloses the electronic display of claim 1, wherein the circuitry configured to perform subframe dithering comprises column-level subframe dithering circuitry (F4 and F9f dither 5 operates in accordance with frame, row, and column C10 L7-18).
Claim Rejections - 35 USC § 103
5. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Guy in view of Ochi (US Patent Application Publication 2008/0018559).
Regarding claim 3, Guy discloses the electronic display of claim 1, wherein the content-addressable control circuitry comprises circuitry configured to perform 1-bit subframe dithering (C9 L26-29 describes adding a dither bit (1) to the LSB).
Guy does not specifically disclose 2-bit subframe dithering.
Ochi discloses 2-bit subframe dithering (paragraph [0027] describes 2bit dither signal sd (figure 4) may be set in accordance with need as added to LSB of the input signal ([0036])).
It would have been obvious to one skilled in the art before the effective filing date of the current application to enable Guy’s 1-bit dither signal with the known technique of a 2-bit dither signal yielding the predictable results of modifying the dither signal according to need as disclosed by Ochi ([0027]).
6. Claim(s) 7-13, 15, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Guy in view of Morimatsu (US Patent Application Publication 2003/0058482).
Regarding claim 7, Guy discloses the electronic display of claim 1.
Guy does not specifically disclose wherein the circuitry configured to perform subframe dithering comprises pixel-level subframe dithering circuitry disposed in each core cell of the content-addressable control circuitry.
Morimatsu discloses wherein the circuitry configured to perform subframe dithering (F1 104) comprises pixel-level subframe dithering circuitry disposed in each core cell (support for the subject matter is found in [0009] of the originally filed specification regards the ore cell of the CAMiD memory comprising the pixel data) of the content-addressable control circuitry ([0033] describes figure 1 to regard pixel data acquisition means from image memory (core cell) utilized by dithering means 104 on the basis of an address of the image data (corresponding to Guy F4 dithering means utilizing frame row and column addressing).).
It would have been obvious to one skilled in the art before the effective filing date of the current application to enable Guy’s circuitry configured to perform subframe dithering with the known technique of comprising pixel-level subframe dithering circuitry disposed in each core cell of the content-addressable control circuitry yielding the predictable results of preventing generation of an array of iteratively arranged dots as disclosed by Morimatsu ([0008]).
Regarding claim 8, Guy and Morimatsu discloses the electronic display of claim 7, wherein each core cell of the content-addressable control circuitry comprises a comparator (Morimatsu: F1 102) that comprises the pixel-level subframe dithering circuitry.
Regarding claim 9, Guy and Morimatsu discloses the electronic display of claim 8, wherein each comparator (Morimatsu: F1 102) is configured to compare pixel data (Morimatsu: F1 100+101) of the image frame for one display pixel (Morimatsu: [0033] comparator 102 compares pixels data of each addressed pixel against the dithering means) against multiple counters, in parallel, that have different offsets from one another (Guy: F4 dither circuity uses frame, row, and column counters for addressing which comprise different offsets).
Regarding claim 10, Guy and Morimatsu discloses the electronic display of claim 9, wherein each comparator (Morimatsu: F1 102) is configured to vary its operation based on a subframe index indicating a present subframe of the series of subframes (Guy: F4 dither circuity uses frame, row, and column counters for addressing which comprise different offsets.).
Regarding independent claim 11, Guy discloses content-addressable circuit configured to selectively control a pixel active (C1 L35-37) array (F3 38) based on operations comprising:
in a first subframe (F9b frame 0 of the odd values) of a frame (F1-F2 C5 L1 to C6 L18 and F9B C9 L65 to C10 L6 describes subfields/subframes of a frame/field to display an image in accordance with grayscale levels of the pixel being active for a sustained subfield. Further, F9a depicts the dither table with a repeated 4 frame cycle describing frames 1-4 as odd and even subframes of the frame repeat cycle. F9b, for example, may be interpreted as subframe 0-3.), issuing a first control signal to a pixel of the pixel active array to turn off (F9b pixel in row 1 column 1 depicted as the first turn on and the pixel in the second row first column as the last to turn on, C9 L56-65. Describing control signals to turn a pixel on includes the inherent signal of not applying the turn on signal interpreted as a turn off signal.) following a first pulse corresponding to a first gray level (C9 L56-65 describes 1 indicates a change in luminance to the next largest level, depicted in F2 regarding grayscale.); and
in a second subframe (F9b frame 2 of the odd values) of the frame (frames 0-frames 3), issuing a second control signal to the pixel of the pixel active array to turn off following a second pulse corresponding to a second gray level (the same first pixel in row 1 column 1 now comprises a value of 6 a different gray level between the minimum increase of 1 and maximum value of 16).
Guy does not specifically disclose content-addressable memory.
Morimatsu discloses content-addressable memory (F1 100+101 [0033] describes address image data from image memory 100 utilized for dithering means 104).
It would have been obvious to one skilled in the art before the effective filing date of the current application to enable Guy’s content-addressable circuit with the known technique of content-addressable memory yielding the predictable results of acquiring image data of each pixel on a pixel-by-pixel basis as disclosed by Morimatsu ([0033]).
Regarding claim 12, Guy and Morimatsu discloses the content-addressable memory of claim 11, wherein:
issuing the first control signal comprises, in the first subframe of the frame (Guy: F9b frame 0), performing multiple sequential (Morimatsu: [0033] for each pixel on a pixel-by-pixel basis (multiple sequential)) comparisons (Morimatsu: F1 comparator 102) of pixel image data (Guy: F4 1 Morimatsu: F1 101) corresponding to the pixel to a counter with multiple immediately subsequent counter values (Guy: F4 dither circuity uses frame, row, and column counters for addressing which comprise different offsets) using a single comparator (Morimatsu: F1 comparator 102); and
issuing the second control signal comprises, in the second subframe of the frame (Guy: F9b frame 2), performing multiple sequential (Morimatsu: [0033] for each pixel on a pixel-by-pixel basis (multiple sequential)) comparisons (Morimatsu: F1 comparator 102) of the pixel image data (Guy: F4 1 Morimatsu: F1 101) corresponding to the pixel to the counter at the multiple immediately subsequent counter values (Guy: F4 dither circuity uses frame, row, and column counters for addressing which comprise different offsets (next row, next column, next frame); Morimatsu: [0033] pixel-by-pixel) using the single comparator (Morimatsu: F1 comparator 102), wherein the counter is configured to initially repeat a zero count (Guy: F9b value 1 set in the pixel of row 3 column 1) for a first set of comparisons (Morimatsu: F1 comparator 102).
Regarding claim 13, Guy and Morimatsu discloses the content-addressable memory of claim 11, wherein:
issuing the first control signal comprises, in the first subframe of the frame (Guy: F9b frame 0), performing multiple (Morimatsu: [0033] for each pixel on a pixel-by-pixel basis (multiple sequential)) comparisons (Morimatsu: F1 comparator 102) of pixel image data (Guy: F4 1 Morimatsu: F1 101) corresponding to the pixel to a counter at multiple immediately subsequent counter values (Guy: F4 dither circuity uses frame, row, and column counters for addressing which comprise different offsets) using a single comparator (Morimatsu: F1 comparator 102) [ ]; and
issuing the second control signal comprises, in the second subframe of the frame (Guy: F9b frame 2), performing multiple (Morimatsu: [0033] for each pixel on a pixel-by-pixel basis (multiple sequential)) comparisons (Morimatsu: F1 comparator 102) of the pixel image data (Guy: F4 1 Morimatsu: F1 101) corresponding to the pixel to the single counter at multiple immediately subsequent counter values (Guy: F4 dither circuity uses frame, row, and column counters for addressing which comprise different offsets (next row, next column, next frame); Morimatsu: [0033] pixel-by-pixel) using the single comparator (Morimatsu: F1 comparator 102) [ ], wherein one of the counters are configured to initially repeat a zero count (Guy: F9b value 1 set in the pixel of row 3 column 1).
Morimatsu does not specifically disclose multiple comparators in parallel.
It would have been obvious to one skilled in the art before the effective filing date of the current application to enable Morimatsu’s single comparator for serialized processing of data with the known technique of a plurality of parallel comparators yielding the expected results of parallel processing in accordance with design preference comprising the known differences in serial and parallel processing as well known in the art.
Regarding independent claim 15, Guy discloses an electronic display (Figure F 3 described in column C 6 lines L 19-20 to regard a display.) comprising:
a pixel active (C1 L35-37) array (F3 38); and
content-addressable circuitry (F3 31-37 (including X and Y electrodes)) configured to perform subframe dithering (5) on the pixel active array (38) (C9 L26-51).
Guy does not specifically disclose content-addressable memory.
Morimatsu discloses content-addressable memory (F1 100+101 [0033] describes address image data from image memory 100 utilized for dithering means 104).
It would have been obvious to one skilled in the art before the effective filing date of the current application to enable Guy’s content-addressable circuit with the known technique of content-addressable memory yielding the predictable results of acquiring image data of each pixel on a pixel-by-pixel basis as disclosed by Morimatsu ([0033]).
Regarding claim 18, Guy and Morimatsu discloses the electronic display of claim 15, wherein the content-addressable memory comprises pixel-level dithering circuitry configured to perform 1-bit dithering (Guy: C9 L26-29 describes adding a dither bit (1) to the LSB).
7. Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Guy-Morimatsu in view of Sewell et al. (US Patent 4,898,469), herein after referred to as Sewell.
Regarding claim 16, Guy and Morimatsu discloses the electronic display of claim 15, wherein the content-addressable memory comprises column-level dithering circuitry (Guy: F4 and F9f dither 5 operates in accordance with frame, row, and column C10 L7-18) [ ] store a result of multiple consecutive content-addressable memory (Guy: F4 frame buffer 6 stores dither 5 results) comparisons (Morimatsu: F1 comparator 102).
Neither Guy or Morimatsu disclose comprising multiple flip-flops to store a result.
Sewell discloses multiple flip-flops to store a result (F3 321-324 C5 L54 to C6 L7 describes the flip flops 321-324 to receive the LSB and LSB+1).
It would have been obvious to one skilled in the art before the effective filing date of the current application to enable Guy-Morimatsu’s content-addressable memory with the known technique of multiple flip-flops to store a result yielding the predictable results of acting as a buffer as disclosed by Sewell (C5 L54 to C6 L7).
8. Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Guy-Morimatsu in view of Ochi.
Regarding claim 19, Guy discloses the electronic display of claim 15, wherein the content-addressable control memory comprises pixel-level dithering circuitry configured to perform 1-bit subframe dithering (C9 L26-29 describes adding a dither bit (1) to the LSB).
Guy does not specifically disclose 2-bit subframe dithering.
Ochi discloses 2-bit subframe dithering (paragraph [0027] describes 2bit dither signal sd (figure 4) may be set in accordance with need as added to LSB of the input signal ([0036])).
It would have been obvious to one skilled in the art before the effective filing date of the current application to enable Guy’s 1-bit dither signal with the known technique of a 2-bit dither signal yielding the predictable results of modifying the dither signal according to need as disclosed by Ochi ([0027]).
9. Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Guy-Morimatsu in view of Hwang et al. (US Patent Application Publication 2024/0257693), herein after referred to as Hwang.
Regarding claim 20, Guy and Morimatsu discloses the electronic display of claim 15, wherein the content-addressable memory comprises pixel-level dithering circuitry configured to selectively perform N-bit dithering in a first configuration (Guy: C9 L26-29 describes adding a dither bit (1) to the LSB) [ ].
Neither Guy or Morimatsu disclose and M-bit dithering in a second configuration, wherein N is a first integer value and M is a second integer value different from the first integer value.
Hwang discloses pixel-level dithering circuitry configured to selectively perform N-bit dithering in a first configuration and M-bit dithering in a second configuration, wherein N is a first integer value and M is a second integer value different from the first integer value ([0094] dither number of bits is based on the crosstalk level including an example of 1 bit and 2 bits).
It would have been obvious to one skilled in the art before the effective filing date of the current application to enable Guy-Morimatsu with the known technique of selectively perform N-bit dithering in a first configuration and M-bit dithering in a second configuration, wherein N is a first integer value and M is a second integer value different from the first integer value yielding the predictable results of compensating for crosstalk as disclosed by Hwang ([0005]-[0007]).
Allowable Subject Matter
10. Claims 5-6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 5, Guy discloses the electronic display of claim 4.
However, Guy does not specifically disclose wherein the column-level subframe dithering circuitry comprises: a first flip-flop configured to store an output of a first read from a core cell of the content-addressable control circuitry; a second flip-flop configured to store an output of a second read from the core cell of the content-addressable control circuitry; and one or more logic gates configured to output one of the control signals based on an output of the first flip-flop and an output of the second flip-flop.
It is noted Kim et al. (US Patent Application Publication 2010/0013530) discloses a first flip-flop (F4A DFF1) configured to store (D) an output of a first read from a core cell of a content-addressable control circuitry;
a second flip-flop (DFF2) configured to store (D) an output of a second read (out Q of DFF1 similar to applicant’s Figure 22 282 Q output to D 284) from the core cell of the content-addressable control circuitry; and
one or more logic gates (L2) configured to output one of the control signals (output to modified clock and rising edge detector) based on an output of the first flip-flop (indirectly via DFF2) and an output of the second flip-flop (directly via DFF2 Q1).
However, Kim et al. does not specifically disclose the dithering circuitry regarding the column-level subframe as required by claim 4.
Regarding claim 14, Guy and Morimatsu discloses the content-addressable memory of claim 11.
However, Neither Guy or Morimatsu specifically disclose wherein: issuing the first control signal or the second control signal, or both, comprises performing two comparisons of pixel image data corresponding to the pixel to two counters at two immediately subsequent counter values using two comparators independently of a number of dithering bits used for dithering; and a multiplexer controlling which of the two comparator outputs is used based on a carry bit resulting from adding one or more of the dithering bits to one or more subframe index signals.
Regarding claim 17, Guy and Morimatsu discloses the electronic display of claim 15 (assumed dependency to claim 16).
However, neither art discloses wherein the multiple flip-flops are clocked to a frequency that is 2.sup.N that of a pixel active area clock for N-bit dithering, where N corresponds to an integer number.
Conclusion
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/CHRISTOPHER E LEIBY/Primary Examiner, Art Unit 2621
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