Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
In the response to this office action, the Examiner respectfully requests that support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line numbers in the specification and/or drawing figure(s). This will assist the Examiner in prosecuting this application.
ALLOWABLE SUBJECT MATTER
Claim 3-4, 6-9, 13-14, 16-17 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claims 3-4, 13-14, and 20 are objected because the cited references do not disclose “a first clock signal wire connected to the transistor A of the odd-numbered stages and to the transistor C of the even-numbered stages; a second clock signal wire connected to the transistor B of the odd-numbered stages; a third clock signal wire connected to the transistor B of the even-numbered stages; and a fourth clock signal wire connected to the transistor C of the odd-numbered stages and to the transistor A of the even-numbered stages.” Claims 6 and 16 are objected because the cited references do not disclose “wherein, when viewed in the second direction, the transistor A of the odd-numbered stages is positioned adjacent to the transistor C of the even-numbered stages, when viewed in the second direction, the transistor B of a (2K−1).sup.th stage is positioned adjacent to the transistor B of a (2K+1).sup.th stage, with the transistor D of a (2K).sup.th stage interposed therebetween, where K is a natural number, when viewed in the second direction, the transistor C of the odd-numbered stages is positioned adjacent to the transistor A of the even-numbered stages, and when viewed in the second direction, the transistor D of the (2K−1).sup.th stage is positioned adjacent to the transistor D of the (2K+1).sup.th stage, with the transistor B of the (2K).sup.th stage interposed therebetween”. Claims 7-9 are objected because the cited references do not disclose “a second electrode connected to a start signal input node, and wherein the transistor A of the even-numbered stages includes a first electrode connected to a Q node of a corresponding even-numbered transistor, a gate electrode to which the second clock signal is applied, and a second electrode connected to a start signal input node”. Claim 17 is objected because the cited references do not disclose wherein the transistor A of the odd-numbered stages includes a first electrode connected to a Q node of a corresponding odd-numbered transistor, a gate electrode to which the first clock signal is applied, and a second electrode connected to a start signal input node, the transistor A of the even-numbered stages includes a first electrode connected to a Q node of a corresponding even-numbered transistor, a gate electrode to which the second clock signal is applied, and a second electrode connected to a start signal input node, the transistor B of the odd-numbered stages includes a first electrode, a gate electrode to which the first clock signal is applied, and a second electrode, the transistor B of the even-numbered stages includes a first electrode, a gate electrode to which the second clock signal is applied, and a second electrode, the transistor C of the odd-numbered stages includes a first electrode, a gate electrode connected to a start signal input node, and a second electrode to which the second clock signal is applied, and the transistor C of the even-numbered stages includes a first electrode, a gate electrode connected to a start signal input node, and a second electrode to which the first clock signal is applied”.
INFORMATION DISCLOSURE STATEMENT
The information disclosure statement filed 09/29/2025, has been acknowledged and considered by the examiner. An initialed copy of the PTO-1449 is included in this correspondence.
CLAIM REJECTIONS - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention
1. Claims 1-2, 5, 10, and 19 are rejected under 35 U.S.C. 102 (a) (1) as being anticipated by Feng et al. US 20230154410.
Consider claim 1. Feng discloses a display panel [0070]-[0071] OLED display apparatus and display panel 1 comprising:
sub-pixel circuits fig. 1A-1B display region 10 with subpixels circuits P [0074] pixel driver circuits 12. also see fig. 4A-4D, 5A-5B fig. 7A-7C ;
a gate driving circuit fig. 1A and 1C 13 gate driver circuit including transistors fig. 1D see equivalent circuit of a shift register which includes transistors positioned between the sub-pixel circuits fig. 1A 1D 131 132 between pixels P also see fig. 1A 2A [0149-0150] at least one thin film transistor group 131 is located in the display region 10 and distributed between adjacent sub-pixels P in a same row of sub-pixels. Each thin film transistor group 131 includes, for example, one first thin film transistor 1310;
first-direction wires positioned in parallel along a first direction fig. 1A fig. 2A control signal lines 132 extending in horizontal direction ; and
second-direction wires positioned in parallel along a second direction intersecting the first direction fig. 1A fig. 2A control signal lines 132 extending in vertical direction,
wherein the gate driving circuit includes:
a plurality of odd-numbered stages fig. 1C first, third and fifth stage of the shift register 130; and
a plurality of even-numbered stages fig. 1C second, fourth and sixth stage of the shift register 130,
wherein each of the odd-numbered stages and the even-numbered stages includes a transistor A, a transistor B, and a transistor C see fig. 1A and 2A first rows has thin film transistor groups 131 in between pixels including shown first, second, third, and fourth transistor which correspond to transistors A, B, D and C , and wherein the transistor A, the transistor B, and the transistor C of the odd-numbered stages are arranged in an order from one side to another side in the first direction see fig. 1A and 2A e.g. see first rows has thin film transistor groups 131 in between pixels including shown first, second, third, and fourth transistor extending from left to right corresponding to transistors A, B, D and C,
and wherein the transistor C, the transistor B, and the transistor A of the even-numbered stages are arranged in an order from the one side to the another side in the first direction fig. 1A and 2A e.g. see second rows has thin film transistor groups 131 in between pixels including shown first, second, third, and fourth transistor extending from left to right corresponding to transistors A, B, D and C.
Consider claim 2. Feng discloses the display panel of claim 1, wherein a first clock signal is applied to the transistor A and the transistor B of the odd-numbered stages, a second clock signal is applied to the transistor C of the odd-numbered stages, the second clock signal is applied to the transistor A and the transistor B of the even-numbered stages, and the first clock signal is applied to the transistor C of the even-numbered stages. see [0232-0233] fig. 7A-C7 figs 8B M24 transistors are connected to CLKE fig. 8D M5 and M27 connected to clock signal line 133 CLKA and CLKD fig. 1D [0099]. also see fig. 9 where transistors A B C in even and odd stages are connected to lines 133 which connect to clock signals. Note that the claim does not recite that the first and second clock signals are different. Thus, they can be the same or different.
Consider claim 5. Feng discloses the display panel of claim 1, wherein each of the odd-numbered stages further includes a transistor D positioned between the transistor B and the transistor C of the odd-numbered stage in the first direction see fig. 1A and 2A first rows has thin film transistor groups 131 in between pixels including shown first, second, third, and fourth transistor which correspond to transistors A, B, D and C, and each of the even-numbered stages further includes a transistor D positioned between the transistor B and the transistor C of the even-numbered stage in the first direction fig. 1A and 2A e.g. see second rows has thin film transistor groups 131 in between pixels including shown first, second, third, and fourth transistor extending from left to right corresponding to transistors A, B, D and C.
Consider claim 10. Feng discloses the display panel of claim 1, wherein the gate driving circuit includes a light emitting driving circuit configured to supply an emission signal to the sub-pixel circuits fig. 1D and fig. 1F.
Claim 19 is rejected for similar reasons, mutatis mutandis, to claim 1.
CLAIM REJECTIONS - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 , if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
2. Claims 11, 12, 15, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Feng et al. US 20230154410 in view of Jang et al. US 20250384829.
Consider claim 11. Feng discloses a display device[0070] OLED display apparatus comprising:
a display panel [0071] display panel 1 including sub-pixel circuits fig. 1A-1B display region 10 with subpixels circuits P [0074] pixel driver circuits 12. also see fig. 4A-4D, 5A-5B fig. 7A-7C , a gate driving circuit fig. 1A and 1C 13 gate driver circuit including transistors fig. 1D see equivalent circuit of a shift register which includes transistors positioned between the sub-pixel circuits fig. 1A 1D 131 132 between pixels P also see fig. 1A 2A [0149-0150] at least one thin film transistor group 131 is located in the display region 10 and distributed between adjacent sub-pixels P in a same row of sub-pixels. Each thin film transistor group 131 includes, for example, one first thin film transistor 1310;
first-direction wires positioned in parallel along a first direction fig. 1A fig. 2A control signal lines 132 extending in horizontal direction ; and
second-direction wires positioned in parallel along a second direction intersecting the first direction fig. 1A fig. 2A control signal lines 132 extending in vertical direction,
supply a data signal and at least one clock signal to the display panel see fig. 1B data line supplies data signal to pixel circuit and see fig. 1C and fig. 1D
wherein the gate driving circuit includes:
a plurality of odd-numbered stages fig. 1C first, third and fifth stage of the shift register 130; and
a plurality of even-numbered stages fig. 1C second, fourth and sixth stage of the shift register 130,
wherein each of the odd-numbered stages and the even-numbered stages includes a transistor A, a transistor B, and a transistor C see fig. 1A and 2A first rows has thin film transistor groups 131 in between pixels including shown first, second, third, and fourth transistor which correspond to transistors A, B, D and C , and wherein the transistor A, the transistor B, and the transistor C of the odd-numbered stages are arranged in an order from one side to another side in the first direction see fig. 1A and 2A e.g. see first rows has thin film transistor groups 131 in between pixels including shown first, second, third, and fourth transistor extending from left to right corresponding to transistors A, B, D and C,
and wherein the transistor C, the transistor B, and the transistor A of the even-numbered stages are arranged in an order from the one side to the another side in the first direction fig. 1A and 2A e.g. see second rows has thin film transistor groups 131 in between pixels including shown first, second, third, and fourth transistor extending from left to right corresponding to transistors A, B, D and C.
Feng does not explicitly disclose and a source circuit electrically connected to a pad region of the display panel supply at least one clock signal to the display panel.
Jang however discloses a source circuit electrically connected to a pad region of the display panel see fig. 1 Data driver 400 is in the pad region and supply at least one clock signal to the display panel [0068] the data driver 400 operates in response to a third control signal (CS3). In embodiments, the third control signal (CS3) may include a source start pulse, a source shift clock, a source output enabling signal, and so on.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the display panel of Feng to include a source circuit electrically connected to a pad region of the display panel region and supply at least one clock signal to the display panel, as taught by Jang, to regulate horizontal pixel progression preventing display artifacts like jitter, image tearing or scrambled lines.
Claim 12 is rejected for similar reasons, mutatis mutandis, to claim 2.
Claim 15 is rejected for similar reasons, mutatis mutandis, to claim 5.
Claim 18 is rejected for similar reasons, mutatis mutandis, to claim 10.
CONCLUSION
Any inquiry concerning this communication or earlier communications from the examiner should be directed to IBRAHIM A KHAN whose telephone number is (571)270-7998. The examiner can normally be reached on 10am-6pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Nitin Patel can be reached on 571-272-7677. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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IBRAHIM A. KHAN
Primary Examiner
Art Unit 2628
/IBRAHIM A KHAN/ 07/22/2026Primary Examiner, Art Unit 2628
Prosecution Insights