DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, 4-6, 8-10, 12-15, 17, and 18 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Bae et al. (US 20250372022 A1, hereafter Bae).
Regarding claim 1, Bae teaches a method for a display driver circuit, comprising:
receiving an input frame having a plurality of slices from a host processor (Fig. 1, [0062], where input image data IDAT for a frame period is received, the input image data corresponding to a panel region; Figs. 11 and 12, [0108], [0113], where each panel region of the display panel is divided into a plurality of slices);
detecting the earliest horizontal synchronization start packet in the plurality of slices, wherein the earliest horizontal synchronization start packet indicates a start of the earliest slice of a full refresh display area of an output frame (Fig. 3, [0073], where for a given packet region, i.e., plurality of slices, there is received a horizontal synchronization packet HSP to drive the update of the first panel region); and
updating the full refresh display area of the output frame in response to that the earliest horizontal synchronization start packet of the earliest slice of the full refresh display area is detected (Figs. 11 and 12, [0112]-[0114], where the panel region is updated according to the received signals, the HSP occurring at the beginning of a frame period FP1).
Regarding claim 2, Bae teaches the method of claim 1, wherein the step of updating the full refresh display area of the output frame comprises:
determining when to update the full refresh display area of the output frame without considering whether a page address setting command is received or not ([0073]-[0074], where no page address setting command is provided during driving).
Regarding claim 4, Bae teaches the method of claim 1, further comprising: stopping updating a partial refresh display area of the output frame when no horizontal synchronization start packet is detected in another slice of the partial refresh display area ([0074], where the HSP is not provided is not provided in a second panel region where display is not updated).
Regarding claim 5, Bae teaches a method for a display driver circuit, comprising:
receiving an input frame having a plurality of slices from a host processor (Fig. 1, [0062], where input image data IDAT for a frame period is received, the input image data corresponding to a panel region; Figs. 11 and 12, [0108], [0113], where each panel region of the display panel is divided into a plurality of slices);
detecting a transmission start packet indicating a start of a full refresh display area of the input frame and a transmission end packet indicating an end of the full refresh display area of the input frame ([0057]-[0060], where the panel driver provides command packets for both beginning and ending a frame period); and
updating the full refresh display area of an output frame according to the transmission start packet and the transmission end packet (Figs. 11 and 12, [0112]-[0114], where the panel region is updated according to the received signals, the HSP occurring at the beginning of a frame period FP1; [0067], [0074], where the period VFP indicates that no data is to be transferred).
Regarding claim 6, Bae teaches the method of claim 5, wherein the step of updating the full refresh display area of the output frame comprises:
determining when to update the full refresh display area of the output frame without considering whether a page address setting command is received or not ([0073]-[0074], where no page address setting command is provided during driving).
Regarding claim 8, Bae teaches the method of claim 5, wherein when the full refresh display area starts is determined by the transmission start packet, and when the full refresh display area ends is determined by the transmission end packet (Figs. 11 and 12, [0112]-[0114], where the panel region is updated according to the received signals, the HSP occurring at the beginning of a frame period FP1; [0067], [0074], where the period VFP indicates that no data is to be transferred).
Regarding claim 9, Bae teaches a method for a display driver circuit, comprising:
receiving an input frame having a plurality of slices from a host processor (Fig. 1, [0062], where input image data IDAT for a frame period is received, the input image data corresponding to a panel region; Figs. 11 and 12, [0108], [0113], where each panel region of the display panel is divided into a plurality of slices);
detecting the earliest valid data packet following a horizontal synchronization start packet in the plurality of slices (Fig. 3, [0073], where for a given packet region, i.e., plurality of slices, there is received a horizontal synchronization packet HSP to drive the update of the first panel region, the detection of the updated data packets following from the HSP); and
updating a full refresh display area of an output frame in response to that the earliest valid data packet is detected (Figs. 11 and 12, [0112]-[0114], where the panel region is updated according to the received signals, the HSP occurring at the beginning of a frame period FP1).
Regarding claim 10, Bae teaches the method of claim 9, wherein the step of updating the full refresh display area of the output frame comprises: determining when to update the full refresh display area of the output frame without considering whether a page address setting command is received or not ([0073]-[0074], where no page address setting command is provided during driving).
Regarding claim 12, Bae teaches the method of claim 9, further comprising: stopping updating a partial refresh display area of the output frame in response to that a slice having a blanking or low-power (BLLP) interval among the plurality of slices is detected ([0067], [0074], where the period VFP indicates that the data line is to be put in a low-power state).
Regarding claim 13, Bae teaches the method of claim 9, further comprising: stopping updating a partial refresh display area of the output frame in response to that a slice having a transmission end packet or a stop state among the plurality of slices is detected (Figs. 11 and 12, [0112]-[0114], where the panel region is updated according to the received signals, the HSP occurring at the beginning of a frame period FP1; [0067], [0074], where the period VFP indicates that no data is to be transferred).
Regarding claim 14, Bae teaches a method for a display driver circuit, comprising:
receiving an input frame having a plurality of slices from a host processor (Fig. 1, [0062], where input image data IDAT for a frame period is received, the input image data corresponding to a panel region; Figs. 11 and 12, [0108], [0113], where each panel region of the display panel is divided into a plurality of slices);
detecting an output signal sent from the host processor when receiving the input frame (Fig. 3, [0073], where for a given packet region, i.e., plurality of slices, there is received a horizontal synchronization packet HSP to drive the update of the first panel region); and
updating a full refresh display area of an output frame according to a level of the output signal (Figs. 11 and 12, [0112]-[0114], where the panel region is updated according to the received signals, the HSP occurring at the beginning of a frame period FP1).
Regarding claim 15, Bae teaches the method of claim 14, wherein the step of updating the full refresh display area of the output frame comprises: determining when to update the full refresh display area of the output frame without considering whether a page address setting command is received or not ([0073]-[0074], where no page address setting command is provided during driving).
Regarding claim 17, Bae teaches the method of claim 14, further comprising: stopping updating a partial refresh display area of the output frame when the output signal is in a second level different from the first level (Figs. 11 and 12, [0112]-[0114], where the panel region is updated according to the received signals, the HSP occurring at the beginning of a frame period FP1; [0067], [0074], where the period VFP has a low power data lane which indicates that no data is to be transferred).
Regarding claim 18, Bae teaches the method of claim 14, wherein the output signal is received through a general purpose output (GPO) pin of the display driver circuit ([0118]-[0119], where the host processor is a microprocessor or CPU as opposed to an application-specific processor).
Allowable Subject Matter
Claim 3, 7, 11, and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER D MCLOONE whose telephone number is (571)272-4631. The examiner can normally be reached M-F 9 AM - 5 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amr Awad can be reached at 5712727764. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/PETER D MCLOONE/Primary Examiner, Art Unit 2621
Prosecution Insights