DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
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Claims 2-7 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-6 of U.S. Patent No. 11,423,838. Although the claims at issue are not identical, they are not patentably distinct from each other because all claimed limitations of claims 2-7 of the instant application are encompassed by the claimed limitations of claims 1-6 of the patent.
Instant Application
U.S. Patent 11,423,838
An electro-optical device comprising: a scanning line extending along a first direction; a data line extending along a second direction intersecting the first direction; a light emitting element; a first transistor having a first gate electrode and a first source region, the first transistor being configured to supply a current to the light emitting element corresponding to a voltage between the first gate electrode and the first source region, and the voltage corresponding to a data signal; a second transistor that is electrically connected to the first gate electrode that has a second source region, a second drain region, and a second gate electrode; and a first contact that electrically connects the scanning line to the second gate electrode, wherein the data signal is transmitted via the data line and the second transistor, and in plan view, the first contact overlaps a region between the second source region and the second drain region.
An electro-optical device comprising: a scanning line extending in a first direction; a data line extending in a second direction intersecting the first direction; a light emitting element; a first transistor that has a first gate electrode and a first source region and is a second transistor that is electrically connected to the first gate electrode and the data line and that has a second source region, a second drain region, and a second gate electrode; and a first contact hole that electrically connects the scanning line to the second gate electrode, wherein in plan view, the first contact hole overlaps a region between the second source region and the second drain region.
The electro-optical device according to claim 2, further comprising: a second contact overlapping with the second source region in plan view; and a third contact overlapping with the second drain region in plan view, wherein in plan view, the first contact, the second contact, and the third contact are arranged along the second direction.
The electro-optical device according to claim 1, further comprising: a second contact hole overlapping with the second source region in plan view; and a third contact hole overlapping with the second drain region in plan view, wherein in plan view, the first contact hole, the second contact hole, and the third contact hole are arranged along the second direction.
The electro-optical device according to claim 2, further comprising: a wiring; a third transistor that has a third source region, a third drain region, and a third gate electrode; and a fourth contact that electrically connects the wiring to the third gate electrode, wherein in plan view, the fourth contact overlaps a region between the third source region and the third drain region.
The electro-optical device according to claim 1, further comprising: a wiring; a third transistor that has a third source region, a third drain region, and a third gate electrode; and a fourth contact hole that electrically connects the wiring to the third gate electrode, wherein in plan view, the fourth contact hole overlaps a region between the third source region and the third drain region.
The electro-optical device according to claim 3, further comprising: a wiring; a third transistor that has a third source region, a third drain region, and a third gate electrode; and a fourth contact that electrically connects the wiring to the third gate electrode, wherein in plan view, the fourth contact overlaps a region between the third source region and the third drain region.
The electro-optical device according to claim 2, further comprising: a wiring; a third transistor that has a third source region, a third drain region, and a third gate electrode; and a fourth contact hole that electrically connects the wiring to the third gate electrode, wherein in plan view, the fourth contact hole overlaps a region between the third source region and the third drain region.
The electro-optical device according to claim 4, further comprising: a fifth contact overlapping with the third source region in plan view; and a sixth contact overlapping with the third drain region in plan view, wherein in plan view, the fourth contact, the fifth contact, and the sixth contact are arranged along the second direction.
The electro-optical device according to claim 3, further comprising: a fifth contact hole overlapping with the third source region in plan view; and a sixth contact hole overlapping with the third drain region in plan view, wherein in plan view, the fourth contact hole, the fifth contact hole, and the sixth contact hole are arranged along the second direction.
The electro-optical device according to claim 5, further comprising: a fifth contact overlapping with the third source region in plan view; and a sixth contact overlapping with the third drain region in plan view, wherein in plan view, the fourth contact, the fifth contact, and the sixth contact are arranged along the second direction.
The electro-optical device according to claim 4, further comprising: a fifth contact hole overlapping with the third source region in plan view; and a sixth contact hole overlapping with the third drain region in plan view, wherein in plan view, the fourth contact hole, the fifth contact hole, and the sixth contact hole are arranged along the second direction.
Claim 2 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 2 and 4 of U.S. Patent No. 10,957,254 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because all claimed limitations of claim 2 of the instant application are encompassed by the claimed limitations of claims 1, 2 and 4 of the patent.
Instant application (claim 2)
U.S. 10,957,254 (claims 1, 2 and 4)
An electro-optical device comprising:
An electro-optical device comprising:
a scanning line extending along a first direction; a data line extending along a second direction intersecting the first direction; a light emitting element;
a scanning line; a data line; a light emitting element;
a first transistor having a first gate electrode and a first source region, the first transistor being configured to supply a current to the light emitting element corresponding to a voltage between the first gate electrode and the first source region, and the voltage corresponding to a data signal;
a first transistor having a first gate electrode, the first gate electrode being electrically connected to the scanning line;
a second transistor that is electrically connected to the first gate electrode that has a second source region, a second drain region, and a second gate electrode; and
a second transistor having a second gate electrode, the second transistor being electrically connected between the first feed line and the light emitting element;
a first contact that electrically connects the scanning line to the second gate electrode, wherein the data signal is transmitted via the data line and the second transistor, and in plan view, the first contact overlaps a region between the second source region and the second drain region.
a first contact hole that electrically connects between the second gate electrode and the first wiring; the second transistor has a drain and source that are arranged in a first direction; the first contact hole overlaps the second gate electrode when viewed in plan view.
Claim 2 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 4 and 6 of U.S. Patent No. 9,721,506 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because all claimed limitations of claim 2 of the instant application are encompassed by the claimed limitations of claims 1, 4 and 6 of the patent.
Instant application (claim 2)
U.S. 9,721,506 (claims 1, 4 and 6)
An electro-optical device comprising:
An electro-optical device comprising:
a scanning line extending along a first direction; a data line extending along a second direction intersecting the first direction; a light emitting element;
a light emitting element; a data line extending in a second direction intersecting the first direction; a light emitting element (inherently included in the electro-optical display device)
a first transistor having a first gate electrode and a first source region, the first transistor being configured to supply a current to the light emitting element corresponding to a voltage between the first gate electrode and the first source region, and the voltage corresponding to a data signal;
a feed line; a driving transistor electrically connected between the feed line and the light emitting element; a first transistor having a first gate electrode, the first transistor being electrically connected between the light emitting element and the driving transistor;
a second transistor that is electrically connected to the first gate electrode that has a second source region, a second drain region, and a second gate electrode; and
a second transistor having a second gate electrode, wherein the first wiring is provide to intersect the second gate electrode when viewed in plan view;
a first contact that electrically connects the scanning line to the second gate electrode, wherein the data signal is transmitted via the data line and the second transistor, and in plan view, the first contact overlaps a region between the second source region and the second drain region.
a first contact hole formed in the insulating layer through which the first gate electrode is electrically connected to the first wiring; the first contact hole overlaps the first gate electrode when viewed in plan view.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made.
Claims 2-7 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Shishido (US 2008/0143653 A1) in view of Yang (US 2006/0097261 A1).
Regarding independent claim 2, Shishido discloses an electro-optical device (light emitting display device, para. 0038) comprising:
a scanning line (308, fig. 20) extending along a first direction (para. 0143);
a data line (307) extending along a second direction intersecting the first direction (para. 0143);
a light emitting element (315) (para. 0143);
a first transistor (303) having a first gate electrode and a first source region, the first transister being configured to supply a current (VDD) to the light emitting element (315) corresponding to a voltage between the first gate electrode and the first source region (a gate electrode of the third transistor 303 is connected to the second scan line 309, and a first electrode of the third transistor 303 is connected to the first power supply line 312 (para. 0143). In the third period T3, the second scan line 309 and the fourth scan line 311 become an L level, and the third transistor 303 and the fifth transistor 305 are turned on. In addition, the first scan line 308 and the third scan line 310 become an H level, and the second transistor 302 and the fourth transistor 304 are turned off. Thus, the first electrode of the first transistor 301 is connected to the first power supply line 312 (para. 0155). The current IOLED which is dependent on the video signal voltage Vdata is supplied to the light-emitting element 315 in the third period T3, so that the light-emitting element 315 emits light (para. 0158)). The first transistor 301 supplies the voltage Vdata corresponding to a data signal (para. 0128 and 0154);
a second transistor (305) that is electrically connected to the first gate electrode (the third transistor 303, and the fifth transistor 305 are controlled with the first scan line 308, para. 0208) and the data line (307) and that has a second source region, a second drain region, and a second gate electrode (para. 0143); and
a first contact that electrically connects the scanning line to the second gate electrode (e.g., a node that connects the gate electrode of the transistor 305 to the scanning line 308, fig. 20, para. 0208), wherein the data signal is transmitted via the data line and the second transistor (para. 0156, 0200, and 0207-0208), and
in plan view, the first contact overlaps a region between the second source region and the second drain region (the layout of pixel circuit as shown in fig. 37, the first contact overlaps a middle region between drain and source regions of the transistor 305, para. 0296).
Shishido does not specifically disclose the same first contact.
In a similar field of endeavor of a display device comprises a transistor structure, Yang discloses the first contact comprise a first contact hole (contact holes 291 electrically connects a gate line 202 to a gate electrode 206, fig. 3, para. 0052).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to incorporate the contact hole as taught by Yang in the system of Shishido in order to allow signal that passes through the contact hole, and hence enhance the performance of the semiconductor device.
Regarding claim 3, Shishido discloses a second contact overlapping with the second source region in plan view (a contact hole overlaps the source region of the second transistor 305, fig. 37); and
a third contact overlapping with the second drain region in plan view (a contact hole overlaps the drain region of the second transistor 305, fig. 37), wherein
in plan view, the first contact, the second contact, and the third contact are arranged along the second direction (gate electrode, source and drain of the second transistor 305 are arranged along the signal line 307 direction, fig. 20).
Regarding claims 4 and 5, Shishido discloses a wiring (310, fig. 20);
a third transistor (304) that has a third source region, a third drain region, and a third gate electrode (para. 0143); and
a fourth contact that electrically connects the wiring to the third gate electrode (gate electrode of the transistor 304 that electrically connects to the wiring 310, figs. 20 and 37), wherein
in plan view, the fourth contact overlaps a region between the third source region and the third drain region (the layout of pixel circuit as shown in fig. 37, the gate electrode of the transistor 304 overlaps a middle region between drain and source regions of the transistor 305, para. 0296).
Regarding claims 6 and 7, Shishido discloses a fifth contact overlapping with the third source region in plan view (a contact hole overlaps the source region of the third transistor 304, fig. 37); and
a sixth contact overlapping with the third drain region in plan view (a contact hole overlaps the drain region of the third transistor 304, fig. 37), wherein
in plan view, the fourth contact, the fifth contact, and the sixth contact are arranged along the second direction (gate electrode, source and drain of the third transistor 304 are arranged along the signal line 307 direction, fig. 20).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure is made of record in the attached notice of references cited, especially:
Tanikame et al. (US 2009/0273547 A1) discloses a display apparatus employing a plurality of pixel circuits (para. 0095) each pixel circuit comprises transistors each made of semiconductor layers, the inter-layer insulation layers and contact holes (para. 0110).
Kwak et al. (US 2006/0170634 A1) discloses organic light emitting device includes: a plurality of thin film transistors, each thin film transistor including a gate electrode, and source and drain electrodes; a data line and a power supply line formed in the same layer as the source and drain electrodes; a passivation layer formed on the plurality of thin film transistors; a planarization layer formed on the passivation layer; a via hole formed in the passivation layer and the planarization layer and exposing one of the source and drain electrodes; a pixel electrode formed on the planarization layer and connected to one of the source and drain electrodes through the via hole (para. 0015).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PARUL H GUPTA whose telephone number is (571)272-5260. The examiner can normally be reached Monday through Friday, from 10 AM to 7 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ke Xiao can be reached at 571-272-7776. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PARUL H GUPTA/Primary Examiner, Art Unit 2627
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