DETAILED ACTIONNotice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Fujiwara et al (2012/0139823) (herein “Fujiwara”). In regards to claim 1, Fujiwara teaches a display apparatus, comprising: a backlight assembly (See; Fig. 1 for backlight unit 16), comprising: at least one drive group, wherein one drive group comprises at least one first drive chip and at least one second drive chip, a quantity of channels of a first drive chip differs from a quantity of channels of a second drive chip, and the at least one first drive chip and the at least one second drive chip are connected in series (See; Fig. 9 for LED drivers 5s, 5t and 5u connected in series where LED drivers 5s and 5t comprises 12 channels and LED driver 5u comprises 3 channels); and at least one light-emitting unit group, wherein one light-emitting unit group comprises a plurality of light sources, each of the plurality of light sources is connected to the first drive chip or the second drive chip via a channel of the first drive chip or the second drive chip (See; Fig. 9 for LEDs R1,G1, B1 – R9, G9, B9 each connected to a channel of one of the LED drivers); and a controller, connected to the at least one drive group and configured to: control the at least one drive group to drive the at least one light-emitting unit group to emit light based on drive data and a quantity of channels of the at least one drive group (See; Fig. 9 for LED controller 61).
In regards to claim 2, Fujiwara teaches wherein a sum of a quantity of channels of the at least one first drive chip and a quantity of channels of the at least one second drive chip in the one drive group equals a quantity of the plurality of light sources in the one light-emitting unit group, and the at least one first drive chip and the at least one second drive chip are connected one-to-one with the plurality of light sources in the one light-emitting unit group through channels corresponding to the plurality of light sources (See; Fig. 9 where each channel has a one to one correspondence with the LEDs 62).
In regards to claim 3, Fujiwara teaches wherein the at least one first drive chip and the at least one second drive chip within the one drive group correspond to one light-emitting unit group, the one light-emitting unit group comprises at least one row or at least one column of light sources (See; Fig. 9 where each channel has a one to one correspondence with the LEDs 62).
In regards to claim 4, Fujiwara teaches wherein each drive group among the at least one drive group is assigned a physical address, and different drive groups correspond to different physical addresses (See; Fig. 5, 9 and p[0119] where each LED driver has a different physical address).
In regards to claim 5, Fujiwara teaches wherein a physical address of the first drive chip is the physical address of the drive group to which the first drive chip belongs (See; Fig. 5, 9 and p[0119] where each LED driver has a different physical address). In regards to claim 6, Fujiwara teaches wherein the at least one first drive chip and the at least one second drive chip within the one drive group share the same physical address, and each of the at least one first drive chip and the at least one second drive chip within the one drive group is assigned an internal address, wherein different drive chips within the one drive group are provided with different internal addresses (See; Fig. 5, 9, p[0119] and p[0123] where each LED driver has a different physical address where each separate driver is supplied a different internal address from terminal 61c).
In regards to claim 7, Fujiwara teaches wherein the controller is further configured to: transmit the drive data to a target drive chip based on a physical address of the drive group to which the target drive chip belongs and an internal address of the target drive chip (See; Fig. 5, 9, p[0119] and p[0123] where each LED driver has a different physical address where each separate driver is supplied a different internal address from terminal 61c).
In regards to claim 8, Fujiwara teaches wherein the internal address is a burned-in address or a serial address (See; Fig. 9 and p[0072] for a serial arrangement).
In regards to claim 9, Fujiwara teaches wherein first drive chips or second drive chips with the same quantity of channels are connected in series and adjacent to each other (See; Fig. 9).
In regards to claim 10, Fujiwara teaches wherein the quantity of channels of the first drive chip is greater than the quantity of channels of the second drive chip (See; Fig. 9).
In regards to claim 11, Fujiwara teaches wherein the first drive chip is positioned before the second drive chip (See; Fig. 9).
In regards to claim 12, Fujiwara teaches wherein the controller is connected to a drive chip corresponding to a address calibration circuit within the drive group via the address calibration circuit (See; Fig. 4 for various circuits connected to the drive chip controlling the data such as information processing portion 52 and data latch portion 56. Where an address calibration circuit is broadly recited and is not a known term in the art).
In regards to claim 13, Fujiwara teaches wherein a control terminal and a first terminal of the address calibration circuit are connected to the controller, and an output terminal of the address calibration circuit is connected to an input terminal of the drive chip corresponding to the address calibration circuit (See; Fig. 4).
In regards to claim 14, Fujiwara teaches wherein the address calibration circuit is configured to obtain address data output by the controller from the control terminal of the address calibration circuit, and when the address data comprises an address of the drive chip connected to the address calibration circuit, send the drive data obtained through the first terminal to the drive chip (See; Figs. 4, 6 and 9).
In regards to claim 15, Fujiwara teaches wherein different address calibration circuits correspond to different address data (See; Figs. 4, 6 and 9).
In regards to claim 16, Fujiwara teaches wherein quantities of first drive chips in different drive groups are the same, and quantities of second drive chips in different drive groups are the same (See; Fig. 9).
In regards to claim 17, Fujiwara teaches, wherein quantities of first drive chips in different drive groups are different (See; Fig. 9).
In regards to claim 18, Fujiwara teaches wherein quantities of second drive chips in different drive groups are different (See; Fig. 9).
In regards to claim 19, Fujiwara teaches wherein a sequence of data segments in the drive data of the one drive group is consistent with a sequence of the at least one first drive chip and the at least one second drive chip within the drive group (See; Fig. 9).
In regards to claim 20, Fujiwara teaches wherein a sequence of a data segment corresponding to the first drive chip within the drive data of the drive group is consistent with a sequence of the first drive chip among the at least one first drive chip; and a sequence of a data segment corresponding to the second drive chip within the drive data of the drive group is reverse to a sequence of the second drive chip among the at least one second drive chip (See; Fig. 9).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONATHAN A BOYD whose telephone number is (571)270-7503. The examiner can normally be reached Mon - Fri 8:00 - 5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ke Xiao can be reached at (571) 272-7776. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JONATHAN A BOYD/Primary Examiner, Art Unit 2627
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