Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are currently under review.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on September 30, 2025 is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Objections
Claims 19-20 are objected to because of the following informalities: typographic errors. Appropriate correction is required.
Claim 19, lines 1-2: “wherein [[the]]a plurality of transistors in [[the]]another pixel include a second transistor including [[the]]an oxide semiconductor”
Claim 20, line 8: “a pull-up transistor and a pull-down transistor, wherein a gate electrode of the pull-up”
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 9-13 and their dependent (claim 14) are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 9 indicates “the gate electrode of the first control transistor is configured to receive the second scan clock … , and the gate electrode of the second control transistor is configured to receive a fourth scan clock,” however claim 1 indicates “a gate electrode of the first control transistor is configured to receive a first scan clock … and a gate electrode of the second control transistor is configured to receive a third scan clock or the second scan clock”, therefore it is unclear if the applicant meant for the gate electrode of the first control transistor to receive either a first scan clock or a second scan clock and it is unclear if the applicant meant for the gate electrode of the second control transistor to receive either a third scan clock or the second scan clock or a fourth clock signal. Additionally the specification only mentions that the gate electrode of the first control transistor only receives one signal. Figures 9 and 10 show different implementations/embodiments where the second control transistor receives either SCLK1 or SCLKB2. With respect to Claim 10, claim 10 indicates “wherein a low section of the second scan clock is set to a width greater than a high section of the carry signal, and a high section of the second scan clock is set to a width less than a low section of the first scan clock” however claim 1 indicates, “a gate electrode of the second control transistor is configured to receive a third scan clock or the second scan clock”. Since figures 9 and 10 show different embodiments, it is unclear which scan clock signal is received by the gate electrode of the second control transistor since it can only receive one signal. The same holds true for claims 11-12 since the gate electrode of the second control transistor only receive one signal. With respect to claim 13, the claim limitations indicate “the drain electrode of the pull up transistor is configured to receive the first scan clock, the gate electrode of the first control transistor is configured to receive the second scan clock, and the gate electrode of the second control transistor is configured to receive the first scan clock” however claim 1 indicates “a gate electrode of the first control transistor is configured to receive a first scan clock, a drain electrode of the pull-up transistor is configured to receive a second scan clock, and a gate electrode of the second control transistor is configured to receive a third scan clock or the second scan clock” which contradicts what scan clock signal each transistor receives since in each embodiment a transistor receives only a single signal.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 6-8, and 19-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Zheng et al. (Pub. No.: US 2026/0024499 A1).
With respect to Claim 1, Zheng discloses a display apparatus (fig. 1, item 10; ¶18), comprising: a display panel (figs. 1-2, item 14; ¶17-18) including a pixel (fig. 2, item 22; ¶19), wherein the pixel includes a light emitting diode (fig. 2, item 26; ¶20) and a plurality of transistors (fig. 2, item 28; fig. 3, items Tsw, Tdrive, Tem; ¶20; ¶28) configured to be electrically connected to the light emitting diode; and a first scan driving circuit (fig. 5, item 34; ¶42-43) including, for each of a plurality of horizontal lines of the display panel, a first scan stage (fig. 2, item 100-1; fig. 4, item 100; fig. 5, item 100-1; ¶33; ¶43) that is configured to output a first scan signal of the horizontal line, wherein the first scan stage includes: a pull-up transistor (fig. 4, item T1) and a pull-down transistor (fig. 4, item T2), wherein a gate electrode of the pull up transistor is connected to a first node (fig. 4, item Q2) and a gate electrode of the pull-down transistor is connected to a second node (fig. 4, item Q1); a transfer transistor (fig. 4, item T3) connected between the first node (fig. 4, item Q2) and a third node (fig. 4, Q0 via item T6 or T7); a first control transistor (fig. 4, item T8) and a second control transistor (fig. 4, item T9) which are connected in parallel to each other (¶39), have a first electrode configured to receive a carry signal (fig. 4, item CR_IN = carry signal; ¶39), and have a second electrode connected to the third node (fig. 4, item Q0 = third node); and a third control transistor (fig. 4, item T6) and a fourth control transistor (fig. 4, item T7) which are connected in series to each other with the second node (fig. 4, item Q1 = second node) therebetween, and have respective gate electrodes connected to the third node (fig. 4, gates connected to Q0), wherein the first scan stage (fig. 2, item 100-1; ¶23; ¶33) that is configured to output the first scan signal of a n-th horizontal line is configured to apply the first scan signal of the n-th horizontal line to a first transistor (fig. 2, transistor shown in item 22 of the top row and left column pixel) among the plurality of transistors (fig. 2, transistors of the array of pixels 22; ¶24), and wherein in the first scan stage that is configured to output the first scan signal of the n-th horizontal line (¶23), a gate electrode of the first control transistor (fig. 4, item T8) is configured to receive a first scan clock (fig. 4, item CLK_B = first scan clock), a drain electrode of the pull-up transistor is configured to receive a second scan clock (fig. 4, item CLK_BUF = second scan clock), and a gate electrode of the second control transistor (fig. 4, item T9) is configured to receive a third scan clock (fig. 4, item CLK_A).
With respect to Claim 2, claim 1 is incorporated, Zheng discloses wherein the pull-up and pull-down transistors, the first and fourth control transistors and the transfer transistor include oxide semiconductors (¶25, “gate driver circuitry 34 may be formed using only semiconducting oxide transistors”).
With respect to Claim 3, claim 2 is incorporated, Zheng discloses wherein the first transistor among the plurality of transistors includes an oxide semiconductor (¶25, “pixels 22 and gate driver circuitry 34 may be formed using only semiconducting oxide transistors”).
With respect to Claim 4, claim 1 is incorporated, Zheng discloses wherein the pull-up and pull-down transistors, the first and fourth control transistors, the transfer transistor, and the first transistor among the plurality of transistors are N-type transistors (¶24, “gate driver circuitry 34 may be implemented using thin-film transistors such as semiconducting oxide transistors. Semiconducting oxide transistors are generally considered n-type (n-channel) transistors”).
With respect to Claim 6, claim 1 is incorporated, Zheng discloses further comprising a first capacitor (fig. 4, item C2) connected between the first node (fig. 4, item Q2) and a source electrode of the pull-up transistor (fig. 4).
With respect to Claim 7, claim 1 is incorporated, Zheng discloses further comprising a second capacitor (fig. 4, item C1) connected between the second node (fig. 4, item Q1 via item T7) and a source electrode of the pull-down transistor (fig. 4, via item VGL).
With respect to Claim 8, claim 1 is incorporated, Zheng discloses wherein, in the first scan stage that is configured to output the first scan signal of the n-th horizontal line (¶23; ¶33, the gate electrode of the second control transistor (fig. 4, item T9) is configured to receive the third scan clock (fig. 4, item CLK_A), the third scan clock and the first scan clock (fig. 4, item CLK_B = first scan clock) have opposite phases (fig. 6; ¶45), and a high section of the first scan clock and a high section of the second scan clock are separated by a predetermined time (fig. 6; ¶45).
With respect to Claim 19, claim 1 is incorporated, Zheng discloses wherein a plurality of transistors in another pixel include a second transistor including the oxide semiconductor (fig. 2; ¶25, “pixels 22 and gate driver circuitry 34 may be formed using only semiconducting oxide transistors”), and wherein the display apparatus further comprises a second scan stage that is configured to apply a second scan signal to the second transistor (fig. 2; ¶23; ¶33), wherein the second scan stage is configured with a same structure as the first scan stage that is configured to output the first scan signal of the n-th horizontal line (fig. 2; ¶23).
With respect to Claim 20, Zheng discloses a display panel (figs. 1-2, item 14; ¶17-18), comprising: a pixel (fig. 2, item 22; ¶19) including a light emitting diode (fig. 2, item 26; ¶20) and a plurality of transistors (fig. 2, item 28; fig. 3, items Tsw, Tdrive, Tem; ¶20; ¶28) configured to electrically connected to the light emitting diode; and a first scan driving circuit (fig. 5, item 34; ¶42-43) including a scan stage (fig. 2, item 100-1; fig. 4, item 100; fig. 5, item 100-1; ¶33; ¶43) that is configured to output a scan signal of a horizontal line of the display panel and to apply a scan signal to a first transistor among the plurality of transistors (¶23; ¶33), wherein the scan stage includes: a pull-up transistor (fig. 4, item T1) and a pull-down transistor (fig. 4, item T2), wherein a gate electrode of the pull-up transistor is connected to a first node (fig. 4, item Q2) and a gate electrode of the pull-down transistor is connected to a second node (fig. 4, item Q1); a transfer transistor (fig. 4, item T3) connected between the first node (fig. 4, item Q2) and a third node (fig. 4, Q0 via item T6 or T7); a first control transistor (fig. 4, item T8) and a second control transistor (fig. 4, item T9) which are connected in parallel to each other (¶39), have a first electrode configured to receive a carry signal (fig. 4, item CR_IN = carry signal; ¶39), and have a second electrode connected to the third node (fig. 4, item Q0 = third node); and a third control transistor (fig. 4, item T6) and a fourth control transistor (fig. 4, item T7) which are connected in series to each other with the second node (fig. 4, item Q1 = second node) therebetween, and have respective gate electrodes connected to the third node (fig. 4, gates connected to Q0), wherein a gate electrode of the first control transistor (fig. 4, item T8) is configured to receive a first scan clock (fig. 4, item CLK_B = first scan clock), a drain electrode of the pull-up transistor is configured to receive a second scan clock (fig. 4, item CLK_BUF = second scan clock), and a gate electrode of the second control transistor (fig. 4, item T9) is configured to receive a third scan clock or the second scan clock (fig. 4, item CLK_A).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 15-18 are rejected under 35 U.S.C. 103 as being unpatentable over Zheng as applied to claims 1 and 2 above, and further in view of Kim et al. (Pub. No.: US 2025/0022404 A1) hereinafter referred to as Kim.
With respect to Claim 15, claim 2 is incorporated, Zheng does not mention wherein the second and third control transistors include polycrystalline silicon.
Kim teaches a display apparatus (fig. 5, item 100: display device), comprising: a display panel (fig. 5, item 110; ¶137) including a pixel (fig. 5, item PX; ¶138), wherein the pixel includes a light emitting diode (fig. 6, item LD; ¶151) and a plurality of transistors (fig. 6, transistors within item PX = plurality of transistors) configured to be electrically connected to the light emitting diode; and a first scan driving circuit (fig. 5, item 130; ¶141-142) including, for each of a plurality of horizontal lines of the display panel, a first scan stage that is configured to output a first scan signal of the horizontal line, wherein the first scan stage (fig. 1, item 200; ¶61) includes: a pull-up transistor (fig. 1, item M13) and a pull-down transistor (fig. 1, item M14); a first control transistor (fig. 1, item M1; ¶70) and a second control transistor (fig. 1, item M2; ¶71) which are connected in parallel to each other (fig. 1), have a first electrode configured to receive a carry signal (fig. 1, item FLM; ¶196, “The first input terminal 211 receives the start signal FLM (or a scan signal GWi−1 of the previous stage circuit)”); a third control transistor (fig. 1, item M3; ¶75) and a fourth control transistor (fig. 1, item M4; ¶76) which are connected in series to each other (fig. 1), wherein the second and third control transistors include polycrystalline silicon (¶71; ¶75; ¶261, “the gate driver 1142 may include an amorphous silicon TFT gate driver circuit (ASG), a low temperature polycrystalline silicon (LTPS) TFT gate driver circuit”).
Therefore it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the display apparatus of Zheng, wherein the second and third control transistors include polycrystalline silicon, as taught by Kim so as to provide alternative transistor implementations of the first scan driving circuit.
With respect to Claim 16, claim 15 is incorporated, Zheng does not mention wherein the plurality of transistors in the pixel include a transistor including the polycrystalline silicon.
Kim teaches a display apparatus (fig. 5, item 100: display device), comprising: a display panel (fig. 5, item 110; ¶137) including a pixel (fig. 5, item PX; ¶138), wherein the pixel includes a light emitting diode (fig. 6, item LD; ¶151) and a plurality of transistors (fig. 6, transistors within item PX = plurality of transistors) configured to be electrically connected to the light emitting diode; and a first scan driving circuit (fig. 5, item 130; ¶141-142) including, for each of a plurality of horizontal lines of the display panel, a first scan stage that is configured to output a first scan signal of the horizontal line, wherein the first scan stage (fig. 1, item 200; ¶61) includes: a pull-up transistor (fig. 1, item M13) and a pull-down transistor (fig. 1, item M14); a first control transistor (fig. 1, item M1; ¶70) and a second control transistor (fig. 1, item M2; ¶71) which are connected in parallel to each other (fig. 1), have a first electrode configured to receive a carry signal (fig. 1, item FLM; ¶196, “The first input terminal 211 receives the start signal FLM (or a scan signal GWi−1 of the previous stage circuit)”); a third control transistor (fig. 1, item M3; ¶75) and a fourth control transistor (fig. 1, item M4; ¶76) which are connected in series to each other (fig. 1); wherein the second and third control transistors include polycrystalline silicon (¶71; ¶75; ¶261, “the gate driver 1142 may include an amorphous silicon TFT gate driver circuit (ASG), a low temperature polycrystalline silicon (LTPS) TFT gate driver circuit”); wherein the plurality of transistors in the pixel include a transistor including the polycrystalline silicon (fig. 6; ¶171, “For example, the first transistor M21, the second transistor M22, the fifth transistor M25, the sixth transistor M26, and the seventh transistor M27 may include a polysilicon semiconductor layer formed through a low temperature poly-silicon (LTPS) process as an active layer (channel)”).
Therefore it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the display apparatus of Zheng, wherein the plurality of transistors in the pixel include a transistor including the polycrystalline silicon, as taught by Kim so as to provide alternative transistor implementations of the pixel circuit.
With respect to Claim 17, claim 16 is incorporated, Zheng does not mention wherein the second and third control transistors, and the transistor including the polycrystalline silicon in the pixel are P-type transistors.
Kim teaches a display apparatus (fig. 5, item 100: display device), comprising: a display panel (fig. 5, item 110; ¶137) including a pixel (fig. 5, item PX; ¶138), wherein the pixel includes a light emitting diode (fig. 6, item LD; ¶151) and a plurality of transistors (fig. 6, transistors within item PX = plurality of transistors) configured to be electrically connected to the light emitting diode; and a first scan driving circuit (fig. 5, item 130; ¶141-142) including, for each of a plurality of horizontal lines of the display panel, a first scan stage that is configured to output a first scan signal of the horizontal line, wherein the first scan stage (fig. 1, item 200; ¶61) includes: a pull-up transistor (fig. 1, item M13) and a pull-down transistor (fig. 1, item M14); a first control transistor (fig. 1, item M1; ¶70) and a second control transistor (fig. 1, item M2; ¶71) which are connected in parallel to each other (fig. 1), have a first electrode configured to receive a carry signal (fig. 1, item FLM; ¶196, “The first input terminal 211 receives the start signal FLM (or a scan signal GWi−1 of the previous stage circuit)”); a third control transistor (fig. 1, item M3; ¶75) and a fourth control transistor (fig. 1, item M4; ¶76) which are connected in series to each other (fig. 1); wherein the second and third control transistors include polycrystalline silicon (¶71; ¶75; ¶261, “the gate driver 1142 may include an amorphous silicon TFT gate driver circuit (ASG), a low temperature polycrystalline silicon (LTPS) TFT gate driver circuit”); wherein the plurality of transistors in the pixel include a transistor including the polycrystalline silicon (fig. 6; ¶171, “For example, the first transistor M21, the second transistor M22, the fifth transistor M25, the sixth transistor M26, and the seventh transistor M27 may include a polysilicon semiconductor layer formed through a low temperature poly-silicon (LTPS) process as an active layer (channel)”); wherein the second and third control transistors (¶71; ¶75), and the transistor including the polycrystalline silicon in the pixel are P-type transistors (¶171, “The first transistor M21, the second transistor M22, the fifth transistor M25, the sixth transistor M26, and the seventh transistor M27 may be P-type transistors (for example, PMOS transistors)”).
Therefore it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the display apparatus of Zheng, wherein the second and third control transistors, and the transistor including the polycrystalline silicon in the pixel are P-type transistors, as taught by Kim so as to provide alternative transistor implementations.
With respect to Claim 18, claim 1 is incorporated, Zheng does not mention wherein the first transistor is configured to connect a gate electrode of a driving transistor among the plurality of transistors and a second electrode of the driving transistor in response to the first scan signal, or the first transistor is configured to transmit an initialization voltage to the gate electrode of the driving transistor in response to the first scan signal.
Kim teaches a display apparatus (fig. 5, item 100: display device), comprising: a display panel (fig. 5, item 110; ¶137) including a pixel (fig. 5, item PX; ¶138), wherein the pixel includes a light emitting diode (fig. 6, item LD; ¶151) and a plurality of transistors (fig. 6, transistors within item PX = plurality of transistors) configured to be electrically connected to the light emitting diode; and a first scan driving circuit (fig. 5, item 130; ¶141-142) including, for each of a plurality of horizontal lines of the display panel, a first scan stage that is configured to output a first scan signal of the horizontal line, wherein the first scan stage (fig. 1, item 200; ¶61) includes: a pull-up transistor (fig. 1, item M13) and a pull-down transistor (fig. 1, item M14); a first control transistor (fig. 1, item M1; ¶70) and a second control transistor (fig. 1, item M2; ¶71) which are connected in parallel to each other (fig. 1), have a first electrode configured to receive a carry signal (fig. 1, item FLM; ¶196, “The first input terminal 211 receives the start signal FLM (or a scan signal GWi−1 of the previous stage circuit)”); a third control transistor (fig. 1, item M3; ¶75) and a fourth control transistor (fig. 1, item M4; ¶76) which are connected in series to each other (fig. 1); wherein a first transistor (fig. 6, item M24) is configured to connect a gate electrode of a driving transistor (fig. 6, item M21) among the plurality of transistors and a second electrode of the driving transistor in response to the first scan signal (fig. 6, item GC; ¶179), or a first transistor (fig. 6, item M23) is configured to transmit an initialization voltage (fig. 6, item Vint1) to the gate electrode of the driving transistor in response to the first scan signal (fig. 6, item GI; ¶177).
Therefore it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the display apparatus of Zheng, wherein the first transistor is configured to connect a gate electrode of a driving transistor among the plurality of transistors and a second electrode of the driving transistor in response to the first scan signal, or the first transistor is configured to transmit an initialization voltage to the gate electrode of the driving transistor in response to the first scan signal, as taught by Kim so as to provide commonly implemented transistors in a pixel circuit.
Allowable Subject Matter
Claim 5 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: With respect to Claim 5, Zheng teaches a first electrode of the third control transistor (fig. 4, item T6) is configured to receive the gate high voltage (fig. 4, item VGH), and a first electrode of the fourth control transistor (fig. 4, item T7) and a source electrode of the pull-down transistor (fig. 4, item T2) are configured to receive a gate low voltage (fig. 4, item VG=L), however neither Zheng nor the prior art teaches wherein a gate electrode of the transfer transistor is configured to receive a gate high voltage including all the base limitations.
Conclusion
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/DONNA V Bocar/ Primary Examiner, Art Unit 2621
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