DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 6 is objected to because of the following informalities: the phrase “The pixel circuit of claim 2 or 4” is unclear. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 9, 11 and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (US 2022/0180812).
Regarding claim 1, Lin discloses a pixel circuit (22, fig. 17A) comprising:
a light-emitting element (304, para. 0057);
a driving element (Tdrive, para. 0110) that drives the light-emitting element and includes a first electrode connected to a first node (a node between Tdrive and Tem1), a gate electrode connected to a second node (a node between Tdive and Cst), and a
second electrode connected to a third node (a node between Tdive and Tem2);
a first switch element (Tdata, paras. 0109-0110) that supplies a data voltage (Data) to the second node in response to a first scan signal (SC1);
a second switch element (Toxide, paras. 0109-0110) that supplies a reference voltage (Vini) to the second node in response to a second scan signal (SC1);
a third switch element (Tem1, paras. 0109-0110) that supplies a pixel driving voltage (VDDEL) to the first node in response to a first emission signal (EM);
a fourth switch element (Tem2, , paras. 0109-0110) that connects a fourth node (a node between Tem2 and 304) to the third node in response to a second emission signal (EM);
a compensation circuit (Tar, paras. 0109 and 0115) that supplies an initialization voltage (Var) to the fourth node in response to a third scan signal (SC3) and supplies a compensation voltage for compensating for a ripple in the initialization voltage (Var) to the fourth node (para. 0115); and
a first capacitor (Cst, para. 0055) connected between the second node and the third node.
Regarding claim 9, Lin discloses a pixel circuit (22, fig. 17A) comprising:
a light-emitting element (304, para. 0057);
a driving element (Tdrive, para. 0110) that drives the light-emitting element (304) and includes a first electrode connected to a line to which a pixel driving voltage (VDDEL) is applied, a gate electrode connected to a first node (a node between Tdrive and Cst), and a second electrode connected to a second node (a node between Tdrive and Tem2);
a first switch element (Tdata, paras. 0109-0110) that supplies a data voltage (Data) to the first node in response to a first scan signal (SC1);
a second switch element (Toxide, paras. 0109-0110) that supplies a reference voltage (Vini) to the first node in response to a second scan signal (SC1);
a third switch element (Tem1, paras. 0109-0110) that connects an anode electrode of the light-emitting element (304) to the second node in response to an emission signal (EM);
a compensation circuit (Tar, paras. 0109 and 0115) that supplies an initialization voltage (Var) to a fourth node (a node between Tem2 and 304) in response to a third scan signal (SC3) and supplies a compensation voltage for compensating for a ripple in the initialization voltage (Var) to the second node (para. 0115); and
a first capacitor (Cst, para. 0055) connected between the first node and the second node.
Regarding claim 11, Lin discloses a display device (10, fig. 1, paras. 0043-0045) comprising:
a display panel (14) on which a plurality of data lines (D), a plurality of gate lines (28) intersecting the plurality of data lines, and a plurality of pixel circuits (22) are arranged,
wherein each of the pixel circuits (22) comprises:
a light-emitting element (304, para. 0057);
a driving element (Tdrive, para. 0110) that drives the light-emitting element and includes a first electrode connected to a first node (a node between Tdrive and Tem1), a gate electrode connected to a second node (a node between Tdive and Cst), and a
second electrode connected to a third node (a node between Tdive and Tem2);
a first switch element (Tdata, paras. 0109-0110) that supplies a data voltage (Data) to the second node in response to a first scan signal (SC1);
a second switch element (Toxide, paras. 0109-0110) that supplies a reference voltage (Vini) to the second node in response to a second scan signal (SC1);
a third switch element (Tem1, paras. 0109-0110) that supplies a pixel driving voltage (VDDEL) to the first node in response to a first emission signal (EM);
a fourth switch element (Tem2, , paras. 0109-0110) that connects a fourth node (a node between Tem2 and 304) to the third node in response to a second emission signal (EM);
a compensation circuit (Tar, paras. 0109 and 0115) that supplies an initialization voltage (Var) to the fourth node in response to a third scan signal (SC3) and supplies a compensation voltage for compensating for a ripple in the initialization voltage (Var) to the fourth node (para. 0115); and
a first capacitor (Cst, para. 0055) connected between the second node and the third node.
Regarding claim 19, Lin discloses a display device (10, fig. 1, paras. 0043-0045) comprising:
a display panel (14) on which a plurality of data lines (D), a plurality of gate lines (28) intersecting the plurality of data lines, and a plurality of pixel circuits (22) are arranged,
wherein each of the pixel circuits (22) comprises:
a light-emitting element (304, para. 0057);
a driving element (Tdrive, para. 0110) that drives the light-emitting element and includes a first electrode connected to a first node (a node between Tdrive and Tem1), a gate electrode connected to a second node (a node between Tdive and Cst), and a
second electrode connected to a third node (a node between Tdive and Tem2);
a first switch element (Tdata, paras. 0109-0110) that supplies a data voltage (Data) to the second node in response to a first scan signal (SC1);
a second switch element (Toxide, paras. 0109-0110) that supplies a reference voltage (Vini) to the second node in response to a second scan signal (SC1);
a third switch element (Tem1, paras. 0109-0110) that supplies a pixel driving voltage (VDDEL) to the first node in response to a first emission signal (EM);
a fourth switch element (Tem2, , paras. 0109-0110) that connects a fourth node (a node between Tem2 and 304) to the third node in response to a second emission signal (EM);
a compensation circuit (Tar, paras. 0109 and 0115) that supplies an initialization voltage (Var) to the fourth node in response to a third scan signal (SC3) and supplies a compensation voltage for compensating for a ripple in the initialization voltage (Var) to the fourth node (para. 0115); and
a first capacitor (Cst, para. 0055) connected between the second node and the third node.
Allowable Subject Matter
Claims 2-8, 10, 12-18 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claims 2 and 12 identify the distinct limitations “the compensation circuit comprises: a fifth switch element that supplies an initialization voltage having a ripple of first phase to the fourth node in response to the third scan signal; a sixth switch element that supplies a compensation voltage having a ripple of second phase being a reverse phase of the first phase to the fourth node in response to the third scan signal; and a compensation capacitor connected to a second electrode of the sixth switch element”. Claims 3-4, 6-8, 13-14 and 16-18 are objected for their dependence upon claim 2 and 12. Claim 5 identifies the distinct limitations “the compensation circuit comprises: a fifth switch element that supplies an initialization voltage having a ripple of first phase to the fourth node in response to the third scan signal; a sixth switch element that supplies a compensation voltage having a ripple of second phase being a reverse phase of the first phase to the fourth node in response to a fourth scan signal; and a compensation capacitor connected to a second electrode of the sixth switch element”. Claims 10 and 20 identify the distinct limitations “the compensation circuit comprises: a fifth switch element that supplies an initialization voltage having a ripple of first phase to the second node in response to the third scan signal; a sixth switch element that supplies a compensation voltage having a ripple of second phase being a reverse phase of the first phase to the second node in response to the third scan signal; and a compensation capacitor connected to a second electrode of the sixth switch element”. Claim 15 identifies the distinct limitations “the compensation circuit comprises: a fifth switch element that supplies an initialization voltage having a ripple of first phase to the fourth node in response to the third scan signal; a sixth switch element that supplies a compensation voltage having a ripple of second phase being a reverse phase of the first phase to the fourth node in response to a fourth scan signal; and a compensation capacitor connected to a second electrode of the sixth switch element”.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Lim et al. (US 2024/0257736) disclose a compensation image data calculation unit calculates the magnitude of the compensation image data based on the difference between the voltage level of the initialization voltage of a pixel row in which the ripple occurs and a reference initialization voltage level (fig. 4, abstract).
Son et al. (US 2023/0029234) disclose the sixth switch element M26 is turned on according to the gate-on voltage VGH of the second initialization pulse INIT2 and applies the initialization voltage Vinit1 or the anode voltage Vano to the fourth node n4 in the initialization step Ti, the sensing step Ts, the holding period Th, and the data writing step Tw (fig. 13, paras. 0159-0160).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JENNIFER T NGUYEN whose telephone number is (571)272-7696. The examiner can normally be reached Mon-Fri 7:00-5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Benjamin C Lee can be reached at 5712722963. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JENNIFER T NGUYEN/Primary Examiner, Art Unit 2629
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