Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
In response to this office action, the Examiner respectfully requests that support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line numbers in the specification and/or drawing figure(s). This will assist the Examiner in prosecuting this application.
ALLOWABLE SUBJECT MATTER
Claims 16-20 are allowable. Claim 16-17 are allowable because the cited references do not disclose “in a second display period which is different from the first display period, the third scan signal has a gate-on level pulse, and the first scan signal, the second scan signal, and the fourth scan signal are maintained at a gate-off level“. Claims 18-20 are allowable because the prior art does not disclose “wherein the first scan driver is configured to use a first driving frequency for a first sub active area of the sub active areas and to drive at least a first pixel in the first sub active area based on at least a first control clock signal, the at least a first control clock signal controlling whether or not to output a first gate signal of the first scan driver to the at least a first pixel at a given period, and wherein the second scan driver is configured to use a second driving frequency for a second sub active area of the sub active areas and to drive at least a second pixel in the second sub active area based on at least a second control clock signal, the at least a second control clock signal controlling whether or not to output a second gate signal of the second scan driver to the at least a second pixel at a given period”
Claims 3, 7-15 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim 3 is objected to because the cited references do not disclose “wherein in a period in which at least one control clock signal is toggled between the gate-on level and the gate-off level, the output circuit outputs the gate signal having a gate-on level pulse, and wherein in a period in which at least one control clock signal has the gate-off level, the output circuit outputs the gate signal which is maintained at the gate-off level”. Claim 7 is objected to because the cited references do not disclose “wherein in at least one or more periods, the first control clock signal and the third control clock signal have a same waveform, and wherein in at least one or more periods, the second control clock signal and the fourth control clock signal have a same waveform”. Claims 8-10 are objected to because the cited references do not disclose “wherein the plurality of control clock signals further includes: a fifth control clock signal and a sixth control clock signal, wherein signal levels of the fifth control clock signal and the sixth control clock signal are independently controlled, and phases of the fifth control clock signal and the sixth control clock signal do not overlap each other; and a seventh control clock signal and an eighth control clock signal, wherein signal levels of the seventh control clock signal and the eighth control clock signal are independently controlled, and phases of the seventh control clock signal and the eighth control clock signal do not overlap each other.“ Claims 11-12 and 15 are objected to because the cited references do not disclose “wherein the carry circuit includes: a first transistor which is connected between a first input terminal for receiving the input signal and a first control node, and includes a gate electrode connected to a second input terminal for receiving at least one clock signal; a second transistor which is connected between a second control node and a first power input terminal for receiving a voltage of the first power source, and includes a gate electrode connected to the first input terminal; a third transistor which is connected between the second input terminal and a first QB node, and includes a gate electrode connected to the second control node; a fourth transistor which is connected between the first power input terminal and the first QB node, and includes a gate electrode connected to the first control node; a fifth transistor which is connected between a second power input terminal for receiving a voltage of the second power source and a first output terminal for outputting the carry signal, and includes a gate electrode connected to a first Q node; a sixth transistor which is connected between the first power input terminal and the first output terminal, and includes a gate electrode connected to the first QB node; a first bridge voltage transistor which is connected between the first control node and the first Q node, and includes a gate electrode connected to the second power input terminal; and a first capacitor which is connected between the second input terminal and the second control node”. Claims 13-14 are objected to because the cited references do not disclose “wherein the output circuit includes: a seventh transistor which is connected between a third input terminal for receiving the carry signal and a third control node, and includes a gate electrode connected to a fourth input terminal for receiving at least one control clock signal; an eighth transistor which is connected between a fourth control node and a first power input terminal for receiving a voltage of the first power source, and includes a gate electrode connected to the third input terminal; a ninth transistor which is connected between the fourth input terminal and a second QB node, and includes a gate electrode connected to the fourth control node; a tenth transistor which is connected between the first power input terminal and the second QB node, and includes a gate electrode connected to the third control node; an eleventh transistor which is connected between a second power input terminal for receiving a voltage of the second power source and a second output terminal for outputting the gate signal, and includes a gate electrode connected to a second Q node; a twelfth transistor which is connected between the first power input terminal and the second output terminal, and includes a gate electrode connected to the second QB node; and a second bridge voltage transistor which is connected between the third control node and the second Q node, and includes a gate electrode connected to the second power input terminal; and a fourth capacitor which is connected between the fourth input terminal and the fourth control node”
INFORMATION DISCLOSURE STATEMENT
The information disclosure statements filed 3/10/2026 and 10/02/2025, have been acknowledged and considered by the examiner. Initialed copies of the PTO-1449 forms are included in this correspondence.
CLAIM REJECTIONS - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 , if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
1. Claims 1-2 and 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. US 20220208113 in view of Kim et al. US20250061841.
Consider claim 1. Choi discloses a gate driver fig. 1 gate driver circuit 13, comprising:
a plurality of stages which is cascaded fig. 4 see stages DST1 ST1... STK DST2 and is configured to output a plurality of gate signals based on an input signal fig. 4 SCOUT1-SCOUTn based on VST and [0092] VST and carry signals act as inputs , a plurality of clock signals fig. 4 [0087] clock signal line supplies clock signals CLK which include CRCLK or SCCLK, a plurality of control clock signals fig. 4 [0087] clock signal line supplies clock signals CLK which include CRCLK or SCCLK, a first power source, and a second power source which has a voltage level lower than a voltage level of the first power source fig. 4 GVDD and GVSS,
wherein each of the plurality of stages includes:
a carry circuit see fig. 5 512 which is configured output a carry signal based on the input signal [0092] VST and carry signals act as inputs fig. 4. Also see fig. 5 512, at least one of the plurality of clock signals fig. 4 fig. 5 [0087] clock signal line supplies clock signals CLK which include CRCLK or SCCLK, the first power source, and the second power source fig. 4 and fig. 5 GVDD and GVSS; and
an output circuit fig. 5 514 which is configured output a gate signal based on the carry signal, at least one of the plurality of control clock signals fig. 5 514 outputs based on SCCLK signals, the first power source fig. 5 GVDD, and the second power source fig. 5 GVSS, and
Choi does not explicitly disclose wherein whether to output the gate signal of the output circuit is controlled based on at least one control clock signal.
Kim however discloses wherein whether to output the gate signal of the output circuit is controlled based on at least one control clock signal fig. 4 [0095] the output enable node control circuit 330 and the masking layer 340 is controlled via first and second control clock signals CCLK1 and CCLK2. Also see GC_EN and GC_ENB signals. Fig. 3
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the gate driver of Choi to include wherein whether to output the gate signal of the output circuit is controlled based on at least one control clock signal, as taught by Kim, to reduce power consumption [0006][0090].
Consider claim 2. Choi as modified by Kim disclose the gate driver according to claim 1, wherein each of the plurality of control clock signals has a waveform which is toggled between a gate-on level and a gate-off level or is maintained at a gate-off level Kim fig 5 see waveform for CCLK1 CCLK2.
Motivation to combine is similar to motivation in claim 1.
Consider claim 4. Choi as modified by Kim disclose the gate driver according to claim 1, wherein the plurality of control clock signals has a first control clock signal and a second control clock signal Kim fig. 4 fig. 5 fig. 11 CCLK1 CCLK2, wherein signal levels of the first control clock signal and the second control clock signal are independently controlled Kim fig. 5, and phases of the first control clock signal and the second control clock signal do not overlap each other Kim fig. 4 fig. 5 CCLK1 and CCLK2 do not overlap also fig. 11 GC_EN and GC_ENB do not overlap, wherein the output circuit included in each odd-numbered stage, among the plurality of stages, is configured to receive the first control clock signal, and wherein the output circuit included in each even-numbered stage, among the plurality of stages, is configured to receive the second control clock signal fig. 5 CCLK1 CCLK2 and GC_EN and GC_ENB are in every stage and thus are in both even and odd stages as claimed.
Motivation to combine is similar to the motivation in claim 1.
Consider claim 5. Choi as modified by Kim disclose the gate driver according to claim 1, wherein the plurality of control clock signals includes: a first control clock signal and a second control clock signal Kim fig. 4 fig. 5 fig. 11 CCLK1 CCLK2, wherein signal levels of the first control clock signal and the second control clock signal are independently controlled, and phases of the first control clock signal and the second control clock signal do not overlap each other Kim fig. 4 fig. 5 CCLK1 and CCLK2 do not overlap also fig. 11 GC_EN and GC_ENB do not overlap; and a third control clock signal and a fourth control clock signal fig. 11 GC_EN and GC_ENB, wherein signal levels of the third control clock signal and the fourth control clock signal are independently controlled fig. 11 GC_EN and GC_ENB are separate, and phases of the third control clock signal and the fourth control clock signal do not overlap each other fig. 11 GC_EN and GC_ENB do not overlap.
Consider claim 6. Choi as modified by Kim disclose the gate driver according to claim 5, wherein the output circuit included in each of a k-th stage (wherein k is an integer larger than 0) and a k+2-th stage, among the plurality of stages, is configured to receive the first control clock signal fig. 5 CCLK1 CCLK2 and GC_EN and GC_ENB are in every stage and thus are in both even and odd stages as claimed, the output circuit included in each of a k+1-th stage and a k+3-th stage, among the plurality of stages is configured to receive the second control clock signal fig. 5 CCLK1 CCLK2 and GC_EN and GC_ENB are in every stage and thus are in both even and odd stages as claimed. , the output circuit included in each of a k+4-th stage and a k+6-th stage, among the plurality of stages, is configured to receive the third control clock signal fig. 5 CCLK1 CCLK2 and GC_EN and GC_ENB are in every stage and thus are in both even and odd stages as claimed., and the output circuit included in each of a k+5-th stage and a k+7-th stage, among the plurality of stages, is configured to receive the fourth control clock signal fig. 5 CCLK1 CCLK2 and GC_EN and GC_ENB are in every stage and thus are in both even and odd stages as claimed.
Motivation to combine is similar to the motivation in claim 1.
IV.CONCLUSION
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20250157393 discloses a display device with gate driver comprising first to fourth scan drivers.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to IBRAHIM A KHAN whose telephone number is (571)270-7998. The examiner can normally be reached on 10am-6pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Nitin Patel can be reached on 571-272-7677. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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IBRAHIM A. KHAN
Primary Examiner
Art Unit 2628
/IBRAHIM A KHAN/ 08/25/2026Primary Examiner, Art Unit 2628
Prosecution Insights