Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
A non-patent literature on the information disclosure statement filed 10/02/2025 fails to comply with MPEP § 609 which requires the date and place of publication for each non-patent literature. Applicant is advised that the date of any re-submission of any item of information contained in this information disclosure statement or the submission of any missing element(s) will be the date of submission for purposes of determining compliance with the requirements based on the time of filing the statement, including all certification requirements for statements under 37 CFR 1.97(e). See MPEP § 609.05(a).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-8 and 17-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ishii et al. (US 2011/0243325 A1, hereinafter “Ishii”).
As to claim 1, Ishii (Fig. 16) discloses a display device (12-1) comprising:
pixels (125) arranged in rows and columns (Para. 0258);
a gate driver (123) connected to the rows of the pixels through first scan lines (121) and second scan lines (121B) respectively corresponding to the first scan lines (Para. 0259); and
a data driver (124) connected to the columns of the pixels through data lines (122; Para. 0260),
wherein the pixels are configured to:
receive target voltages through the data lines in a first interval (storage capacitances write interval period; Para. 0263), and
charge pixel voltages based on the target voltages in a second interval (Para. 0264).
As to claim 2, Ishii (Fig. 16) discloses the display device of claim 1, wherein the pixels include:
first transistors (127A) including a gate connected to a corresponding first scan line (121) among the first scan lines, a first terminal (source terminal) connected to a corresponding data line (122) among the data lines, and a second terminal (drain terminal); and
second transistors (127B) including a gate connected to a corresponding second scan line (121B) among the second scan lines, a first terminal connected to the second terminal of the first transistors (126A), and a second terminal (drain terminal).
As to claim 3, Ishii (Fig. 16) discloses the display device of claim 2, wherein the second transistors (127B) are simultaneously turned on based on a voltage of the corresponding second scan line among the second scan lines (Para. 0264).
As to claim 4, Ishii (Fig. 16) discloses the display device of claim 3, wherein the pixels include first capacitors (126A) and second capacitors (126B),
wherein each of the first capacitors (126A) is connected to the second terminal (drain of 127A) of a corresponding first transistor (127A) among the first transistors and the first terminal (source of 127B) of a corresponding second transistor among the second transistors, and
wherein each of the second capacitors (126B) is connected to the second terminal of a corresponding second transistor (127B) among the second transistors.
As to claim 5, Ishii (Fig. 16) discloses the display device of claim 4, wherein the target voltages represent data voltages for inputting data corresponding to a first frame (para. 0264).
As to claim 6, Ishii (Fig. 14) discloses the display device of claim 5, wherein in the first interval, the first transistors are sequentially turned on based on a voltage of the corresponding first scan line among the first scan lines (scanning first picture data; Para. 0247, 0266).
As to claim 7, Ishii (Fig. 16) discloses the display device of claim 6, wherein in response to the first transistors (127A) being turned on in the first interval, the first capacitors (126A) charge the target voltages (Para. 0263-0264).
As to claim 8, Ishii (Fig. 16) discloses the display device of claim 7, wherein in response to the second transistors (127B) being turned on in the second interval, the second capacitors (126B) charge the pixel voltages based on the target voltages (Para. 0264).
As to claim 17, Ishii (Fig. 16) discloses a method of operating a display panel including first transistors (127A), second transistors (127B), first capacitors (126A), and second capacitors (126B), the method comprising:
sequentially turning on the first transistors through first scan lines in a first interval (Fig. 17 element scanning first picture data);
receiving, by the first transistors, target voltages through data lines in response to turning on the first transistors in the first interval (Para. 0263);
charging, by the first capacitors, the target voltages in the first interval (Para. 0263);
simultaneously turning on the second transistors in a second interval (Para. 0264, 0267, response interval); and
charging, by the second capacitors, pixel voltages based on the target voltages in response to turning on the second transistors in the second interval (Para. 0264).
As to claim 18, Ishii discloses the method of claim 17, wherein the target voltages represent data voltages for inputting data corresponding to a first frame (Fig. 17 element display of first picture; para. 0263).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 9-16 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Ishii as applied to claims 1 and 17 above, and further in view of Bae et al. (US 2013/0342478 A1, hereinafter “Bae”).
As to claim 9, Ishii (Fig. 17) discloses the display device of claim 8, wherein, in a third interval (second liquid crystal response interval), the pixels are configured to:
initialize data corresponding to the first frame in response to the reset voltages (Para. 0268).
Ishii does not disclose receive reset voltages through the data lines.
However, Bae (Fig. 14) teaches receive reset voltages (Vreset) through the data lines (D1-D4).
It would have been obvious to one of ordinary skill in the art to combine the teaching of Bae to receive reset signal through data lines in the device disclosed by Ishii. The motivation would have been for design incentives to reduce flicker (Bae; Para. 0043).
As to claim 10, Ishii discloses the display device of claim 9, wherein the pixels display the first frame in the second interval (Fig. 17 element “display of first picture”).
As to claim 11, Ishii does not disclose the display device of claim 4, wherein each of the target voltages includes a reset voltage for initializing data corresponding to a first frame and a data voltage for inputting data corresponding to a second frame.
However, Bae (Fig. 15) teaches wherein each of the target voltages includes a reset voltage (Vreset) for initializing data corresponding to a first frame (1 frame) and a data voltage for inputting data corresponding to a second frame (T1; data voltage for the second frame).
It would have been obvious to one of ordinary skill in the art to combine the teaching of Bae to receive reset signal through data lines in the device disclosed by Ishii. The motivation would have been for design incentives to reduce flicker (Bae; Para. 0043).
As to claim 12, Ishii (Fig. 17) discloses the display device of claim 11, wherein in the first interval (scanning of first picture data), the first transistors (Fig. 16 element 127A) are sequentially turned on based on a voltage of the corresponding first scan line among the first scan lines (Para. 0263-0264).
As to claim 13, Ishii (Fig. 16) discloses the display device of claim 12, wherein in response to the first transistors (127A) being turned on in the first interval, the first capacitors (126A) charge the target voltages (Para. 0263).
As to claim 14, Ishii (Fig. 16) discloses the display device of claim 13, wherein in the first interval, the second capacitors (126B) are in a charged state with first pixel voltages corresponding to the first frame (Para. 0268), and
the pixels display the first frame (Para. 0264).
As to claim 15, Ishii (Fig. 17) discloses the display device of claim 14, wherein in response to the second transistors being turned on in the second interval (scanning second pixel data), the second capacitors are charged with second pixel voltages corresponding to the second frame (para. 0268).
As to claim 16, Ishii (Fig. 17) discloses the display device of claim 15, wherein in response to the second transistors being charged with the second pixel voltages in the second interval, the pixels display the second frame (Display of second picture; Para. 0268).
As to claim 19, Ishii discloses the method of claim 18, further comprising:
initializing data corresponding to the first frame in response to the reset voltages (Para. 0268).
Ishii does not disclose receiving, by the first transistors, reset voltages through the data lines in a third interval.
However, Bae (Fig. 9) teaches receiving, by the first transistors (TFT), reset voltages (Fig. 14 element Vreset) through the data lines (D1-D4) in a third interval (T3).
It would have been obvious to one of ordinary skill in the art to combine the teaching of Bae to receive reset signal through data lines in the device disclosed by Ishii. The motivation would have been for design incentives to reduce flicker (Bae; Para. 0043).
As to claim 20, Ishii does not disclose the method of claim 17, wherein each of the target voltages includes a reset voltage for initializing data corresponding to a first frame and a data voltage for inputting data corresponding to a second frame.
However, Bae (Fig. 15) teaches wherein each of the target voltages includes a reset voltage (Vreset) for initializing data corresponding to a first frame (1 frame) and a data voltage for inputting data corresponding to a second frame (T1; data voltage for the second frame).
It would have been obvious to one of ordinary skill in the art to combine the teaching of Bae to receive reset signal through data lines in the device disclosed by Ishii. The motivation would have been for design incentives to reduce flicker (Bae; Para. 0043).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant‘s disclosure.
Kimura discloses three transistors in a LCD pixel circuit (Fig. 6).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BIPIN GYAWALI whose telephone number is (571)272-1597. The examiner can normally be reached M-F 9:00-5:30 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Will Boddie can be reached at 571-272-0666. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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BIPIN GYAWALI
Primary Examiner
Art Unit 2625
/BIPIN GYAWALI/Primary Examiner, Art Unit 2625
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